sam.sv: correct A0 -> bank[0], A1 -> bank[1]

It was a mistake in the schematic that A0 went to bank[1] and vice
versa. It would hardly have been the strangest thing in this device...

fpga/sam.sv

@@ -294,7 +294,7 @@ module samagnum (
    ff_7474s u9e2l1a(.fast_clk (fast_clk),
 		    .d(a[1]), .c(bank_sel), .s_n(1'b1), .r_n(reset_bank),
 		    .q_p(u9e2l1a_q), .q_n());
-   assign bank[0] = u9e2l1a_q;
+   assign bank[1] = u9e2l1a_q;
 
    ff_7474s u9e2l1b(.fast_clk (fast_clk),
 		    .d(clk), .c(u11d), .s_n(u12b), .r_n(1'b1),
@@ -306,7 +306,7 @@ module samagnum (
    ff_7474s u9e2h1a(.fast_clk (fast_clk),
 		    .d(a[0]), .c(bank_sel), .s_n(1'b1), .r_n(reset_bank),
 		    .q_p(u9e2h1a_q), .q_n());
-   assign bank[1] = u9e2h1a_q;
+   assign bank[0] = u9e2h1a_q;
    // U9_E2_H1B unconnected
 
    // U9_E3 74LS74