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fpga/iodevs.vh

@@ -19,59 +19,71 @@
 
 	wire [31:0] iodev_rdata_sys;
 	wire [ 0:0] iodev_valid_sys = iodev_valid[0:0];
+	localparam [31:0] iodev_sys_base = 32'hfffff800;
 	tri1 [ 0:0] iodev_wait_n_sys;
 
 	wire [31:0] iodev_rdata_abc;
 	wire [ 0:0] iodev_irq_abc;
 	wire [ 0:0] iodev_valid_abc = iodev_valid[1:1];
+	localparam [31:0] iodev_abc_base = 32'hfffff880;
 	tri1 [ 0:0] iodev_wait_n_abc;
 
 	wire [31:0] iodev_rdata_abcmemmap;
 	wire [ 0:0] iodev_valid_abcmemmap = xdev_valid[0:0];
+	localparam [31:0] iodev_abcmemmap_base = 32'hc0000000;
 	tri1 [ 0:0] iodev_wait_n_abcmemmap;
 
 	wire [31:0] iodev_rdata_sysclock;
 	wire [ 0:0] iodev_irq_sysclock;
 	wire [ 0:0] iodev_valid_sysclock = iodev_valid[2:2];
+	localparam [31:0] iodev_sysclock_base = 32'hfffff900;
 	tri1 [ 0:0] iodev_wait_n_sysclock;
 
 	wire [31:0] iodev_rdata_tty;
 	wire [ 1:0] iodev_irq_tty;
 	wire [ 0:0] iodev_valid_tty = iodev_valid[3:3];
+	localparam [31:0] iodev_tty_base = 32'hfffff980;
 	tri1 [ 0:0] iodev_wait_n_tty;
 
 	wire [31:0] iodev_rdata_usbdesc;
 	wire [ 0:0] iodev_valid_usbdesc = xdev_valid[1:1];
+	localparam [31:0] iodev_usbdesc_base = 32'hd0000000;
 	tri1 [ 0:0] iodev_wait_n_usbdesc;
 
 	wire [31:0] iodev_rdata_romcopy;
 	wire [ 0:0] iodev_irq_romcopy;
 	wire [ 0:0] iodev_valid_romcopy = iodev_valid[4:4];
+	localparam [31:0] iodev_romcopy_base = 32'hfffffa00;
 	tri1 [ 0:0] iodev_wait_n_romcopy;
 
 	wire [31:0] iodev_rdata_sdcard;
 	wire [ 0:0] iodev_irq_sdcard;
 	wire [ 0:0] iodev_valid_sdcard = iodev_valid[5:5];
+	localparam [31:0] iodev_sdcard_base = 32'hfffffa80;
 	tri1 [ 0:0] iodev_wait_n_sdcard;
 
 	wire [31:0] iodev_rdata_i2c;
 	wire [ 0:0] iodev_irq_i2c;
 	wire [ 0:0] iodev_valid_i2c = iodev_valid[6:6];
+	localparam [31:0] iodev_i2c_base = 32'hfffffb00;
 	tri1 [ 0:0] iodev_wait_n_i2c;
 
 	wire [31:0] iodev_rdata_esp;
 	wire [ 0:0] iodev_irq_esp;
 	wire [ 0:0] iodev_valid_esp = iodev_valid[7:7];
+	localparam [31:0] iodev_esp_base = 32'hfffffb80;
 	tri1 [ 0:0] iodev_wait_n_esp;
 
 	wire [31:0] iodev_rdata_random;
 	wire [ 0:0] iodev_irq_random;
 	wire [ 0:0] iodev_valid_random = iodev_valid[8:8];
+	localparam [31:0] iodev_random_base = 32'hfffffc00;
 	tri1 [ 0:0] iodev_wait_n_random;
 
 	wire [31:0] iodev_rdata_vjtag;
 	wire [ 0:0] iodev_irq_vjtag;
 	wire [ 0:0] iodev_valid_vjtag = iodev_valid[9:9];
+	localparam [31:0] iodev_vjtag_base = 32'hfffffc80;
 	tri1 [ 0:0] iodev_wait_n_vjtag;
 
 	// I/O input MUX

fpga/max80.qpf

@@ -19,12 +19,12 @@
 #
 # Quartus Prime
 # Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
-# Date created = 03:03:51  February 05, 2023
+# Date created = 22:54:03  February 09, 2023
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "22.1"
-DATE = "03:03:51  February 05, 2023"
+DATE = "22:54:03  February 09, 2023"
 
 # Revisions
 

fpga/v1.qsf

@@ -5,3 +5,6 @@
 #   set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v1_main.qsf
 
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v1_main.qsf
+set_global_assignment -name TOP_LEVEL_ENTITY v1
+
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"

fpga/v2.qsf

@@ -5,3 +5,6 @@
 #   set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v2_main.qsf
 #
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v2_main.qsf
+set_global_assignment -name TOP_LEVEL_ENTITY v2
+
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"