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@@ -1,5 +1,5 @@
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Fitter report for max80
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-Thu Jul 29 01:17:51 2021
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+Thu Jul 29 09:26:56 2021
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Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
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@@ -73,15 +73,15 @@ https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Fitter Summary ;
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+------------------------------------+---------------------------------------------+
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-; Fitter Status ; Successful - Thu Jul 29 01:17:51 2021 ;
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+; Fitter Status ; Successful - Thu Jul 29 09:26:56 2021 ;
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; Quartus Prime Version ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
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; Revision Name ; max80 ;
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; Top-level Entity Name ; max80 ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE15F17C8 ;
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; Timing Models ; Final ;
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-; Total logic elements ; 328 / 15,408 ( 2 % ) ;
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-; Total combinational functions ; 277 / 15,408 ( 2 % ) ;
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+; Total logic elements ; 329 / 15,408 ( 2 % ) ;
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+; Total combinational functions ; 278 / 15,408 ( 2 % ) ;
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; Dedicated logic registers ; 218 / 15,408 ( 1 % ) ;
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; Total registers ; 229 ;
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; Total pins ; 134 / 166 ( 81 % ) ;
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@@ -166,7 +166,7 @@ https://fpgasoftware.intel.com/eula.
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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-; Processor 2 ; 0.6% ;
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+; Processor 2 ; 0.8% ;
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+----------------------------+-------------+
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@@ -217,8 +217,8 @@ https://fpgasoftware.intel.com/eula.
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; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
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+---------------------+--------------------+----------------------------+--------------------------+
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; Placement (by node) ; ; ; ;
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-; -- Requested ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 ) ;
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-; -- Achieved ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 ) ;
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+; -- Requested ; 0.00 % ( 0 / 817 ) ; 0.00 % ( 0 / 817 ) ; 0.00 % ( 0 / 817 ) ;
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+; -- Achieved ; 0.00 % ( 0 / 817 ) ; 0.00 % ( 0 / 817 ) ; 0.00 % ( 0 / 817 ) ;
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; ; ; ; ;
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; Routing (by net) ; ; ; ;
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; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
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@@ -241,7 +241,7 @@ https://fpgasoftware.intel.com/eula.
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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-; Top ; 0.00 % ( 0 / 787 ) ; N/A ; Source File ; N/A ; ;
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+; Top ; 0.00 % ( 0 / 788 ) ; N/A ; Source File ; N/A ; ;
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; hard_block:auto_generated_inst ; 0.00 % ( 0 / 29 ) ; N/A ; Source File ; N/A ; ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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@@ -257,26 +257,26 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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+---------------------------------------------+----------------------+
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; Resource ; Usage ;
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+---------------------------------------------+----------------------+
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-; Total logic elements ; 328 / 15,408 ( 2 % ) ;
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-; -- Combinational with no register ; 110 ;
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+; Total logic elements ; 329 / 15,408 ( 2 % ) ;
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+; -- Combinational with no register ; 111 ;
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; -- Register only ; 51 ;
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; -- Combinational with a register ; 167 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 105 ;
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; -- 3 input functions ; 65 ;
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-; -- <=2 input functions ; 107 ;
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+; -- <=2 input functions ; 108 ;
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; -- Register only ; 51 ;
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; ; ;
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; Logic elements by mode ; ;
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-; -- normal mode ; 220 ;
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-; -- arithmetic mode ; 57 ;
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+; -- normal mode ; 222 ;
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+; -- arithmetic mode ; 56 ;
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; ; ;
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; Total registers* ; 229 / 16,166 ( 1 % ) ;
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; -- Dedicated logic registers ; 218 / 15,408 ( 1 % ) ;
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; -- I/O registers ; 11 / 758 ( 1 % ) ;
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; ; ;
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-; Total LABs: partially or completely used ; 30 / 963 ( 3 % ) ;
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+; Total LABs: partially or completely used ; 29 / 963 ( 3 % ) ;
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; Virtual pins ; 0 ;
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; I/O pins ; 134 / 166 ( 81 % ) ;
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; -- Clock pins ; 4 / 3 ( 133 % ) ;
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@@ -295,11 +295,11 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; Oscillator blocks ; 0 / 1 ( 0 % ) ;
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; Impedance control blocks ; 0 / 4 ( 0 % ) ;
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; Average interconnect usage (total/H/V) ; 0.3% / 0.3% / 0.3% ;
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-; Peak interconnect usage (total/H/V) ; 2.2% / 2.5% / 1.7% ;
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+; Peak interconnect usage (total/H/V) ; 2.0% / 2.0% / 2.0% ;
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; Maximum fan-out ; 90 ;
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; Highest non-global fan-out ; 42 ;
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-; Total fan-out ; 1632 ;
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-; Average fan-out ; 1.89 ;
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+; Total fan-out ; 1640 ;
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+; Average fan-out ; 1.90 ;
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+---------------------------------------------+----------------------+
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* Register count does not include registers inside RAM blocks or DSP blocks.
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@@ -312,26 +312,26 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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+---------------------------------------------+---------------------+--------------------------------+
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; Difficulty Clustering Region ; Low ; Low ;
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; ; ; ;
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-; Total logic elements ; 322 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % ) ;
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-; -- Combinational with no register ; 104 ; 6 ;
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+; Total logic elements ; 323 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % ) ;
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+; -- Combinational with no register ; 105 ; 6 ;
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; -- Register only ; 51 ; 0 ;
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; -- Combinational with a register ; 167 ; 0 ;
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; ; ; ;
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; Logic element usage by number of LUT inputs ; ; ;
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; -- 4 input functions ; 102 ; 3 ;
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; -- 3 input functions ; 65 ; 0 ;
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-; -- <=2 input functions ; 104 ; 3 ;
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+; -- <=2 input functions ; 105 ; 3 ;
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; -- Register only ; 51 ; 0 ;
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; ; ; ;
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; Logic elements by mode ; ; ;
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-; -- normal mode ; 214 ; 6 ;
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-; -- arithmetic mode ; 57 ; 0 ;
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+; -- normal mode ; 216 ; 6 ;
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+; -- arithmetic mode ; 56 ; 0 ;
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; ; ; ;
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; Total registers ; 221 ; 8 ;
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; -- Dedicated logic registers ; 218 / 15408 ( 1 % ) ; 0 / 15408 ( 0 % ) ;
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; -- I/O registers ; 6 ; 16 ;
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; ; ; ;
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-; Total LABs: partially or completely used ; 30 / 963 ( 3 % ) ; 1 / 963 ( < 1 % ) ;
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+; Total LABs: partially or completely used ; 29 / 963 ( 3 % ) ; 1 / 963 ( < 1 % ) ;
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; ; ; ;
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; Virtual pins ; 0 ; 0 ;
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; I/O pins ; 126 ; 8 ;
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@@ -349,8 +349,8 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; -- Registered Output Connections ; 8 ; 0 ;
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; ; ; ;
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; Internal Connections ; ; ;
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-; -- Total Connections ; 1596 ; 291 ;
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-; -- Registered Connections ; 766 ; 0 ;
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+; -- Total Connections ; 1604 ; 291 ;
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+; -- Registered Connections ; 779 ; 0 ;
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; ; ; ;
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; External Connections ; ; ;
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; -- Top ; 90 ; 247 ;
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@@ -1023,12 +1023,12 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
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+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
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; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
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-; |max80 ; 328 (67) ; 218 (66) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 134 ; 0 ; 110 (1) ; 51 (1) ; 167 (50) ; |max80 ; max80 ; work ;
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+; |max80 ; 329 (68) ; 218 (66) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 134 ; 0 ; 111 (2) ; 51 (1) ; 167 (50) ; |max80 ; max80 ; work ;
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; |hdmitx:hdmitx| ; 119 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 41 (0) ; 68 (0) ; |max80|hdmitx:hdmitx ; hdmitx ; work ;
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; |altlvds_tx:ALTLVDS_TX_component| ; 119 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 41 (0) ; 68 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ; altlvds_tx ; work ;
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-; |hdmitx_lvds_tx:auto_generated| ; 119 (61) ; 109 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (1) ; 41 (40) ; 68 (19) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ; hdmitx_lvds_tx ; work ;
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-; |hdmitx_cntr:cntr13| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 3 (3) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13 ; hdmitx_cntr ; work ;
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-; |hdmitx_cntr:cntr2| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2 ; hdmitx_cntr ; work ;
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+; |hdmitx_lvds_tx:auto_generated| ; 119 (60) ; 109 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (1) ; 41 (40) ; 68 (19) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ; hdmitx_lvds_tx ; work ;
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+; |hdmitx_cntr:cntr13| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13 ; hdmitx_cntr ; work ;
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+; |hdmitx_cntr:cntr2| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 3 (3) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2 ; hdmitx_cntr ; work ;
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; |hdmitx_ddio_out1:outclock_ddio| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio ; hdmitx_ddio_out1 ; work ;
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; |hdmitx_ddio_out:ddio_out| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out ; hdmitx_ddio_out ; work ;
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; |hdmitx_shift_reg1:shift_reg23| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23 ; hdmitx_shift_reg1 ; work ;
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@@ -1046,8 +1046,8 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
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; |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ; pll_altpll_dyn_phase_le1 ; work ;
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; |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ; pll_altpll_dyn_phase_le ; work ;
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; |tmdsenc:hdmitmds[0].enc| ; 51 (51) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 3 (3) ; 18 (18) ; |max80|tmdsenc:hdmitmds[0].enc ; tmdsenc ; work ;
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-; |tmdsenc:hdmitmds[1].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 3 (3) ; 15 (15) ; |max80|tmdsenc:hdmitmds[1].enc ; tmdsenc ; work ;
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-; |tmdsenc:hdmitmds[2].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 16 (16) ; |max80|tmdsenc:hdmitmds[2].enc ; tmdsenc ; work ;
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+; |tmdsenc:hdmitmds[1].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 16 (16) ; |max80|tmdsenc:hdmitmds[1].enc ; tmdsenc ; work ;
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+; |tmdsenc:hdmitmds[2].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 3 (3) ; 15 (15) ; |max80|tmdsenc:hdmitmds[2].enc ; tmdsenc ; work ;
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+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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@@ -1292,28 +1292,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
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; clock_48 ; PIN_M15 ; 1 ; Clock ; no ; -- ; -- ; -- ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; FF_X23_Y21_N17 ; 41 ; Clock enable ; no ; -- ; -- ; -- ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; FF_X19_Y23_N19 ; 41 ; Clock enable ; no ; -- ; -- ; -- ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
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; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; Clock ; yes ; Global Clock ; GCLK7 ; -- ;
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; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; Clock ; yes ; Global Clock ; GCLK9 ; -- ;
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; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked ; PLL_2 ; 13 ; Async. clear ; no ; -- ; -- ; -- ;
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-; rst_n ; FF_X40_Y27_N27 ; 75 ; Async. clear ; yes ; Global Clock ; GCLK5 ; -- ;
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-; tmdsenc:hdmitmds[0].enc|denreg ; FF_X26_Y23_N7 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
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+; rst_n ; FF_X20_Y28_N1 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
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+; rst_n ; FF_X20_Y28_N1 ; 75 ; Async. clear ; yes ; Global Clock ; GCLK12 ; -- ;
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+; tmdsenc:hdmitmds[0].enc|denreg ; FF_X22_Y22_N15 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
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+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
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-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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-; Global & Other Fast Signals ;
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-+-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
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-; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
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-+-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; 0 ; Global Clock ; GCLK3 ; -- ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; 0 ; Global Clock ; GCLK4 ; -- ;
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-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ;
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-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; 0 ; Global Clock ; GCLK7 ; -- ;
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-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; 0 ; Global Clock ; GCLK9 ; -- ;
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-; rst_n ; FF_X40_Y27_N27 ; 75 ; 0 ; Global Clock ; GCLK5 ; -- ;
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-+-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
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++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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+; Global & Other Fast Signals ;
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++-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
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+; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
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++-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; 0 ; Global Clock ; GCLK3 ; -- ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; 0 ; Global Clock ; GCLK4 ; -- ;
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+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ;
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+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; 0 ; Global Clock ; GCLK7 ; -- ;
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+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; 0 ; Global Clock ; GCLK9 ; -- ;
|
|
|
+; rst_n ; FF_X20_Y28_N1 ; 75 ; 0 ; Global Clock ; GCLK12 ; -- ;
|
|
|
++-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
|
|
|
|
|
|
+------------------------------------------------+
|
|
|
@@ -1321,24 +1322,24 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
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|
+-----------------------+------------------------+
|
|
|
; Routing Resource Type ; Usage ;
|
|
|
+-----------------------+------------------------+
|
|
|
-; Block interconnects ; 241 / 47,787 ( < 1 % ) ;
|
|
|
-; C16 interconnects ; 5 / 1,804 ( < 1 % ) ;
|
|
|
-; C4 interconnects ; 72 / 31,272 ( < 1 % ) ;
|
|
|
-; Direct links ; 89 / 47,787 ( < 1 % ) ;
|
|
|
+; Block interconnects ; 262 / 47,787 ( < 1 % ) ;
|
|
|
+; C16 interconnects ; 6 / 1,804 ( < 1 % ) ;
|
|
|
+; C4 interconnects ; 89 / 31,272 ( < 1 % ) ;
|
|
|
+; Direct links ; 97 / 47,787 ( < 1 % ) ;
|
|
|
; Global clocks ; 6 / 20 ( 30 % ) ;
|
|
|
-; Local interconnects ; 205 / 15,408 ( 1 % ) ;
|
|
|
-; R24 interconnects ; 5 / 1,775 ( < 1 % ) ;
|
|
|
-; R4 interconnects ; 103 / 41,310 ( < 1 % ) ;
|
|
|
+; Local interconnects ; 186 / 15,408 ( 1 % ) ;
|
|
|
+; R24 interconnects ; 8 / 1,775 ( < 1 % ) ;
|
|
|
+; R4 interconnects ; 98 / 41,310 ( < 1 % ) ;
|
|
|
+-----------------------+------------------------+
|
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
|
; LAB Logic Elements ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; Number of Logic Elements (Average = 10.93) ; Number of LABs (Total = 30) ;
|
|
|
+; Number of Logic Elements (Average = 11.34) ; Number of LABs (Total = 29) ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; 1 ; 5 ;
|
|
|
-; 2 ; 1 ;
|
|
|
+; 1 ; 3 ;
|
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|
+; 2 ; 2 ;
|
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|
; 3 ; 1 ;
|
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|
; 4 ; 0 ;
|
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|
; 5 ; 0 ;
|
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|
@@ -1346,10 +1347,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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; 7 ; 1 ;
|
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; 8 ; 1 ;
|
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; 9 ; 0 ;
|
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-; 10 ; 3 ;
|
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+; 10 ; 2 ;
|
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|
; 11 ; 0 ;
|
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|
-; 12 ; 0 ;
|
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|
-; 13 ; 3 ;
|
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+; 12 ; 2 ;
|
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|
+; 13 ; 2 ;
|
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|
; 14 ; 2 ;
|
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|
; 15 ; 2 ;
|
|
|
; 16 ; 11 ;
|
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|
@@ -1359,28 +1360,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+-------------------------------------------------------------------+
|
|
|
; LAB-wide Signals ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
-; LAB-wide Signals (Average = 1.37) ; Number of LABs (Total = 30) ;
|
|
|
+; LAB-wide Signals (Average = 1.52) ; Number of LABs (Total = 29) ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
-; 1 Async. clear ; 10 ;
|
|
|
-; 1 Clock ; 18 ;
|
|
|
-; 1 Clock enable ; 2 ;
|
|
|
+; 1 Async. clear ; 11 ;
|
|
|
+; 1 Clock ; 19 ;
|
|
|
+; 1 Clock enable ; 4 ;
|
|
|
; 1 Sync. clear ; 3 ;
|
|
|
-; 2 Clocks ; 8 ;
|
|
|
+; 2 Clocks ; 7 ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------------+
|
|
|
; LAB Signals Sourced ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
-; Number of Signals Sourced (Average = 17.93) ; Number of LABs (Total = 30) ;
|
|
|
+; Number of Signals Sourced (Average = 18.41) ; Number of LABs (Total = 29) ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
; 0 ; 0 ;
|
|
|
-; 1 ; 3 ;
|
|
|
-; 2 ; 2 ;
|
|
|
+; 1 ; 1 ;
|
|
|
+; 2 ; 3 ;
|
|
|
; 3 ; 1 ;
|
|
|
-; 4 ; 1 ;
|
|
|
+; 4 ; 0 ;
|
|
|
; 5 ; 0 ;
|
|
|
-; 6 ; 0 ;
|
|
|
+; 6 ; 1 ;
|
|
|
; 7 ; 1 ;
|
|
|
; 8 ; 0 ;
|
|
|
; 9 ; 0 ;
|
|
|
@@ -1388,23 +1389,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
; 11 ; 0 ;
|
|
|
; 12 ; 0 ;
|
|
|
; 13 ; 0 ;
|
|
|
-; 14 ; 0 ;
|
|
|
+; 14 ; 1 ;
|
|
|
; 15 ; 0 ;
|
|
|
-; 16 ; 1 ;
|
|
|
+; 16 ; 0 ;
|
|
|
; 17 ; 0 ;
|
|
|
-; 18 ; 0 ;
|
|
|
-; 19 ; 4 ;
|
|
|
+; 18 ; 1 ;
|
|
|
+; 19 ; 3 ;
|
|
|
; 20 ; 1 ;
|
|
|
-; 21 ; 2 ;
|
|
|
-; 22 ; 0 ;
|
|
|
-; 23 ; 4 ;
|
|
|
-; 24 ; 2 ;
|
|
|
+; 21 ; 0 ;
|
|
|
+; 22 ; 3 ;
|
|
|
+; 23 ; 5 ;
|
|
|
+; 24 ; 1 ;
|
|
|
; 25 ; 1 ;
|
|
|
-; 26 ; 2 ;
|
|
|
-; 27 ; 0 ;
|
|
|
-; 28 ; 2 ;
|
|
|
-; 29 ; 1 ;
|
|
|
-; 30 ; 1 ;
|
|
|
+; 26 ; 1 ;
|
|
|
+; 27 ; 1 ;
|
|
|
+; 28 ; 1 ;
|
|
|
+; 29 ; 0 ;
|
|
|
+; 30 ; 2 ;
|
|
|
; 31 ; 1 ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
|
|
|
@@ -1412,53 +1413,57 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+--------------------------------------------------------------------------------+
|
|
|
; LAB Signals Sourced Out ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
-; Number of Signals Sourced Out (Average = 4.80) ; Number of LABs (Total = 30) ;
|
|
|
+; Number of Signals Sourced Out (Average = 5.38) ; Number of LABs (Total = 29) ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
; 0 ; 1 ;
|
|
|
-; 1 ; 9 ;
|
|
|
-; 2 ; 4 ;
|
|
|
+; 1 ; 4 ;
|
|
|
+; 2 ; 6 ;
|
|
|
; 3 ; 4 ;
|
|
|
; 4 ; 2 ;
|
|
|
-; 5 ; 1 ;
|
|
|
-; 6 ; 0 ;
|
|
|
+; 5 ; 3 ;
|
|
|
+; 6 ; 1 ;
|
|
|
; 7 ; 1 ;
|
|
|
-; 8 ; 1 ;
|
|
|
+; 8 ; 0 ;
|
|
|
; 9 ; 0 ;
|
|
|
; 10 ; 1 ;
|
|
|
; 11 ; 1 ;
|
|
|
; 12 ; 2 ;
|
|
|
-; 13 ; 1 ;
|
|
|
+; 13 ; 0 ;
|
|
|
; 14 ; 1 ;
|
|
|
; 15 ; 1 ;
|
|
|
+; 16 ; 0 ;
|
|
|
+; 17 ; 0 ;
|
|
|
+; 18 ; 1 ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
|
; LAB Distinct Inputs ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; Number of Distinct Inputs (Average = 6.57) ; Number of LABs (Total = 30) ;
|
|
|
+; Number of Distinct Inputs (Average = 7.21) ; Number of LABs (Total = 29) ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
; 0 ; 0 ;
|
|
|
; 1 ; 0 ;
|
|
|
; 2 ; 6 ;
|
|
|
-; 3 ; 8 ;
|
|
|
-; 4 ; 0 ;
|
|
|
-; 5 ; 3 ;
|
|
|
+; 3 ; 6 ;
|
|
|
+; 4 ; 2 ;
|
|
|
+; 5 ; 2 ;
|
|
|
; 6 ; 0 ;
|
|
|
; 7 ; 0 ;
|
|
|
-; 8 ; 4 ;
|
|
|
-; 9 ; 0 ;
|
|
|
-; 10 ; 1 ;
|
|
|
+; 8 ; 1 ;
|
|
|
+; 9 ; 3 ;
|
|
|
+; 10 ; 0 ;
|
|
|
; 11 ; 1 ;
|
|
|
-; 12 ; 1 ;
|
|
|
-; 13 ; 1 ;
|
|
|
+; 12 ; 0 ;
|
|
|
+; 13 ; 2 ;
|
|
|
; 14 ; 0 ;
|
|
|
-; 15 ; 1 ;
|
|
|
+; 15 ; 0 ;
|
|
|
; 16 ; 1 ;
|
|
|
-; 17 ; 1 ;
|
|
|
-; 18 ; 0 ;
|
|
|
+; 17 ; 2 ;
|
|
|
+; 18 ; 1 ;
|
|
|
; 19 ; 0 ;
|
|
|
-; 20 ; 1 ;
|
|
|
+; 20 ; 0 ;
|
|
|
+; 21 ; 1 ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
@@ -1701,7 +1706,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
|
|
|
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
|
|
|
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
|
|
|
-; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 15.3 ;
|
|
|
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 12.8 ;
|
|
|
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
|
|
|
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
|
|
|
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
|
|
|
@@ -1712,41 +1717,39 @@ This will disable optimization of problematic paths and expose them for further
|
|
|
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
|
|
|
; Source Register ; Destination Register ; Delay Added in ns ;
|
|
|
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4] ; 0.579 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.430 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4] ; 0.276 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1] ; 0.275 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3] ; 0.275 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1] ; 0.275 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.044 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.044 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.044 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4] ; 0.043 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4] ; 0.578 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.432 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; 0.274 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0] ; 0.274 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2] ; 0.274 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4] ; 0.272 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4] ; 0.264 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1] ; 0.262 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1] ; 0.262 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3] ; 0.262 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.184 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.184 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.184 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.184 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.184 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.184 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4] ; 0.043 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; 0.025 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; 0.025 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; 0.025 ;
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|
|
@@ -1755,7 +1758,7 @@ This will disable optimization of problematic paths and expose them for further
|
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; 0.025 ;
|
|
|
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; 0.025 ;
|
|
|
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
|
|
|
-Note: This table only shows the top 42 path(s) that have the largest delay added for hold.
|
|
|
+Note: This table only shows the top 40 path(s) that have the largest delay added for hold.
|
|
|
|
|
|
|
|
|
+-----------------+
|
|
|
@@ -1873,7 +1876,17 @@ Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_a
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Info (176353): Automatically promoted node rst_n File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 110
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|
|
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
|
|
|
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
|
|
|
- Info (176357): Destination node rst_ctr[0]~12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 137
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+ Info (176357): Destination node rst_ctr[11] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
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+ Info (176357): Destination node rst_ctr[10] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
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+ Info (176357): Destination node rst_ctr[9] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
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+ Info (176357): Destination node rst_ctr[8] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
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+ Info (176357): Destination node rst_ctr[7] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
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+ Info (176357): Destination node rst_ctr[6] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
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+ Info (176357): Destination node rst_ctr[5] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
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+ Info (176357): Destination node rst_ctr[4] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
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+ Info (176357): Destination node rst_ctr[3] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
|
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+ Info (176357): Destination node rst_ctr[2] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
|
|
|
+ Info (176358): Non-global destination nodes limited to 10 nodes
|
|
|
Info (176233): Starting register packing
|
|
|
Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
|
|
|
Info (176235): Finished register packing
|
|
|
@@ -1906,17 +1919,17 @@ Info (170137): Fitter placement was successful
|
|
|
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
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|
|
Info (170193): Fitter routing operations beginning
|
|
|
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
|
|
|
- Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
|
|
|
+ Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
|
|
|
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
|
|
Info (170201): Optimizations that may affect the design's routability were skipped
|
|
|
Info (170200): Optimizations that may affect the design's timing were skipped
|
|
|
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
|
|
-Info (11888): Total time spent on timing analysis during the Fitter is 0.12 seconds.
|
|
|
+Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
|
|
|
Info (334003): Started post-fitting delay annotation
|
|
|
Info (334004): Delay annotation completed successfully
|
|
|
Info (334003): Started post-fitting delay annotation
|
|
|
Info (334004): Delay annotation completed successfully
|
|
|
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
|
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|
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
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|
|
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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|
|
Warning (169180): Following 1 pins must use external clamping diodes.
|
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|
Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
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@@ -2053,9 +2066,9 @@ Warning (169064): Following 45 pins have no output enable or a GND or VCC output
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Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
|
|
|
Info: Quartus Prime Fitter was successful. 0 errors, 39 warnings
|
|
|
Info: Peak virtual memory: 1345 megabytes
|
|
|
- Info: Processing ended: Thu Jul 29 01:17:52 2021
|
|
|
- Info: Elapsed time: 00:00:09
|
|
|
- Info: Total CPU time (on all processors): 00:00:09
|
|
|
+ Info: Processing ended: Thu Jul 29 09:26:57 2021
|
|
|
+ Info: Elapsed time: 00:00:11
|
|
|
+ Info: Total CPU time (on all processors): 00:00:11
|
|
|
|
|
|
|
|
|
+----------------------------+
|
H. Peter Anvin