Fixa logiken för rst_n, snygga till ip/pll.v

ip/pll.v

@@ -213,7 +213,7 @@ endmodule
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "22"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
@@ -248,15 +248,15 @@ endmodule
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "45"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "36.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"

max80.sv

@@ -132,9 +132,9 @@ module max80 (
 	  rst_ctr <= 1'b0;
 	  rst_n   <= 1'b0;
        end
-     else
+     else if (~rst_n)
        begin
-	  { rst_n, rst_ctr } <= rst_ctr + ~rst_n;
+	  { rst_n, rst_ctr } <= rst_ctr + 1'b1;
        end
    
    // Unused device stubs - remove when used

output_files/max80.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for max80
-Thu Jul 29 01:17:54 2021
+Thu Jul 29 09:27:00 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -39,7 +39,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Jul 29 01:17:54 2021 ;
+; Assembler Status      ; Successful - Thu Jul 29 09:27:00 2021 ;
 ; Revision Name         ; max80                                 ;
 ; Top-level Entity Name ; max80                                 ;
 ; Family                ; Cyclone IV E                          ;
@@ -69,8 +69,8 @@ https://fpgasoftware.intel.com/eula.
 +----------------+--------------------+
 ; Option         ; Setting            ;
 +----------------+--------------------+
-; JTAG usercode  ; 0x0010D31B         ;
-; Checksum       ; 0x0010D31B         ;
+; JTAG usercode  ; 0x0010EA22         ;
+; Checksum       ; 0x0010EA22         ;
 +----------------+--------------------+
 
 
@@ -89,7 +89,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:17:52 2021
+    Info: Processing started: Thu Jul 29 09:26:58 2021
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
@@ -98,7 +98,7 @@ Info (210117): Created JAM or JBC file for the specified chain:
 Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 904 megabytes
-    Info: Processing ended: Thu Jul 29 01:17:54 2021
+    Info: Processing ended: Thu Jul 29 09:27:00 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 

output_files/max80.done

@@ -1 +1 @@
-Thu Jul 29 01:18:00 2021
+Thu Jul 29 09:27:15 2021

output_files/max80.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for max80
-Thu Jul 29 01:18:00 2021
+Thu Jul 29 09:27:08 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Jul 29 01:18:00 2021 ;
+; EDA Netlist Writer Status ; Successful - Thu Jul 29 09:27:08 2021 ;
 ; Revision Name             ; max80                                 ;
 ; Top-level Entity Name     ; max80                                 ;
 ; Family                    ; Cyclone IV E                          ;
@@ -81,14 +81,14 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:17:59 2021
+    Info: Processing started: Thu Jul 29 09:27:07 2021
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 1125 megabytes
-    Info: Processing ended: Thu Jul 29 01:18:00 2021
+    Info: Processing ended: Thu Jul 29 09:27:08 2021
     Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:00
+    Info: Total CPU time (on all processors): 00:00:01
 
 

output_files/max80.fit.rpt

@@ -1,5 +1,5 @@
 Fitter report for max80
-Thu Jul 29 01:17:51 2021
+Thu Jul 29 09:26:56 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -73,15 +73,15 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                   ;
 +------------------------------------+---------------------------------------------+
-; Fitter Status                      ; Successful - Thu Jul 29 01:17:51 2021       ;
+; Fitter Status                      ; Successful - Thu Jul 29 09:26:56 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
 ; Family                             ; Cyclone IV E                                ;
 ; Device                             ; EP4CE15F17C8                                ;
 ; Timing Models                      ; Final                                       ;
-; Total logic elements               ; 328 / 15,408 ( 2 % )                        ;
-;     Total combinational functions  ; 277 / 15,408 ( 2 % )                        ;
+; Total logic elements               ; 329 / 15,408 ( 2 % )                        ;
+;     Total combinational functions  ; 278 / 15,408 ( 2 % )                        ;
 ;     Dedicated logic registers      ; 218 / 15,408 ( 1 % )                        ;
 ; Total registers                    ; 229                                         ;
 ; Total pins                         ; 134 / 166 ( 81 % )                          ;
@@ -166,7 +166,7 @@ https://fpgasoftware.intel.com/eula.
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.6%      ;
+;     Processor 2            ;   0.8%      ;
 +----------------------------+-------------+
 
 
@@ -217,8 +217,8 @@ https://fpgasoftware.intel.com/eula.
 ; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
 +---------------------+--------------------+----------------------------+--------------------------+
 ; Placement (by node) ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 )         ; 0.00 % ( 0 / 816 )       ;
-;     -- Achieved     ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 )         ; 0.00 % ( 0 / 816 )       ;
+;     -- Requested    ; 0.00 % ( 0 / 817 ) ; 0.00 % ( 0 / 817 )         ; 0.00 % ( 0 / 817 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 817 ) ; 0.00 % ( 0 / 817 )         ; 0.00 % ( 0 / 817 )       ;
 ;                     ;                    ;                            ;                          ;
 ; Routing (by net)    ;                    ;                            ;                          ;
 ;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
@@ -241,7 +241,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
 ; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 787 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; Top                            ; 0.00 % ( 0 / 788 )    ; N/A                     ; Source File       ; N/A                 ;       ;
 ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 29 )     ; N/A                     ; Source File       ; N/A                 ;       ;
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
 
@@ -257,26 +257,26 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
 +---------------------------------------------+----------------------+
 ; Resource                                    ; Usage                ;
 +---------------------------------------------+----------------------+
-; Total logic elements                        ; 328 / 15,408 ( 2 % ) ;
-;     -- Combinational with no register       ; 110                  ;
+; Total logic elements                        ; 329 / 15,408 ( 2 % ) ;
+;     -- Combinational with no register       ; 111                  ;
 ;     -- Register only                        ; 51                   ;
 ;     -- Combinational with a register        ; 167                  ;
 ;                                             ;                      ;
 ; Logic element usage by number of LUT inputs ;                      ;
 ;     -- 4 input functions                    ; 105                  ;
 ;     -- 3 input functions                    ; 65                   ;
-;     -- <=2 input functions                  ; 107                  ;
+;     -- <=2 input functions                  ; 108                  ;
 ;     -- Register only                        ; 51                   ;
 ;                                             ;                      ;
 ; Logic elements by mode                      ;                      ;
-;     -- normal mode                          ; 220                  ;
-;     -- arithmetic mode                      ; 57                   ;
+;     -- normal mode                          ; 222                  ;
+;     -- arithmetic mode                      ; 56                   ;
 ;                                             ;                      ;
 ; Total registers*                            ; 229 / 16,166 ( 1 % ) ;
 ;     -- Dedicated logic registers            ; 218 / 15,408 ( 1 % ) ;
 ;     -- I/O registers                        ; 11 / 758 ( 1 % )     ;
 ;                                             ;                      ;
-; Total LABs:  partially or completely used   ; 30 / 963 ( 3 % )     ;
+; Total LABs:  partially or completely used   ; 29 / 963 ( 3 % )     ;
 ; Virtual pins                                ; 0                    ;
 ; I/O pins                                    ; 134 / 166 ( 81 % )   ;
 ;     -- Clock pins                           ; 4 / 3 ( 133 % )      ;
@@ -295,11 +295,11 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
 ; Oscillator blocks                           ; 0 / 1 ( 0 % )        ;
 ; Impedance control blocks                    ; 0 / 4 ( 0 % )        ;
 ; Average interconnect usage (total/H/V)      ; 0.3% / 0.3% / 0.3%   ;
-; Peak interconnect usage (total/H/V)         ; 2.2% / 2.5% / 1.7%   ;
+; Peak interconnect usage (total/H/V)         ; 2.0% / 2.0% / 2.0%   ;
 ; Maximum fan-out                             ; 90                   ;
 ; Highest non-global fan-out                  ; 42                   ;
-; Total fan-out                               ; 1632                 ;
-; Average fan-out                             ; 1.89                 ;
+; Total fan-out                               ; 1640                 ;
+; Average fan-out                             ; 1.90                 ;
 +---------------------------------------------+----------------------+
 *  Register count does not include registers inside RAM blocks or DSP blocks.
 
@@ -312,26 +312,26 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
 +---------------------------------------------+---------------------+--------------------------------+
 ; Difficulty Clustering Region                ; Low                 ; Low                            ;
 ;                                             ;                     ;                                ;
-; Total logic elements                        ; 322 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % )            ;
-;     -- Combinational with no register       ; 104                 ; 6                              ;
+; Total logic elements                        ; 323 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % )            ;
+;     -- Combinational with no register       ; 105                 ; 6                              ;
 ;     -- Register only                        ; 51                  ; 0                              ;
 ;     -- Combinational with a register        ; 167                 ; 0                              ;
 ;                                             ;                     ;                                ;
 ; Logic element usage by number of LUT inputs ;                     ;                                ;
 ;     -- 4 input functions                    ; 102                 ; 3                              ;
 ;     -- 3 input functions                    ; 65                  ; 0                              ;
-;     -- <=2 input functions                  ; 104                 ; 3                              ;
+;     -- <=2 input functions                  ; 105                 ; 3                              ;
 ;     -- Register only                        ; 51                  ; 0                              ;
 ;                                             ;                     ;                                ;
 ; Logic elements by mode                      ;                     ;                                ;
-;     -- normal mode                          ; 214                 ; 6                              ;
-;     -- arithmetic mode                      ; 57                  ; 0                              ;
+;     -- normal mode                          ; 216                 ; 6                              ;
+;     -- arithmetic mode                      ; 56                  ; 0                              ;
 ;                                             ;                     ;                                ;
 ; Total registers                             ; 221                 ; 8                              ;
 ;     -- Dedicated logic registers            ; 218 / 15408 ( 1 % ) ; 0 / 15408 ( 0 % )              ;
 ;     -- I/O registers                        ; 6                   ; 16                             ;
 ;                                             ;                     ;                                ;
-; Total LABs:  partially or completely used   ; 30 / 963 ( 3 % )    ; 1 / 963 ( < 1 % )              ;
+; Total LABs:  partially or completely used   ; 29 / 963 ( 3 % )    ; 1 / 963 ( < 1 % )              ;
 ;                                             ;                     ;                                ;
 ; Virtual pins                                ; 0                   ; 0                              ;
 ; I/O pins                                    ; 126                 ; 8                              ;
@@ -349,8 +349,8 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
 ;     -- Registered Output Connections        ; 8                   ; 0                              ;
 ;                                             ;                     ;                                ;
 ; Internal Connections                        ;                     ;                                ;
-;     -- Total Connections                    ; 1596                ; 291                            ;
-;     -- Registered Connections               ; 766                 ; 0                              ;
+;     -- Total Connections                    ; 1604                ; 291                            ;
+;     -- Registered Connections               ; 779                 ; 0                              ;
 ;                                             ;                     ;                                ;
 ; External Connections                        ;                     ;                                ;
 ;     -- Top                                  ; 90                  ; 247                            ;
@@ -1023,12 +1023,12 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
 +--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
 ; Compilation Hierarchy Node                                   ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                ; Entity Name               ; Library Name ;
 +--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
-; |max80                                                       ; 328 (67)    ; 218 (66)                  ; 11 (11)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 134  ; 0            ; 110 (1)      ; 51 (1)            ; 167 (50)         ; |max80                                                                                                             ; max80                     ; work         ;
+; |max80                                                       ; 329 (68)    ; 218 (66)                  ; 11 (11)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 134  ; 0            ; 111 (2)      ; 51 (1)            ; 167 (50)         ; |max80                                                                                                             ; max80                     ; work         ;
 ;    |hdmitx:hdmitx|                                           ; 119 (0)     ; 109 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (0)       ; 41 (0)            ; 68 (0)           ; |max80|hdmitx:hdmitx                                                                                               ; hdmitx                    ; work         ;
 ;       |altlvds_tx:ALTLVDS_TX_component|                      ; 119 (0)     ; 109 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (0)       ; 41 (0)            ; 68 (0)           ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ; altlvds_tx                ; work         ;
-;          |hdmitx_lvds_tx:auto_generated|                     ; 119 (61)    ; 109 (60)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (1)       ; 41 (40)           ; 68 (19)          ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
-;             |hdmitx_cntr:cntr13|                             ; 8 (8)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 3 (3)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ; hdmitx_cntr               ; work         ;
-;             |hdmitx_cntr:cntr2|                              ; 8 (8)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 4 (4)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ; hdmitx_cntr               ; work         ;
+;          |hdmitx_lvds_tx:auto_generated|                     ; 119 (60)    ; 109 (60)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (1)       ; 41 (40)           ; 68 (19)          ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
+;             |hdmitx_cntr:cntr13|                             ; 8 (8)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 4 (4)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ; hdmitx_cntr               ; work         ;
+;             |hdmitx_cntr:cntr2|                              ; 8 (8)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 3 (3)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ; hdmitx_cntr               ; work         ;
 ;             |hdmitx_ddio_out1:outclock_ddio|                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ; hdmitx_ddio_out1          ; work         ;
 ;             |hdmitx_ddio_out:ddio_out|                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ; hdmitx_ddio_out           ; work         ;
 ;             |hdmitx_shift_reg1:shift_reg23|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ; hdmitx_shift_reg1         ; work         ;
@@ -1046,8 +1046,8 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
 ;             |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ; pll_altpll_dyn_phase_le1  ; work         ;
 ;             |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|   ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ; pll_altpll_dyn_phase_le   ; work         ;
 ;    |tmdsenc:hdmitmds[0].enc|                                 ; 51 (51)     ; 15 (15)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (30)      ; 3 (3)             ; 18 (18)          ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ; tmdsenc                   ; work         ;
-;    |tmdsenc:hdmitmds[1].enc|                                 ; 50 (50)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 32 (32)      ; 3 (3)             ; 15 (15)          ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ; tmdsenc                   ; work         ;
-;    |tmdsenc:hdmitmds[2].enc|                                 ; 50 (50)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 3 (3)             ; 16 (16)          ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ; tmdsenc                   ; work         ;
+;    |tmdsenc:hdmitmds[1].enc|                                 ; 50 (50)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 3 (3)             ; 16 (16)          ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ; tmdsenc                   ; work         ;
+;    |tmdsenc:hdmitmds[2].enc|                                 ; 50 (50)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 32 (32)      ; 3 (3)             ; 15 (15)          ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ; tmdsenc                   ; work         ;
 +--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
@@ -1292,28 +1292,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
 ; clock_48                                                                                            ; PIN_M15        ; 1       ; Clock                   ; no     ; --                   ; --               ; --                        ;
 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; PLL_1          ; 82      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ; --                        ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a            ; FF_X23_Y21_N17 ; 41      ; Clock enable            ; no     ; --                   ; --               ; --                        ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a            ; FF_X19_Y23_N19 ; 41      ; Clock enable            ; no     ; --                   ; --               ; --                        ;
 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1          ; 31      ; Clock                   ; yes    ; Global Clock         ; GCLK4            ; --                        ;
 ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; PLL_2          ; 45      ; Clock                   ; yes    ; Global Clock         ; GCLK7            ; --                        ;
 ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; PLL_2          ; 68      ; Clock                   ; yes    ; Global Clock         ; GCLK9            ; --                        ;
 ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked                          ; PLL_2          ; 13      ; Async. clear            ; no     ; --                   ; --               ; --                        ;
-; rst_n                                                                                               ; FF_X40_Y27_N27 ; 75      ; Async. clear            ; yes    ; Global Clock         ; GCLK5            ; --                        ;
-; tmdsenc:hdmitmds[0].enc|denreg                                                                      ; FF_X26_Y23_N7  ; 42      ; Sync. clear, Sync. load ; no     ; --                   ; --               ; --                        ;
+; rst_n                                                                                               ; FF_X20_Y28_N1  ; 14      ; Clock enable            ; no     ; --                   ; --               ; --                        ;
+; rst_n                                                                                               ; FF_X20_Y28_N1  ; 75      ; Async. clear            ; yes    ; Global Clock         ; GCLK12           ; --                        ;
+; tmdsenc:hdmitmds[0].enc|denreg                                                                      ; FF_X22_Y22_N15 ; 42      ; Sync. clear, Sync. load ; no     ; --                   ; --               ; --                        ;
 +-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
 
 
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals                                                                                                                                                                                                                 ;
-+-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; Name                                                                                                ; Location       ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; PLL_1          ; 82      ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1          ; 31      ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; PLL_2          ; 1       ; 0                                    ; Global Clock         ; GCLK8            ; --                        ;
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; PLL_2          ; 45      ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; PLL_2          ; 68      ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
-; rst_n                                                                                               ; FF_X40_Y27_N27 ; 75      ; 0                                    ; Global Clock         ; GCLK5            ; --                        ;
-+-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                                ;
++-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                                ; Location      ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; PLL_1         ; 82      ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1         ; 31      ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; PLL_2         ; 1       ; 0                                    ; Global Clock         ; GCLK8            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; PLL_2         ; 45      ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; PLL_2         ; 68      ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+; rst_n                                                                                               ; FF_X20_Y28_N1 ; 75      ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
++-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
 
 
 +------------------------------------------------+
@@ -1321,24 +1322,24 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-----------------------+------------------------+
 ; Routing Resource Type ; Usage                  ;
 +-----------------------+------------------------+
-; Block interconnects   ; 241 / 47,787 ( < 1 % ) ;
-; C16 interconnects     ; 5 / 1,804 ( < 1 % )    ;
-; C4 interconnects      ; 72 / 31,272 ( < 1 % )  ;
-; Direct links          ; 89 / 47,787 ( < 1 % )  ;
+; Block interconnects   ; 262 / 47,787 ( < 1 % ) ;
+; C16 interconnects     ; 6 / 1,804 ( < 1 % )    ;
+; C4 interconnects      ; 89 / 31,272 ( < 1 % )  ;
+; Direct links          ; 97 / 47,787 ( < 1 % )  ;
 ; Global clocks         ; 6 / 20 ( 30 % )        ;
-; Local interconnects   ; 205 / 15,408 ( 1 % )   ;
-; R24 interconnects     ; 5 / 1,775 ( < 1 % )    ;
-; R4 interconnects      ; 103 / 41,310 ( < 1 % ) ;
+; Local interconnects   ; 186 / 15,408 ( 1 % )   ;
+; R24 interconnects     ; 8 / 1,775 ( < 1 % )    ;
+; R4 interconnects      ; 98 / 41,310 ( < 1 % )  ;
 +-----------------------+------------------------+
 
 
 +----------------------------------------------------------------------------+
 ; LAB Logic Elements                                                         ;
 +---------------------------------------------+------------------------------+
-; Number of Logic Elements  (Average = 10.93) ; Number of LABs  (Total = 30) ;
+; Number of Logic Elements  (Average = 11.34) ; Number of LABs  (Total = 29) ;
 +---------------------------------------------+------------------------------+
-; 1                                           ; 5                            ;
-; 2                                           ; 1                            ;
+; 1                                           ; 3                            ;
+; 2                                           ; 2                            ;
 ; 3                                           ; 1                            ;
 ; 4                                           ; 0                            ;
 ; 5                                           ; 0                            ;
@@ -1346,10 +1347,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; 7                                           ; 1                            ;
 ; 8                                           ; 1                            ;
 ; 9                                           ; 0                            ;
-; 10                                          ; 3                            ;
+; 10                                          ; 2                            ;
 ; 11                                          ; 0                            ;
-; 12                                          ; 0                            ;
-; 13                                          ; 3                            ;
+; 12                                          ; 2                            ;
+; 13                                          ; 2                            ;
 ; 14                                          ; 2                            ;
 ; 15                                          ; 2                            ;
 ; 16                                          ; 11                           ;
@@ -1359,28 +1360,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +-------------------------------------------------------------------+
 ; LAB-wide Signals                                                  ;
 +------------------------------------+------------------------------+
-; LAB-wide Signals  (Average = 1.37) ; Number of LABs  (Total = 30) ;
+; LAB-wide Signals  (Average = 1.52) ; Number of LABs  (Total = 29) ;
 +------------------------------------+------------------------------+
-; 1 Async. clear                     ; 10                           ;
-; 1 Clock                            ; 18                           ;
-; 1 Clock enable                     ; 2                            ;
+; 1 Async. clear                     ; 11                           ;
+; 1 Clock                            ; 19                           ;
+; 1 Clock enable                     ; 4                            ;
 ; 1 Sync. clear                      ; 3                            ;
-; 2 Clocks                           ; 8                            ;
+; 2 Clocks                           ; 7                            ;
 +------------------------------------+------------------------------+
 
 
 +-----------------------------------------------------------------------------+
 ; LAB Signals Sourced                                                         ;
 +----------------------------------------------+------------------------------+
-; Number of Signals Sourced  (Average = 17.93) ; Number of LABs  (Total = 30) ;
+; Number of Signals Sourced  (Average = 18.41) ; Number of LABs  (Total = 29) ;
 +----------------------------------------------+------------------------------+
 ; 0                                            ; 0                            ;
-; 1                                            ; 3                            ;
-; 2                                            ; 2                            ;
+; 1                                            ; 1                            ;
+; 2                                            ; 3                            ;
 ; 3                                            ; 1                            ;
-; 4                                            ; 1                            ;
+; 4                                            ; 0                            ;
 ; 5                                            ; 0                            ;
-; 6                                            ; 0                            ;
+; 6                                            ; 1                            ;
 ; 7                                            ; 1                            ;
 ; 8                                            ; 0                            ;
 ; 9                                            ; 0                            ;
@@ -1388,23 +1389,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; 11                                           ; 0                            ;
 ; 12                                           ; 0                            ;
 ; 13                                           ; 0                            ;
-; 14                                           ; 0                            ;
+; 14                                           ; 1                            ;
 ; 15                                           ; 0                            ;
-; 16                                           ; 1                            ;
+; 16                                           ; 0                            ;
 ; 17                                           ; 0                            ;
-; 18                                           ; 0                            ;
-; 19                                           ; 4                            ;
+; 18                                           ; 1                            ;
+; 19                                           ; 3                            ;
 ; 20                                           ; 1                            ;
-; 21                                           ; 2                            ;
-; 22                                           ; 0                            ;
-; 23                                           ; 4                            ;
-; 24                                           ; 2                            ;
+; 21                                           ; 0                            ;
+; 22                                           ; 3                            ;
+; 23                                           ; 5                            ;
+; 24                                           ; 1                            ;
 ; 25                                           ; 1                            ;
-; 26                                           ; 2                            ;
-; 27                                           ; 0                            ;
-; 28                                           ; 2                            ;
-; 29                                           ; 1                            ;
-; 30                                           ; 1                            ;
+; 26                                           ; 1                            ;
+; 27                                           ; 1                            ;
+; 28                                           ; 1                            ;
+; 29                                           ; 0                            ;
+; 30                                           ; 2                            ;
 ; 31                                           ; 1                            ;
 +----------------------------------------------+------------------------------+
 
@@ -1412,53 +1413,57 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------------------------------------------------------------------------+
 ; LAB Signals Sourced Out                                                        ;
 +-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out  (Average = 4.80) ; Number of LABs  (Total = 30) ;
+; Number of Signals Sourced Out  (Average = 5.38) ; Number of LABs  (Total = 29) ;
 +-------------------------------------------------+------------------------------+
 ; 0                                               ; 1                            ;
-; 1                                               ; 9                            ;
-; 2                                               ; 4                            ;
+; 1                                               ; 4                            ;
+; 2                                               ; 6                            ;
 ; 3                                               ; 4                            ;
 ; 4                                               ; 2                            ;
-; 5                                               ; 1                            ;
-; 6                                               ; 0                            ;
+; 5                                               ; 3                            ;
+; 6                                               ; 1                            ;
 ; 7                                               ; 1                            ;
-; 8                                               ; 1                            ;
+; 8                                               ; 0                            ;
 ; 9                                               ; 0                            ;
 ; 10                                              ; 1                            ;
 ; 11                                              ; 1                            ;
 ; 12                                              ; 2                            ;
-; 13                                              ; 1                            ;
+; 13                                              ; 0                            ;
 ; 14                                              ; 1                            ;
 ; 15                                              ; 1                            ;
+; 16                                              ; 0                            ;
+; 17                                              ; 0                            ;
+; 18                                              ; 1                            ;
 +-------------------------------------------------+------------------------------+
 
 
 +----------------------------------------------------------------------------+
 ; LAB Distinct Inputs                                                        ;
 +---------------------------------------------+------------------------------+
-; Number of Distinct Inputs  (Average = 6.57) ; Number of LABs  (Total = 30) ;
+; Number of Distinct Inputs  (Average = 7.21) ; Number of LABs  (Total = 29) ;
 +---------------------------------------------+------------------------------+
 ; 0                                           ; 0                            ;
 ; 1                                           ; 0                            ;
 ; 2                                           ; 6                            ;
-; 3                                           ; 8                            ;
-; 4                                           ; 0                            ;
-; 5                                           ; 3                            ;
+; 3                                           ; 6                            ;
+; 4                                           ; 2                            ;
+; 5                                           ; 2                            ;
 ; 6                                           ; 0                            ;
 ; 7                                           ; 0                            ;
-; 8                                           ; 4                            ;
-; 9                                           ; 0                            ;
-; 10                                          ; 1                            ;
+; 8                                           ; 1                            ;
+; 9                                           ; 3                            ;
+; 10                                          ; 0                            ;
 ; 11                                          ; 1                            ;
-; 12                                          ; 1                            ;
-; 13                                          ; 1                            ;
+; 12                                          ; 0                            ;
+; 13                                          ; 2                            ;
 ; 14                                          ; 0                            ;
-; 15                                          ; 1                            ;
+; 15                                          ; 0                            ;
 ; 16                                          ; 1                            ;
-; 17                                          ; 1                            ;
-; 18                                          ; 0                            ;
+; 17                                          ; 2                            ;
+; 18                                          ; 1                            ;
 ; 19                                          ; 0                            ;
-; 20                                          ; 1                            ;
+; 20                                          ; 0                            ;
+; 21                                          ; 1                            ;
 +---------------------------------------------+------------------------------+
 
 
@@ -1701,7 +1706,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
 ; Source Clock(s)                                               ; Destination Clock(s)                                          ; Delay Added in ns ;
 +---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
-; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 15.3              ;
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 12.8              ;
 +---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
 Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
 This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
@@ -1712,41 +1717,39 @@ This will disable optimization of problematic paths and expose them for further
 +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
 ; Source Register                                                                                                          ; Destination Register                                                                                                     ; Delay Added in ns ;
 +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; 0.579             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.430             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; 0.276             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; 0.275             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; 0.275             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; 0.275             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.182             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.182             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.182             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.044             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.044             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.044             ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; 0.043             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; 0.578             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.432             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; 0.274             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; 0.274             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; 0.274             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; 0.272             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; 0.264             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; 0.262             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; 0.262             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; 0.262             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.184             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.184             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.184             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.184             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.184             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.184             ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; 0.043             ;
 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; 0.025             ;
 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; 0.025             ;
 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; 0.025             ;
@@ -1755,7 +1758,7 @@ This will disable optimization of problematic paths and expose them for further
 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; 0.025             ;
 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; 0.025             ;
 +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
-Note: This table only shows the top 42 path(s) that have the largest delay added for hold.
+Note: This table only shows the top 40 path(s) that have the largest delay added for hold.
 
 
 +-----------------+
@@ -1873,7 +1876,17 @@ Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_a
 Info (176353): Automatically promoted node rst_n  File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 110
     Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
     Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
-        Info (176357): Destination node rst_ctr[0]~12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 137
+        Info (176357): Destination node rst_ctr[11] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[10] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[9] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[8] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[7] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[6] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[5] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[4] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[3] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176357): Destination node rst_ctr[2] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 135
+        Info (176358): Non-global destination nodes limited to 10 nodes
 Info (176233): Starting register packing
 Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
 Info (176235): Finished register packing
@@ -1906,17 +1919,17 @@ Info (170137): Fitter placement was successful
 Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
 Info (170193): Fitter routing operations beginning
 Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
+    Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
 Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
     Info (170201): Optimizations that may affect the design's routability were skipped
     Info (170200): Optimizations that may affect the design's timing were skipped
 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.12 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
 Warning (169180): Following 1 pins must use external clamping diodes.
     Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
@@ -2053,9 +2066,9 @@ Warning (169064): Following 45 pins have no output enable or a GND or VCC output
 Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 39 warnings
     Info: Peak virtual memory: 1345 megabytes
-    Info: Processing ended: Thu Jul 29 01:17:52 2021
-    Info: Elapsed time: 00:00:09
-    Info: Total CPU time (on all processors): 00:00:09
+    Info: Processing ended: Thu Jul 29 09:26:57 2021
+    Info: Elapsed time: 00:00:11
+    Info: Total CPU time (on all processors): 00:00:11
 
 
 +----------------------------+

output_files/max80.fit.summary

@@ -1,12 +1,12 @@
-Fitter Status : Successful - Thu Jul 29 01:17:51 2021
+Fitter Status : Successful - Thu Jul 29 09:26:56 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
 Family : Cyclone IV E
 Device : EP4CE15F17C8
 Timing Models : Final
-Total logic elements : 328 / 15,408 ( 2 % )
-    Total combinational functions : 277 / 15,408 ( 2 % )
+Total logic elements : 329 / 15,408 ( 2 % )
+    Total combinational functions : 278 / 15,408 ( 2 % )
     Dedicated logic registers : 218 / 15,408 ( 1 % )
 Total registers : 229
 Total pins : 134 / 166 ( 81 % )

output_files/max80.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for max80
-Thu Jul 29 01:18:00 2021
+Thu Jul 29 09:27:08 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -41,15 +41,15 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Thu Jul 29 01:18:00 2021       ;
+; Flow Status                        ; Successful - Thu Jul 29 09:27:08 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
 ; Family                             ; Cyclone IV E                                ;
 ; Device                             ; EP4CE15F17C8                                ;
 ; Timing Models                      ; Final                                       ;
-; Total logic elements               ; 328 / 15,408 ( 2 % )                        ;
-;     Total combinational functions  ; 277 / 15,408 ( 2 % )                        ;
+; Total logic elements               ; 329 / 15,408 ( 2 % )                        ;
+;     Total combinational functions  ; 278 / 15,408 ( 2 % )                        ;
 ;     Dedicated logic registers      ; 218 / 15,408 ( 1 % )                        ;
 ; Total registers                    ; 229                                         ;
 ; Total pins                         ; 134 / 166 ( 81 % )                          ;
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 07/29/2021 01:17:30 ;
+; Start date & time ; 07/29/2021 09:26:33 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; max80               ;
 +-------------------+---------------------+
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                      ; 180546899331588.162754665061494        ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID                      ; 180546899331588.162757599302772        ; --            ; --          ; --                                ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
@@ -125,13 +125,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:12     ; 1.0                     ; 1038 MB             ; 00:00:28                           ;
-; Fitter               ; 00:00:08     ; 1.0                     ; 1345 MB             ; 00:00:09                           ;
+; Analysis & Synthesis ; 00:00:14     ; 1.0                     ; 1030 MB             ; 00:00:28                           ;
+; Fitter               ; 00:00:10     ; 1.0                     ; 1345 MB             ; 00:00:10                           ;
 ; Assembler            ; 00:00:02     ; 1.0                     ; 904 MB              ; 00:00:02                           ;
-; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1264 MB             ; 00:00:02                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 891 MB              ; 00:00:02                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 1125 MB             ; 00:00:00                           ;
-; Total                ; 00:00:27     ; --                      ; --                  ; 00:00:43                           ;
+; Power Analyzer       ; 00:00:03     ; 1.0                     ; 1263 MB             ; 00:00:02                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 892 MB              ; 00:00:03                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 1125 MB             ; 00:00:01                           ;
+; Total                ; 00:00:32     ; --                      ; --                  ; 00:00:46                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 

output_files/max80.map.rpt

@@ -1,5 +1,5 @@
 Analysis & Synthesis report for max80
-Thu Jul 29 01:17:42 2021
+Thu Jul 29 09:26:46 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -67,13 +67,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Thu Jul 29 01:17:42 2021       ;
+; Analysis & Synthesis Status        ; Successful - Thu Jul 29 09:26:46 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
 ; Family                             ; Cyclone IV E                                ;
-; Total logic elements               ; 336                                         ;
-;     Total combinational functions  ; 273                                         ;
+; Total logic elements               ; 337                                         ;
+;     Total combinational functions  ; 274                                         ;
 ;     Dedicated logic registers      ; 218                                         ;
 ; Total registers                    ; 226                                         ;
 ; Total pins                         ; 130                                         ;
@@ -221,17 +221,17 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------+----------------------------------------------------------------------------------------+
 ; Resource                                    ; Usage                                                                                  ;
 +---------------------------------------------+----------------------------------------------------------------------------------------+
-; Estimated Total logic elements              ; 336                                                                                    ;
+; Estimated Total logic elements              ; 337                                                                                    ;
 ;                                             ;                                                                                        ;
-; Total combinational functions               ; 273                                                                                    ;
+; Total combinational functions               ; 274                                                                                    ;
 ; Logic element usage by number of LUT inputs ;                                                                                        ;
 ;     -- 4 input functions                    ; 102                                                                                    ;
 ;     -- 3 input functions                    ; 65                                                                                     ;
-;     -- <=2 input functions                  ; 106                                                                                    ;
+;     -- <=2 input functions                  ; 107                                                                                    ;
 ;                                             ;                                                                                        ;
 ; Logic elements by mode                      ;                                                                                        ;
-;     -- normal mode                          ; 216                                                                                    ;
-;     -- arithmetic mode                      ; 57                                                                                     ;
+;     -- normal mode                          ; 218                                                                                    ;
+;     -- arithmetic mode                      ; 56                                                                                     ;
 ;                                             ;                                                                                        ;
 ; Total registers                             ; 226                                                                                    ;
 ;     -- Dedicated logic registers            ; 218                                                                                    ;
@@ -246,8 +246,8 @@ https://fpgasoftware.intel.com/eula.
 ;                                             ;                                                                                        ;
 ; Maximum fan-out node                        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ;
 ; Maximum fan-out                             ; 114                                                                                    ;
-; Total fan-out                               ; 1553                                                                                   ;
-; Average fan-out                             ; 1.93                                                                                   ;
+; Total fan-out                               ; 1566                                                                                   ;
+; Average fan-out                             ; 1.94                                                                                   ;
 +---------------------------------------------+----------------------------------------------------------------------------------------+
 
 
@@ -256,7 +256,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
 ; Compilation Hierarchy Node                                   ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                ; Entity Name               ; Library Name ;
 +--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
-; |max80                                                       ; 273 (51)            ; 218 (66)                  ; 0           ; 0            ; 0       ; 0         ; 130  ; 0            ; |max80                                                                                                             ; max80                     ; work         ;
+; |max80                                                       ; 274 (52)            ; 218 (66)                  ; 0           ; 0            ; 0       ; 0         ; 130  ; 0            ; |max80                                                                                                             ; max80                     ; work         ;
 ;    |hdmitx:hdmitx|                                           ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx                                                                                               ; hdmitx                    ; work         ;
 ;       |altlvds_tx:ALTLVDS_TX_component|                      ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ; altlvds_tx                ; work         ;
 ;          |hdmitx_lvds_tx:auto_generated|                     ; 78 (20)             ; 109 (60)                  ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
@@ -363,7 +363,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; Number of registers using Synchronous Load   ; 9     ;
 ; Number of registers using Asynchronous Clear ; 85    ;
 ; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 27    ;
+; Number of registers using Clock Enable       ; 39    ;
 ; Number of registers using Preset             ; 0     ;
 +----------------------------------------------+-------+
 
@@ -408,11 +408,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
 ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
 +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
-; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[1] ;
-; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[0] ;
-; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[0] ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[4] ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[1] ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[6] ;
 ; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[5] ;
-; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[3] ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[5] ;
 ; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[7] ;
 ; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[2].enc|Add8    ;
 ; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[0].enc|Add8    ;
@@ -1054,26 +1054,27 @@ Note: In order to hide this table in the UI and the text report file, please set
 ; boundary_port         ; 130                         ;
 ; cycloneiii_ddio_out   ; 4                           ;
 ; cycloneiii_ff         ; 218                         ;
-;     CLR               ; 58                          ;
+;     CLR               ; 46                          ;
 ;     CLR SCLR          ; 18                          ;
 ;     CLR SLD           ; 9                           ;
 ;     ENA               ; 27                          ;
+;     ENA CLR           ; 12                          ;
 ;     plain             ; 106                         ;
 ; cycloneiii_io_obuf    ; 51                          ;
-; cycloneiii_lcell_comb ; 277                         ;
-;     arith             ; 57                          ;
-;         2 data inputs ; 40                          ;
+; cycloneiii_lcell_comb ; 278                         ;
+;     arith             ; 56                          ;
+;         2 data inputs ; 39                          ;
 ;         3 data inputs ; 17                          ;
-;     normal            ; 220                         ;
+;     normal            ; 222                         ;
 ;         0 data inputs ; 8                           ;
-;         1 data inputs ; 23                          ;
-;         2 data inputs ; 36                          ;
+;         1 data inputs ; 24                          ;
+;         2 data inputs ; 37                          ;
 ;         3 data inputs ; 48                          ;
 ;         4 data inputs ; 105                         ;
 ; cycloneiii_pll        ; 2                           ;
 ;                       ;                             ;
 ; Max LUT depth         ; 7.20                        ;
-; Average LUT depth     ; 2.81                        ;
+; Average LUT depth     ; 2.84                        ;
 +-----------------------+-----------------------------+
 
 
@@ -1092,7 +1093,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:17:30 2021
+    Info: Processing started: Thu Jul 29 09:26:32 2021
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
@@ -1500,16 +1501,16 @@ Warning (21074): Design contains 37 input pin(s) that do not drive logic
     Warning (15610): No output dependent on input pin "flash_miso" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
     Warning (15610): No output dependent on input pin "rtc_32khz" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
     Warning (15610): No output dependent on input pin "rtc_int_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
-Info (21057): Implemented 475 device resources after synthesis - the final resource count might be different
+Info (21057): Implemented 476 device resources after synthesis - the final resource count might be different
     Info (21058): Implemented 38 input pins
     Info (21059): Implemented 47 output pins
     Info (21060): Implemented 45 bidirectional pins
-    Info (21061): Implemented 339 logic cells
+    Info (21061): Implemented 340 logic cells
     Info (21065): Implemented 2 PLLs
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 208 warnings
-    Info: Peak virtual memory: 1087 megabytes
-    Info: Processing ended: Thu Jul 29 01:17:42 2021
-    Info: Elapsed time: 00:00:12
+    Info: Peak virtual memory: 1079 megabytes
+    Info: Processing ended: Thu Jul 29 09:26:46 2021
+    Info: Elapsed time: 00:00:14
     Info: Total CPU time (on all processors): 00:00:28
 
 

output_files/max80.map.summary

@@ -1,10 +1,10 @@
-Analysis & Synthesis Status : Successful - Thu Jul 29 01:17:42 2021
+Analysis & Synthesis Status : Successful - Thu Jul 29 09:26:46 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
 Family : Cyclone IV E
-Total logic elements : 336
-    Total combinational functions : 273
+Total logic elements : 337
+    Total combinational functions : 274
     Dedicated logic registers : 218
 Total registers : 226
 Total pins : 130

output_files/max80.pow.rpt

@@ -1,5 +1,5 @@
 Power Analyzer report for max80
-Thu Jul 29 01:17:56 2021
+Thu Jul 29 09:27:03 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -65,15 +65,15 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------------+
 ; Power Analyzer Summary                                                                    ;
 +----------------------------------------+--------------------------------------------------+
-; Power Analyzer Status                  ; Successful - Thu Jul 29 01:17:56 2021            ;
+; Power Analyzer Status                  ; Successful - Thu Jul 29 09:27:03 2021            ;
 ; Quartus Prime Version                  ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition      ;
 ; Revision Name                          ; max80                                            ;
 ; Top-level Entity Name                  ; max80                                            ;
 ; Family                                 ; Cyclone IV E                                     ;
 ; Device                                 ; EP4CE15F17C8                                     ;
 ; Power Models                           ; Final                                            ;
-; Total Thermal Power Dissipation        ; 213.74 mW                                        ;
-; Core Dynamic Thermal Power Dissipation ; 38.27 mW                                         ;
+; Total Thermal Power Dissipation        ; 214.72 mW                                        ;
+; Core Dynamic Thermal Power Dissipation ; 39.23 mW                                         ;
 ; Core Static Thermal Power Dissipation  ; 60.18 mW                                         ;
 ; I/O Thermal Power Dissipation          ; 115.30 mW                                        ;
 ; Power Estimation Confidence            ; Low: user provided insufficient toggle rate data ;
@@ -211,7 +211,7 @@ https://fpgasoftware.intel.com/eula.
 ;     2.5 V I/O Standard                  ; 2.5 V                      ;
 ;     LVDS I/O Standard                   ; 2.5 V                      ;
 ;                                         ;                            ;
-; Auto computed junction temperature      ; 31.3 degrees Celsius       ;
+; Auto computed junction temperature      ; 31.4 degrees Celsius       ;
 ;     Ambient temperature                 ; 25.0 degrees Celsius       ;
 ;     Junction-to-Case thermal resistance ; 7.30 degrees Celsius/Watt  ;
 ;     Case-to-Ambient thermal resistance  ; 22.30 degrees Celsius/Watt ;
@@ -234,9 +234,9 @@ https://fpgasoftware.intel.com/eula.
 ; Block Type                            ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ;
 +---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
 ; PLL                                   ; 23.74 mW                          ; 23.74 mW                    ; --                             ; 0.00 mW                       ;  111.003                                                  ;
-; Combinational cell                    ; 0.43 mW                           ; 0.35 mW                     ; --                             ; 0.07 mW                       ;    8.145                                                  ;
-; Clock control block                   ; 11.65 mW                          ; 0.00 mW                     ; --                             ; 11.65 mW                      ;  180.003                                                  ;
-; Register cell                         ; 2.44 mW                           ; 1.88 mW                     ; --                             ; 0.57 mW                       ;   13.191                                                  ;
+; Combinational cell                    ; 0.42 mW                           ; 0.35 mW                     ; --                             ; 0.07 mW                       ;    8.056                                                  ;
+; Clock control block                   ; 12.52 mW                          ; 0.00 mW                     ; --                             ; 12.52 mW                      ;  180.003                                                  ;
+; Register cell                         ; 2.56 mW                           ; 1.99 mW                     ; --                             ; 0.57 mW                       ;   13.191                                                  ;
 ; Double Data Rate I/O Output Circuitry ; 0.49 mW                           ; 0.49 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
 ; I/O register                          ; 0.21 mW                           ; 0.21 mW                     ; --                             ; 0.00 mW                       ;   12.000                                                  ;
 ; I/O                                   ; 88.23 mW                          ; 3.58 mW                     ; 84.65 mW                       ; 0.00 mW                       ;    2.418                                                  ;
@@ -249,30 +249,30 @@ https://fpgasoftware.intel.com/eula.
 +-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
 ; Compilation Hierarchy Node                                      ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name                                                                                                ;
 +-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
-; |max80                                                          ; 127.19 mW (91.53 mW)                 ; 30.25 mW (4.26 mW)              ; 84.65 mW (84.65 mW)               ; 12.29 mW (2.61 mW)                ; |max80                                                                                                             ;
+; |max80                                                          ; 128.16 mW (91.35 mW)                 ; 30.35 mW (4.25 mW)              ; 84.65 mW (84.65 mW)               ; 13.16 mW (2.45 mW)                ; |max80                                                                                                             ;
 ;     |hard_block:auto_generated_inst                             ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hard_block:auto_generated_inst                                                                              ;
-;     |tmdsenc:hdmitmds[0].enc                                    ; 0.16 mW (0.16 mW)                    ; 0.13 mW (0.13 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ;
-;     |tmdsenc:hdmitmds[1].enc                                    ; 0.14 mW (0.14 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ;
+;     |tmdsenc:hdmitmds[0].enc                                    ; 0.17 mW (0.17 mW)                    ; 0.14 mW (0.14 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ;
+;     |tmdsenc:hdmitmds[1].enc                                    ; 0.15 mW (0.15 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ;
 ;     |tmdsenc:hdmitmds[2].enc                                    ; 0.14 mW (0.14 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ;
 ;     |transpose:hdmitranspose                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|transpose:hdmitranspose                                                                                     ;
-;     |hdmitx:hdmitx                                              ; 18.66 mW (0.00 mW)                   ; 13.23 mW (0.00 mW)              ; --                                ; 5.43 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx                                                                                               ;
-;         |altlvds_tx:ALTLVDS_TX_component                        ; 18.66 mW (0.00 mW)                   ; 13.23 mW (0.00 mW)              ; --                                ; 5.43 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ;
-;             |hdmitx_lvds_tx:auto_generated                      ; 18.66 mW (17.08 mW)                  ; 13.23 mW (11.90 mW)             ; --                                ; 5.43 mW (5.18 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ;
+;     |hdmitx:hdmitx                                              ; 19.77 mW (0.00 mW)                   ; 13.33 mW (0.00 mW)              ; --                                ; 6.43 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx                                                                                               ;
+;         |altlvds_tx:ALTLVDS_TX_component                        ; 19.77 mW (0.00 mW)                   ; 13.33 mW (0.00 mW)              ; --                                ; 6.43 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ;
+;             |hdmitx_lvds_tx:auto_generated                      ; 19.77 mW (18.14 mW)                  ; 13.33 mW (12.00 mW)             ; --                                ; 6.43 mW (6.14 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ;
 ;                 |hdmitx_cntr:cntr2                              ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ;
 ;                 |hdmitx_cntr:cntr13                             ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ;
 ;                 |hdmitx_ddio_out:ddio_out                       ; 0.37 mW (0.37 mW)                    ; 0.37 mW (0.37 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ;
 ;                 |hdmitx_shift_reg:outclk_shift_h                ; 0.10 mW (0.10 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.01 mW (0.01 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ;
-;                 |hdmitx_shift_reg:outclk_shift_l                ; 0.08 mW (0.08 mW)                    ; 0.07 mW (0.07 mW)               ; --                                ; 0.01 mW (0.01 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ;
+;                 |hdmitx_shift_reg:outclk_shift_l                ; 0.09 mW (0.09 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.01 mW (0.01 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ;
 ;                 |hdmitx_ddio_out1:outclock_ddio                 ; 0.12 mW (0.12 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ;
-;                 |hdmitx_shift_reg1:shift_reg23                  ; 0.10 mW (0.10 mW)                    ; 0.07 mW (0.07 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ;
-;                 |hdmitx_shift_reg1:shift_reg24                  ; 0.09 mW (0.09 mW)                    ; 0.07 mW (0.07 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ;
-;                 |hdmitx_shift_reg1:shift_reg25                  ; 0.13 mW (0.13 mW)                    ; 0.10 mW (0.10 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ;
-;                 |hdmitx_shift_reg1:shift_reg26                  ; 0.14 mW (0.14 mW)                    ; 0.10 mW (0.10 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ;
-;                 |hdmitx_shift_reg1:shift_reg27                  ; 0.13 mW (0.13 mW)                    ; 0.10 mW (0.10 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ;
+;                 |hdmitx_shift_reg1:shift_reg23                  ; 0.12 mW (0.12 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ;
+;                 |hdmitx_shift_reg1:shift_reg24                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ;
+;                 |hdmitx_shift_reg1:shift_reg25                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ;
+;                 |hdmitx_shift_reg1:shift_reg26                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ;
+;                 |hdmitx_shift_reg1:shift_reg27                  ; 0.14 mW (0.14 mW)                    ; 0.10 mW (0.10 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ;
 ;                 |hdmitx_shift_reg1:shift_reg28                  ; 0.13 mW (0.13 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ;
-;     |pll:pll                                                    ; 16.56 mW (0.00 mW)                   ; 12.39 mW (0.00 mW)              ; --                                ; 4.18 mW (0.00 mW)                 ; |max80|pll:pll                                                                                                     ;
-;         |altpll:altpll_component                                ; 16.56 mW (0.00 mW)                   ; 12.39 mW (0.00 mW)              ; --                                ; 4.18 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component                                                                             ;
-;             |pll_altpll:auto_generated                          ; 16.56 mW (16.56 mW)                  ; 12.39 mW (12.39 mW)             ; --                                ; 4.18 mW (4.18 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ;
+;     |pll:pll                                                    ; 16.58 mW (0.00 mW)                   ; 12.39 mW (0.00 mW)              ; --                                ; 4.19 mW (0.00 mW)                 ; |max80|pll:pll                                                                                                     ;
+;         |altpll:altpll_component                                ; 16.58 mW (0.00 mW)                   ; 12.39 mW (0.00 mW)              ; --                                ; 4.19 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component                                                                             ;
+;             |pll_altpll:auto_generated                          ; 16.58 mW (16.58 mW)                  ; 12.39 mW (12.39 mW)             ; --                                ; 4.19 mW (4.19 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ;
 ;                 |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2   ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ;
 ;                 |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ;
 ;                 |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ;
@@ -290,12 +290,12 @@ https://fpgasoftware.intel.com/eula.
 ; Clock Domain                                                                                        ; Clock Frequency (MHz) ; Total Core Dynamic Power ;
 +-----------------------------------------------------------------------------------------------------+-----------------------+--------------------------+
 ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; 96.00                 ; 13.64                    ;
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; 96.00                 ; 2.72                     ;
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; 36.00                 ; 1.39                     ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; 96.00                 ; 2.66                     ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; 36.00                 ; 1.43                     ;
 ; clock_48                                                                                            ; 48.00                 ; 0.00                     ;
-; rst_n                                                                                               ; 96.00                 ; 2.56                     ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; 180.02                ; 17.89                    ;
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; 36.00                 ; 0.77                     ;
+; rst_n                                                                                               ; 96.00                 ; 2.43                     ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; 180.02                ; 18.81                    ;
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; 36.00                 ; 0.95                     ;
 ; rtc_32khz                                                                                           ; 0.03                  ; 0.00                     ;
 +-----------------------------------------------------------------------------------------------------+-----------------------+--------------------------+
 
@@ -305,9 +305,9 @@ https://fpgasoftware.intel.com/eula.
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
 ; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
-; VCCINT         ; 52.99 mA                ; 12.96 mA                  ; 40.03 mA                 ; 52.99 mA                         ;
+; VCCINT         ; 53.80 mA                ; 13.77 mA                  ; 40.03 mA                 ; 53.80 mA                         ;
 ; VCCIO          ; 28.12 mA                ; 1.01 mA                   ; 27.11 mA                 ; 28.12 mA                         ;
-; VCCA           ; 22.35 mA                ; 4.08 mA                   ; 18.28 mA                 ; 22.35 mA                         ;
+; VCCA           ; 22.36 mA                ; 4.08 mA                   ; 18.28 mA                 ; 22.36 mA                         ;
 ; VCCD           ; 19.07 mA                ; 11.29 mA                  ; 7.78 mA                  ; 19.07 mA                         ;
 +----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
 (1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
@@ -356,9 +356,9 @@ https://fpgasoftware.intel.com/eula.
 ;     -- Number of signals with Static Probability from Node, entity or clock assignment ; 8 (0.9%)    ; 2 (1.1%)   ; 1 (0.5%)    ; 5 (1.0%)      ;
 ;                                                                                        ;             ;            ;             ;               ;
 ; Vectorless estimation                                                                  ;             ;            ;             ;               ;
-;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 803 (90.0%) ; 96 (53.6%) ; 220 (99.5%) ; 487 (99.0%)   ;
-;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 200 (22.4%) ; 92 (51.4%) ; 1 (0.5%)    ; 107 (21.7%)   ;
-;     -- Number of signals with Static Probability from Vectorless estimation            ; 803 (90.0%) ; 96 (53.6%) ; 220 (99.5%) ; 487 (99.0%)   ;
+;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 798 (90.0%) ; 96 (53.6%) ; 220 (99.5%) ; 482 (99.0%)   ;
+;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 200 (22.5%) ; 92 (51.4%) ; 1 (0.5%)    ; 107 (22.0%)   ;
+;     -- Number of signals with Static Probability from Vectorless estimation            ; 798 (90.0%) ; 96 (53.6%) ; 220 (99.5%) ; 482 (99.0%)   ;
 ;                                                                                        ;             ;            ;             ;               ;
 ; Default assignment                                                                     ;             ;            ;             ;               ;
 ;     -- Number of signals with Toggle Rate from Default assignment                      ; 0 (0.0%)    ; 0 (0.0%)   ; 0 (0.0%)    ; 0 (0.0%)      ;
@@ -383,7 +383,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Power Analyzer
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:17:54 2021
+    Info: Processing started: Thu Jul 29 09:27:00 2021
 Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (21077): Low junction temperature is 0 degrees C
@@ -421,12 +421,12 @@ Info (223001): Completed Vectorless Power Activity Estimation
 Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
-Info (215049): Average toggle rate for this design is 11.033 millions of transitions / sec
-Info (215031): Total thermal power estimate for the design is 213.74 mW
+Info (215049): Average toggle rate for this design is 11.008 millions of transitions / sec
+Info (215031): Total thermal power estimate for the design is 214.72 mW
 Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 1264 megabytes
-    Info: Processing ended: Thu Jul 29 01:17:56 2021
-    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:02
+    Info: Peak virtual memory: 1263 megabytes
+    Info: Processing ended: Thu Jul 29 09:27:03 2021
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:03
 
 

output_files/max80.pow.summary

@@ -1,12 +1,12 @@
-Power Analyzer Status : Successful - Thu Jul 29 01:17:56 2021
+Power Analyzer Status : Successful - Thu Jul 29 09:27:03 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80
 Family : Cyclone IV E
 Device : EP4CE15F17C8
 Power Models : Final
-Total Thermal Power Dissipation : 213.74 mW
-Core Dynamic Thermal Power Dissipation : 38.27 mW
+Total Thermal Power Dissipation : 214.72 mW
+Core Dynamic Thermal Power Dissipation : 39.23 mW
 Core Static Thermal Power Dissipation : 60.18 mW
 I/O Thermal Power Dissipation : 115.30 mW
 Power Estimation Confidence : Low: user provided insufficient toggle rate data

output_files/max80.sta.summary

@@ -3,23 +3,23 @@ Timing Analyzer Summary
 ------------------------------------------------------------
 
 Type  : Slow 1200mV 85C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 1.950
+Slack : 1.779
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 4.836
+Slack : 4.943
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 18.699
+Slack : 18.707
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 22.674
+Slack : 22.654
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 0.467
+Slack : 0.466
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
@@ -27,11 +27,11 @@ Slack : 0.504
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.653
+Slack : 0.519
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 2.352
+Slack : 2.160
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
@@ -39,7 +39,7 @@ Slack : 2.477
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 4.910
+Slack : 4.908
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'clock_48'
@@ -47,7 +47,7 @@ Slack : 10.341
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 13.586
+Slack : 13.587
 TNS   : 0.000
 
 Type  : Slow 1200mV 85C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
@@ -59,23 +59,23 @@ Slack : 30513.579
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 2.147
+Slack : 2.014
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 5.372
+Slack : 5.426
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 19.264
+Slack : 19.293
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 22.960
+Slack : 22.954
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 0.419
+Slack : 0.417
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
@@ -83,19 +83,19 @@ Slack : 0.472
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.609
+Slack : 0.480
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 2.189
+Slack : 2.012
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 2.475
+Slack : 2.476
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 4.910
+Slack : 4.908
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'clock_48'
@@ -103,11 +103,11 @@ Slack : 10.354
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 13.586
+Slack : 13.587
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 13.588
+Slack : 13.589
 TNS   : 0.000
 
 Type  : Slow 1200mV 0C Model Minimum Pulse Width 'rtc_32khz'
@@ -115,19 +115,19 @@ Slack : 30513.579
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 3.903
+Slack : 3.799
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 8.006
+Slack : 8.053
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 23.668
+Slack : 23.683
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Setup 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 24.654
+Slack : 24.637
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
@@ -135,19 +135,19 @@ Slack : 0.194
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 0.195
+Slack : 0.194
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 0.269
+Slack : 0.211
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Hold 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
-Slack : 0.989
+Slack : 0.891
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
-Slack : 2.563
+Slack : 2.564
 TNS   : 0.000
 
 Type  : Fast 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[1]'