v2: v2 has a 16 MHz oscillator instead of 48 MHz

The master clock on v2 is a 16 MHz oscillator, not 48 MHz as on
v1. Accordingly, parameterize PLL 2, the master clock PLL, per
version.

fpga/ip/pll2.qip → fpga/ip/pll2_16.qip

@@ -1,6 +1,6 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll2.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2_bb.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2.ppf"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll2_16.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2_16_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2_16.ppf"]

fpga/ip/pll2_16.v

@@ -0,0 +1,319 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll2_16.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll2_16 (
+	areset,
+	inclk0,
+	c0,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "LOW",
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 21,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.inclk0_input_frequency = 62500,
+		altpll_component.intended_device_family = "Cyclone IV E",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2_16",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NO_COMPENSATION",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "ON",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "336.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "16.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "21"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "336.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2_16.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "21"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "62500"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

fpga/ip/pll2_48.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll2_48.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2_48_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2_48.ppf"]

fpga/ip/pll2.v → fpga/ip/pll2_48.v

@@ -4,7 +4,7 @@
 // MODULE: altpll 
 
 // ============================================================
-// File Name: pll2.v
+// File Name: pll2_48.v
 // Megafunction Name(s):
 // 			altpll
 //
@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -37,7 +37,7 @@
 // synopsys translate_off
 `timescale 1 ps / 1 ps
 // synopsys translate_on
-module pll2 (
+module pll2_48 (
 	areset,
 	inclk0,
 	c0,
@@ -103,14 +103,14 @@ module pll2 (
 				.vcooverrange (),
 				.vcounderrange ());
 	defparam
-		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.bandwidth_type = "LOW",
 		altpll_component.clk0_divide_by = 1,
 		altpll_component.clk0_duty_cycle = 50,
 		altpll_component.clk0_multiply_by = 7,
 		altpll_component.clk0_phase_shift = "0",
 		altpll_component.inclk0_input_frequency = 20833,
 		altpll_component.intended_device_family = "Cyclone IV E",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2_48",
 		altpll_component.lpm_type = "altpll",
 		altpll_component.operation_mode = "NO_COMPENSATION",
 		altpll_component.pll_type = "AUTO",
@@ -169,8 +169,8 @@ endmodule
 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
 // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
@@ -179,7 +179,7 @@ endmodule
 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "336.000000"
@@ -225,7 +225,7 @@ endmodule
 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2.mif"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2_48.mif"
 // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
@@ -245,7 +245,7 @@ endmodule
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
@@ -308,12 +308,12 @@ endmodule
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48_bb.v TRUE
 // Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

fpga/max80.qpf

@@ -19,12 +19,12 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 20:20:54  December 26, 2021
+# Date created = 05:39:58  December 27, 2021
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "20:20:54  December 26, 2021"
+DATE = "05:39:58  December 27, 2021"
 
 # Revisions
 

fpga/max80.qsf

@@ -90,7 +90,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk
 
 
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_48
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_*
 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
 set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
 set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[2]
@@ -117,7 +117,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_miso
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_mosi
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to board_id
-set_instance_assignment -name IO_STANDARD "2.5 V" -to clock_48
 
 
 set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
@@ -217,12 +216,10 @@ set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
 set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
 set_global_assignment -name POWER_USE_TA_VALUE 35
 
-
-
-
+# PLL 2 ends up located appropriately without an explicit constraint
 set_location_assignment PLL_3 -to "max80:max80|pll3:pll3|altpll:altpll_component|pll3_altpll:auto_generated|pll1"
 set_location_assignment PLL_4 -to "max80:max80|pll4:pll4|altpll:altpll_component|pll4_altpll:auto_generated|pll1"
-set_location_assignment PLL_2 -to "max80:max80|pll2:pll2|altpll:altpll_component|pll2_altpll:auto_generated|pll1"
+
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[15]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[14]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[13]
@@ -251,7 +248,10 @@ set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
 set_global_assignment -name QIP_FILE ip/int_osc/synthesis/int_osc.qip
 set_global_assignment -name VERILOG_FILE ip/pll4.v
 set_global_assignment -name VERILOG_FILE ip/pll3.v
-set_global_assignment -name VERILOG_FILE ip/pll2.v
+set_global_assignment -name VERILOG_FILE ip/pll2_16.v
+set_global_assignment -name VERILOG_FILE ip/pll2_48.v
+set_global_assignment -name QIP_FILE ip/pll2_16.qip
+set_global_assignment -name QIP_FILE ip/pll2_48.qip
 set_global_assignment -name VERILOG_FILE usb/usb_fs_phy/src_v/usb_fs_phy.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.v

fpga/max80.sdc

@@ -4,6 +4,7 @@
 
 # Input master clock for all PLLs
 create_clock -name "clock_48" -period 20.834ns [get_ports {clock_48}]
+create_clock -name "clock_16" -period 62.500ns [get_ports {clock_16}]
 derive_pll_clocks
 
 # RTC clock; asynchronous with all others
@@ -18,15 +19,16 @@ set_false_path -to [get_registers sld_signaltap:*]
 
 # -------- PLL clock mappings --------
 
+set master_clk    [get_clocks {pll2|*|clk[0]}]
 set sdram_clk     [get_clocks {*|pll3|*|clk[0]}]
 set sdram_out_clk [get_clocks {*|pll3|*|clk[1]}]
 set sys_clk       [get_clocks {*|pll3|*|clk[2]}]
 set flash_clk     [get_clocks {*|pll3|*|clk[3]}]
+set usb_clk       [get_clocks {*|pll3|*|clk[4]}]
 set hdmi_clk      [get_clocks {*|pll4|*|clk[0]}]
 set vid_clk       [get_clocks {*|pll4|*|clk[1]}]
-set usb_clk       [get_clocks {*|pll2|*|clk[0]}]
 
-set main_clocks   [get_clocks {*|pll*|*|clk[*]}]
+set main_clocks   [get_clocks {pll*|*|clk[*] *|pll*|*|clk[*]}]
 
 # Reset isn't actually a clock, but Quartus thinks it is
 create_generated_clock -name rst_n \

fpga/max80.sv

@@ -8,114 +8,117 @@
 // Sharing JTAG pins (via JTAGEN)
 `undef SHARED_JTAG
 
-module max80 
+module max80
   #(parameter logic [6:1] x_mosfet,
     parameter logic [7:0] fpga_ver)
    (
     // Clock oscillator
-    input 	  clock_48, // 48 MHz
-    input 	  board_id, // This better match the firmware
+    input	  master_clk,		// 336 MHz from PLL2
+    input	  master_pll_locked,	// PLL2 is locked, master_clk is good
+    output	  reset_plls,		// Reset all PLLs including PLL2
+
+    input	  board_id, // This better match the firmware
 
     // ABC-bus
-    inout 	  abc_clk, // ABC-bus 3 MHz clock
+    inout	  abc_clk, // ABC-bus 3 MHz clock
     inout [15:0]  abc_a, // ABC address bus
     inout [7:0]   abc_d, // ABC data bus
-    output 	  abc_d_oe, // Data bus output enable
-    inout 	  abc_rst_n, // ABC bus reset strobe
-    inout 	  abc_cs_n, // ABC card select strobe
+    output	  abc_d_oe, // Data bus output enable
+    inout	  abc_rst_n, // ABC bus reset strobe
+    inout	  abc_cs_n, // ABC card select strobe
     inout [4:0]   abc_out_n, // OUT, C1-C4 strobe
     inout [1:0]   abc_inp_n, // INP, STATUS strobe
-    inout 	  abc_xmemfl_n, // Memory read strobe
-    inout 	  abc_xmemw800_n, // Memory write strobe (ABC800)
-    inout 	  abc_xmemw80_n, // Memory write strobe (ABC80)
-    inout 	  abc_xinpstb_n, // I/O read strobe (ABC800)
-    inout 	  abc_xoutpstb_n, // I/O write strobe (ABC80)
+    inout	  abc_xmemfl_n, // Memory read strobe
+    inout	  abc_xmemw800_n, // Memory write strobe (ABC800)
+    inout	  abc_xmemw80_n, // Memory write strobe (ABC80)
+    inout	  abc_xinpstb_n, // I/O read strobe (ABC800)
+    inout	  abc_xoutpstb_n, // I/O write strobe (ABC80)
     // The following are inverted versus the bus IF
     // the corresponding MOSFETs are installed
-    inout 	  abc_rdy_x, // RDY = WAIT#
-    inout 	  abc_resin_x, // System reset request
-    inout 	  abc_int80_x, // System INT request (ABC80)
-    inout 	  abc_int800_x, // System INT request (ABC800)
-    inout 	  abc_nmi_x, // System NMI request (ABC800)
-    inout 	  abc_xm_x, // System memory override (ABC800)
+    inout	  abc_rdy_x, // RDY = WAIT#
+    inout	  abc_resin_x, // System reset request
+    inout	  abc_int80_x, // System INT request (ABC80)
+    inout	  abc_int800_x, // System INT request (ABC800)
+    inout	  abc_nmi_x, // System NMI request (ABC800)
+    inout	  abc_xm_x, // System memory override (ABC800)
     // Host/device control
-    output 	  abc_host, // 1 = host, 0 = target
+    output	  abc_host, // 1 = host, 0 = target
 
     // ABC-bus extension header
     // (Note: cannot use an array here because HC and HH are
     // input only.)
-    inout 	  exth_ha,
-    inout 	  exth_hb,
-    input 	  exth_hc,
-    inout 	  exth_hd,
-    inout 	  exth_he,
-    inout 	  exth_hf,
-    inout 	  exth_hg,
-    input 	  exth_hh,
+    inout	  exth_ha,
+    inout	  exth_hb,
+    input	  exth_hc,
+    inout	  exth_hd,
+    inout	  exth_he,
+    inout	  exth_hf,
+    inout	  exth_hg,
+    input	  exth_hh,
 
     // SDRAM bus
-    output 	  sr_clk,
+    output	  sr_clk,
     output [1:0]  sr_ba, // Bank address
     output [12:0] sr_a, // Address within bank
     inout [15:0]  sr_dq, // Also known as D or IO
     output [1:0]  sr_dqm, // DQML and DQMH
-    output 	  sr_cs_n,
-    output 	  sr_we_n,
-    output 	  sr_cas_n,
-    output 	  sr_ras_n,
+    output	  sr_cs_n,
+    output	  sr_we_n,
+    output	  sr_cas_n,
+    output	  sr_ras_n,
 
     // SD card
-    input 	  sd_cd_n,
-    output 	  sd_cs_n,
-    output 	  sd_clk,
-    output 	  sd_di,
-    input 	  sd_do,
+    input	  sd_cd_n,
+    output	  sd_cs_n,
+    output	  sd_clk,
+    output	  sd_di,
+    input	  sd_do,
 
     // Serial console (naming is FPGA as DCE)
-    input 	  tty_txd,
-    output 	  tty_rxd,
-    input 	  tty_rts,
-    output 	  tty_cts,
-    input 	  tty_dtr,
+    input	  tty_txd,
+    output	  tty_rxd,
+    input	  tty_rts,
+    output	  tty_cts,
+    input	  tty_dtr,
 
     // SPI flash memory (also configuration)
-    output 	  flash_cs_n,
-    output 	  flash_sck,
+    output	  flash_cs_n,
+    output	  flash_sck,
     inout [1:0]   flash_io,
 
     // SPI bus (connected to ESP32 so can be bidirectional)
-    inout 	  spi_clk,
-    inout 	  spi_miso,
-    inout 	  spi_mosi,
-    inout 	  spi_cs_esp_n, // ESP32 IO10
-    inout 	  spi_cs_flash_n, // ESP32 IO01
+    inout	  spi_clk,
+    inout	  spi_miso,
+    inout	  spi_mosi,
+    inout	  spi_cs_esp_n, // ESP32 IO10
+    inout	  spi_cs_flash_n, // ESP32 IO01
 
     // Other ESP32 connections
-    inout 	  esp_io0, // ESP32 IO00
-    inout 	  esp_int, // ESP32 IO09
+    inout	  esp_io0, // ESP32 IO00
+    inout	  esp_int, // ESP32 IO09
 
     // I2C bus (RTC and external)
-    inout 	  i2c_scl,
-    inout 	  i2c_sda,
-    input 	  rtc_32khz,
-    input 	  rtc_int_n,
+    inout	  i2c_scl,
+    inout	  i2c_sda,
+    input	  rtc_32khz,
+    input	  rtc_int_n,
 
     // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
     output [2:0]  led,
 
     // USB
-    inout 	  usb_dp,
-    inout 	  usb_dn,
-    output 	  usb_pu,
-    input 	  usb_rx,
-    input         usb_rx_ok,
+    inout	  usb_dp,
+    inout	  usb_dn,
+    output	  usb_pu,
+    input	  usb_rx,
+    input	  usb_rx_ok,
 
     // HDMI
     output [2:0]  hdmi_d,
-    output 	  hdmi_clk,
-    inout 	  hdmi_scl,
-    inout 	  hdmi_sda,
-    inout 	  hdmi_hpd,
+    output	  hdmi_clk,
+    inout	  hdmi_scl,
+    inout	  hdmi_sda,
+    inout	  hdmi_hpd,
 
     // Unconnected pins with pullups, used for randomness
     inout [2:0]   rngio
@@ -129,13 +132,20 @@ module max80
 
    tri1 [4:1]		    pll_locked;
 
+   assign   reset_plls = 1'b0;
+   assign   pll_locked[2] = master_pll_locked;
+
    //
    // Clocks.
    //
-   //  All clocks are derived from a common 48 MHz oscillator
-   //  connected to clock_48, which is a dedicated clock pin
-   //  feeding into hardware PLL2 and PLL4. The SDRAM clock output
-   //  is a dedicated clock out pin from PLL3.
+   //  All clocks are derived from a common oscillator connected to an
+   //  input clock pin, which is a dedicated clock pin feeding into
+   //  hardware PLL2 and PLL4. The SDRAM clock output is a dedicated
+   //  clock out pin from PLL3.
+   //
+   //  The input frequency is not consistent across board revisions,
+   //  so PLL2 is configured to produce a common master clock (336 MHz)
+   //  in the appropriate top level file.
    //
    //  The following sets of clocks are closely tied and expected to
    //  be synchronous, and therefore should come from the same PLL each;
@@ -144,15 +154,6 @@ module max80
    //  sdram_clk, sys_clk    - 2:1 ratio
    //  vid_hdmiclk, vid_clk  - 5:1 ratio
    //
-   wire     reset_plls = 1'b0;
-   wire     master_clk;		// 336 MHz internal master clock
-   pll2 pll2 (
-	      .areset ( reset_plls ),
-	      .locked ( pll_locked[2] ),
-
-	      .inclk0 ( clock_48 ),
-	      .c0     ( master_clk )
-	      );
 
    wire	    sdram_clk;		// 168 MHz SDRAM clock
    wire	    sys_clk;		//  84 MHz System clock
@@ -312,7 +313,7 @@ module max80
    wire        sdram_valid = cpu_mem_quad[1];
    wire [31:0] sdram_mem_rdata;
    wire        sdram_ready;
-   reg 	       sdram_ready_q;
+   reg	       sdram_ready_q;
    reg	       sdram_mem_ready;
 
    //

fpga/output/v1.pin

@@ -259,7 +259,7 @@ hdmi_scl                     : M11       : bidir  : 3.3-V LVTTL       :
 GNDA4                        : M12       : gnd    :                   :         :           :                
 GND                          : M13       : gnd    :                   :         :           :                
 VCCIO5                       : M14       : power  :                   : 2.5V    : 5         :                
-clock_48                     : M15       : input  : 2.5 V             :         : 5         : Y              
+clock_48                     : M15       : input  : 3.3-V LVTTL       :         : 5         : Y              
 GND+                         : M16       :        :                   :         : 5         :                
 abc_a[15]                    : N1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_a[14]                    : N2        : input  : 3.3-V LVTTL       :         : 2         : Y              

fpga/output/v2.pin

@@ -259,7 +259,7 @@ hdmi_scl                     : M11       : bidir  : 3.3-V LVTTL       :
 GNDA4                        : M12       : gnd    :                   :         :           :                
 GND                          : M13       : gnd    :                   :         :           :                
 VCCIO5                       : M14       : power  :                   : 2.5V    : 5         :                
-clock_48                     : M15       : input  : 2.5 V             :         : 5         : Y              
+clock_16                     : M15       : input  : 3.3-V LVTTL       :         : 5         : Y              
 GND+                         : M16       :        :                   :         : 5         :                
 abc_a[15]                    : N1        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
 abc_a[14]                    : N2        : bidir  : 3.3-V LVTTL       :         : 2         : Y              

fpga/v1.sv

@@ -8,94 +8,94 @@
 module v1
    (
     // Clock oscillator
-    input 	  clock_48, // 48 MHz
-    input 	  board_id, // This better match the firmware
+    input	  clock_48, // 48 MHz
+    input	  board_id, // This better match the firmware
 
     // ABC-bus
-    input 	  abc_clk, // ABC-bus 3 MHz clock
+    input	  abc_clk, // ABC-bus 3 MHz clock
     input [15:0]  abc_a, // ABC address bus
     inout [7:0]   abc_d, // ABC data bus
-    output 	  abc_d_oe, // Data bus output enable
-    input 	  abc_rst_n, // ABC bus reset strobe
-    input 	  abc_cs_n, // ABC card select strobe
+    output	  abc_d_oe, // Data bus output enable
+    input	  abc_rst_n, // ABC bus reset strobe
+    input	  abc_cs_n, // ABC card select strobe
     input [4:0]   abc_out_n, // OUT, C1-C4 strobe
     input [1:0]   abc_inp_n, // INP, STATUS strobe
-    input 	  abc_xmemfl_n, // Memory read strobe
-    input 	  abc_xmemw800_n, // Memory write strobe (ABC800)
-    input 	  abc_xmemw80_n, // Memory write strobe (ABC80)
-    input 	  abc_xinpstb_n, // I/O read strobe (ABC800)
-    input 	  abc_xoutpstb_n, // I/O write strobe (ABC80)
+    input	  abc_xmemfl_n, // Memory read strobe
+    input	  abc_xmemw800_n, // Memory write strobe (ABC800)
+    input	  abc_xmemw80_n, // Memory write strobe (ABC80)
+    input	  abc_xinpstb_n, // I/O read strobe (ABC800)
+    input	  abc_xoutpstb_n, // I/O write strobe (ABC80)
     // The following are inverted versus the bus IF
     // the corresponding MOSFETs are installed
-    output 	  abc_rdy_x, // RDY = WAIT#
-    output 	  abc_resin_x, // System reset request
-    output 	  abc_int80_x, // System INT request (ABC80)
-    output 	  abc_int800_x, // System INT request (ABC800)
-    output 	  abc_nmi_x, // System NMI request (ABC800)
-    output 	  abc_xm_x, // System memory override (ABC800)
+    output	  abc_rdy_x, // RDY = WAIT#
+    output	  abc_resin_x, // System reset request
+    output	  abc_int80_x, // System INT request (ABC80)
+    output	  abc_int800_x, // System INT request (ABC800)
+    output	  abc_nmi_x, // System NMI request (ABC800)
+    output	  abc_xm_x, // System memory override (ABC800)
     // Host/device control
-    output 	  abc_host, // 1 = host, 0 = target
-    output 	  abc_a_oe,
+    output	  abc_host, // 1 = host, 0 = target
+    output	  abc_a_oe,
     // Bus isolation
-    output 	  abc_d_ce_n,
+    output	  abc_d_ce_n,
 
     // ABC-bus extension header
     // (Note: cannot use an array here because HC and HH are
     // input only.)
-    inout 	  exth_ha,
-    inout 	  exth_hb,
-    input 	  exth_hc,
-    inout 	  exth_hd,
-    inout 	  exth_he,
-    inout 	  exth_hf,
-    inout 	  exth_hg,
-    input 	  exth_hh,
+    inout	  exth_ha,
+    inout	  exth_hb,
+    input	  exth_hc,
+    inout	  exth_hd,
+    inout	  exth_he,
+    inout	  exth_hf,
+    inout	  exth_hg,
+    input	  exth_hh,
 
     // SDRAM bus
-    output 	  sr_clk,
-    output 	  sr_cke,
+    output	  sr_clk,
+    output	  sr_cke,
     output [1:0]  sr_ba, // Bank address
     output [12:0] sr_a, // Address within bank
     inout [15:0]  sr_dq, // Also known as D or IO
     output [1:0]  sr_dqm, // DQML and DQMH
-    output 	  sr_cs_n,
-    output 	  sr_we_n,
-    output 	  sr_cas_n,
-    output 	  sr_ras_n,
+    output	  sr_cs_n,
+    output	  sr_we_n,
+    output	  sr_cas_n,
+    output	  sr_ras_n,
 
     // SD card
-    output 	  sd_clk,
-    output 	  sd_cmd,
+    output	  sd_clk,
+    output	  sd_cmd,
     inout [3:0]   sd_dat,
 
     // Serial console (naming is FPGA as DCE)
-    input 	  tty_txd,
-    output 	  tty_rxd,
-    input 	  tty_rts,
-    output 	  tty_cts,
-    input 	  tty_dtr,
+    input	  tty_txd,
+    output	  tty_rxd,
+    input	  tty_rts,
+    output	  tty_cts,
+    input	  tty_dtr,
 
     // SPI flash memory (also configuration)
-    output 	  flash_cs_n,
-    output 	  flash_sck,
+    output	  flash_cs_n,
+    output	  flash_sck,
     inout [1:0]   flash_io,
 
     // SPI bus (connected to ESP32 so can be bidirectional)
-    inout 	  spi_clk,
-    inout 	  spi_miso,
-    inout 	  spi_mosi,
-    inout 	  spi_cs_esp_n, // ESP32 IO10
-    inout 	  spi_cs_flash_n, // ESP32 IO01
+    inout	  spi_clk,
+    inout	  spi_miso,
+    inout	  spi_mosi,
+    inout	  spi_cs_esp_n, // ESP32 IO10
+    inout	  spi_cs_flash_n, // ESP32 IO01
 
     // Other ESP32 connections
-    inout 	  esp_io0, // ESP32 IO00
-    inout 	  esp_int, // ESP32 IO09
+    inout	  esp_io0, // ESP32 IO00
+    inout	  esp_int, // ESP32 IO09
 
     // I2C bus (RTC and external)
-    inout 	  i2c_scl,
-    inout 	  i2c_sda,
-    input 	  rtc_32khz,
-    input 	  rtc_int_n,
+    inout	  i2c_scl,
+    inout	  i2c_sda,
+    input	  rtc_32khz,
+    input	  rtc_int_n,
 
     // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
     output [2:0]  led,
@@ -105,10 +105,10 @@ module v1
 
     // HDMI
     output [2:0]  hdmi_d,
-    output 	  hdmi_clk,
-    inout 	  hdmi_scl,
-    inout 	  hdmi_sda,
-    inout 	  hdmi_hpd,
+    output	  hdmi_clk,
+    inout	  hdmi_scl,
+    inout	  hdmi_sda,
+    inout	  hdmi_hpd,
 
     // Unconnected pins with pullups, used for randomness
     inout [2:0]   rngio
@@ -129,10 +129,25 @@ module v1
    // Always active
    assign sr_cke      = 1'b1;
 
+   // Master PLL: 48 -> 336 MHz
+   wire		  reset_plls;
+   wire		  master_pll_locked;
+   wire		  master_clk;
+
+   pll2_48 pll2 (
+		 .areset ( reset_plls ),
+		 .locked ( master_pll_locked ),
+		 .inclk0 ( clock_48 ),
+		 .c0 ( master_clk )
+		 );
+
+
    max80 #(.x_mosfet(6'b111111),
 	   .fpga_ver(8'd1))
    max80 (
-	  .clock_48               ( clock_48 ),
+	  .master_clk             ( master_clk ),
+	  .master_pll_locked	  ( master_pll_locked ),
+	  .reset_plls             ( reset_plls ),
 	  .board_id               ( board_id ),
 	  .abc_clk                ( abc_clk ),
 	  .abc_a                  ( abc_a ),

fpga/v2.pins

@@ -115,7 +115,7 @@ j16	hdmi_clk(n)
 j15	hdmi_clk
 # m16	GPI  GND
 # j14	GPIO N/C
-m15	clock_48
+m15	clock_16
 # j12	GPIO N/C
 # j13	GPIO N/C
 

fpga/v2.sv

@@ -8,104 +8,104 @@
 module v2
    (
     // Clock oscillator
-    input 	  clock_48, // 48 MHz
-    input 	  board_id, // This better match the firmware
+    input	  clock_16, // 16 MHz
+    input	  board_id, // This better match the firmware
 
     // ABC-bus
-    inout 	  abc_clk, // ABC-bus 3 MHz clock
+    inout	  abc_clk, // ABC-bus 3 MHz clock
     inout [15:0]  abc_a, // ABC address bus
     inout [7:0]   abc_d, // ABC data bus
-    output 	  abc_d_oe, // Data bus inout enable
-    inout 	  abc_rst_n, // ABC bus reset strobe
-    inout 	  abc_cs_n, // ABC card select strobe
+    output	  abc_d_oe, // Data bus inout enable
+    inout	  abc_rst_n, // ABC bus reset strobe
+    inout	  abc_cs_n, // ABC card select strobe
     inout [4:0]   abc_out_n, // OUT, C1-C4 strobe
     inout [1:0]   abc_inp_n, // INP, STATUS strobe
-    inout 	  abc_xmemfl_n, // Memory read strobe
-    inout 	  abc_xmemw800_n, // Memory write strobe (ABC800)
-    inout 	  abc_xmemw80_n, // Memory write strobe (ABC80)
-    inout 	  abc_xinpstb_n, // I/O read strobe (ABC800)
-    inout 	  abc_xoutpstb_n, // I/O write strobe (ABC80)
+    inout	  abc_xmemfl_n, // Memory read strobe
+    inout	  abc_xmemw800_n, // Memory write strobe (ABC800)
+    inout	  abc_xmemw80_n, // Memory write strobe (ABC80)
+    inout	  abc_xinpstb_n, // I/O read strobe (ABC800)
+    inout	  abc_xoutpstb_n, // I/O write strobe (ABC80)
     // The following are inverted versus the bus IF
     // the corresponding MOSFETs are installed
-    inout 	  abc_rdy_x, // RDY = WAIT#
-    inout 	  abc_resin_x, // System reset request
-    inout 	  abc_int80_x, // System INT request (ABC80)
-    inout 	  abc_int800_x, // System INT request (ABC800)
-    inout 	  abc_nmi_x, // System NMI request (ABC800)
-    inout 	  abc_xm_x, // System memory override (ABC800)
+    inout	  abc_rdy_x, // RDY = WAIT#
+    inout	  abc_resin_x, // System reset request
+    inout	  abc_int80_x, // System INT request (ABC80)
+    inout	  abc_int800_x, // System INT request (ABC800)
+    inout	  abc_nmi_x, // System NMI request (ABC800)
+    inout	  abc_xm_x, // System memory override (ABC800)
     // Host/device control
-    output 	  abc_host, // 1 = host, 0 = target
+    output	  abc_host, // 1 = host, 0 = target
 
     // ABC-bus extension header
     // (Note: cannot use an array here because HC and HH are
     // input only.)
-    inout 	  exth_ha,
-    inout 	  exth_hb,
-    input 	  exth_hc,
-    inout 	  exth_hd,
-    inout 	  exth_he,
-    inout 	  exth_hf,
-    inout 	  exth_hg,
-    input 	  exth_hh,
+    inout	  exth_ha,
+    inout	  exth_hb,
+    input	  exth_hc,
+    inout	  exth_hd,
+    inout	  exth_he,
+    inout	  exth_hf,
+    inout	  exth_hg,
+    input	  exth_hh,
 
     // SDRAM bus
-    output 	  sr_clk,
+    output	  sr_clk,
     output [1:0]  sr_ba, // Bank address
     output [12:0] sr_a, // Address within bank
     inout [15:0]  sr_dq, // Also known as D or IO
     output [1:0]  sr_dqm, // DQML and DQMH
-    output 	  sr_cs_n,
-    output 	  sr_we_n,
-    output 	  sr_cas_n,
-    output 	  sr_ras_n,
+    output	  sr_cs_n,
+    output	  sr_we_n,
+    output	  sr_cas_n,
+    output	  sr_ras_n,
 
     // SD card
-    input 	  sd_cd_n,
-    output 	  sd_cs_n,
-    output 	  sd_clk,
-    output 	  sd_di,
-    input 	  sd_do,
+    input	  sd_cd_n,
+    output	  sd_cs_n,
+    output	  sd_clk,
+    output	  sd_di,
+    input	  sd_do,
 
     // SPI flash memory (also configuration)
-    output 	  flash_cs_n,
-    output 	  flash_sck,
+    output	  flash_cs_n,
+    output	  flash_sck,
     inout [1:0]   flash_io,
 
     // SPI bus (connected to ESP32 so can be bidirectional)
-    inout 	  spi_clk,
-    inout 	  spi_miso,
-    inout 	  spi_mosi,
-    inout 	  spi_cs_esp_n, // ESP32 IO10
-    inout 	  spi_cs_flash_n, // ESP32 IO01
+    inout	  spi_clk,
+    inout	  spi_miso,
+    inout	  spi_mosi,
+    inout	  spi_cs_esp_n, // ESP32 IO10
+    inout	  spi_cs_flash_n, // ESP32 IO01
 
     // Other ESP32 connections
-    inout 	  esp_io0, // ESP32 IO00
-    inout 	  esp_int, // ESP32 IO09
+    inout	  esp_io0, // ESP32 IO00
+    inout	  esp_int, // ESP32 IO09
 
     // I2C bus (RTC and external)
-    inout 	  i2c_scl,
-    inout 	  i2c_sda,
-    input 	  rtc_32khz,
-    input 	  rtc_int_n,
+    inout	  i2c_scl,
+    inout	  i2c_sda,
+    input	  rtc_32khz,
+    input	  rtc_int_n,
 
     // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
     output [2:0]  led,
 
     // USB
-    inout 	  usb_dp,
-    inout 	  usb_dn,
-    output 	  usb_pu,
-    input 	  usb_rx,
+    inout	  usb_dp,
+    inout	  usb_dn,
+    output	  usb_pu,
+    input	  usb_rx,
 
     // GPIO
     inout [5:0]   gpio,
 
     // HDMI
     output [2:0]  hdmi_d,
-    output 	  hdmi_clk,
-    inout 	  hdmi_scl,
-    inout 	  hdmi_sda,
-    inout 	  hdmi_hpd,
+    output	  hdmi_clk,
+    inout	  hdmi_scl,
+    inout	  hdmi_sda,
+    inout	  hdmi_hpd,
 
     // Unconnected pins with pullups, used for randomness
     inout [2:0]   rngio
@@ -115,16 +115,31 @@ module v2
    // gpio[0] - TxD
    // gpio[2] - RxD
    // gpio[4] - DTR#
-   
+
    // Permanently unused
    assign gpio[1] = 1'bz;
    assign gpio[3] = 1'bz;
    assign gpio[5] = 1'bz;
 
+   // Master PLL: 16 -> 336 MHz
+   wire		  reset_plls;
+   wire		  master_pll_locked;
+   wire		  master_clk;
+
+   pll2_16 pll2 (
+		 .areset ( reset_plls ),
+		 .locked ( master_pll_locked ),
+		 .inclk0 ( clock_16 ),
+		 .c0 ( master_clk )
+		 );
+
+
    max80 #(.x_mosfet(6'b000000),
 	   .fpga_ver(8'd2))
    max80 (
-	  .clock_48               ( clock_48 ),
+	  .master_clk             ( master_clk ),
+	  .master_pll_locked	  ( master_pll_locked ),
+	  .reset_plls             ( reset_plls ),
 	  .board_id               ( board_id ),
 	  .abc_clk                ( abc_clk ),
 	  .abc_a                  ( abc_a ),