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@@ -1,5 +1,5 @@
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Fitter report for max80
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-Wed Jul 28 12:56:07 2021
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+Thu Jul 29 01:11:26 2021
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Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
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@@ -73,14 +73,14 @@ https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Fitter Summary ;
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+------------------------------------+---------------------------------------------+
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-; Fitter Status ; Successful - Wed Jul 28 12:56:07 2021 ;
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+; Fitter Status ; Successful - Thu Jul 29 01:11:26 2021 ;
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; Quartus Prime Version ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
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; Revision Name ; max80 ;
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; Top-level Entity Name ; max80 ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE15F17C8 ;
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; Timing Models ; Final ;
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-; Total logic elements ; 332 / 15,408 ( 2 % ) ;
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+; Total logic elements ; 328 / 15,408 ( 2 % ) ;
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; Total combinational functions ; 277 / 15,408 ( 2 % ) ;
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; Dedicated logic registers ; 218 / 15,408 ( 1 % ) ;
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; Total registers ; 229 ;
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@@ -166,7 +166,7 @@ https://fpgasoftware.intel.com/eula.
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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-; Processor 2 ; 0.7% ;
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+; Processor 2 ; 0.6% ;
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+----------------------------+-------------+
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@@ -217,8 +217,8 @@ https://fpgasoftware.intel.com/eula.
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; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
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+---------------------+--------------------+----------------------------+--------------------------+
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; Placement (by node) ; ; ; ;
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-; -- Requested ; 0.00 % ( 0 / 815 ) ; 0.00 % ( 0 / 815 ) ; 0.00 % ( 0 / 815 ) ;
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-; -- Achieved ; 0.00 % ( 0 / 815 ) ; 0.00 % ( 0 / 815 ) ; 0.00 % ( 0 / 815 ) ;
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+; -- Requested ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 ) ;
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+; -- Achieved ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 ) ; 0.00 % ( 0 / 816 ) ;
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; ; ; ; ;
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; Routing (by net) ; ; ; ;
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; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
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@@ -241,7 +241,7 @@ https://fpgasoftware.intel.com/eula.
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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-; Top ; 0.00 % ( 0 / 786 ) ; N/A ; Source File ; N/A ; ;
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+; Top ; 0.00 % ( 0 / 787 ) ; N/A ; Source File ; N/A ; ;
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; hard_block:auto_generated_inst ; 0.00 % ( 0 / 29 ) ; N/A ; Source File ; N/A ; ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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@@ -257,16 +257,16 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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+---------------------------------------------+----------------------+
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; Resource ; Usage ;
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+---------------------------------------------+----------------------+
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-; Total logic elements ; 332 / 15,408 ( 2 % ) ;
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-; -- Combinational with no register ; 114 ;
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-; -- Register only ; 55 ;
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-; -- Combinational with a register ; 163 ;
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+; Total logic elements ; 328 / 15,408 ( 2 % ) ;
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+; -- Combinational with no register ; 110 ;
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+; -- Register only ; 51 ;
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+; -- Combinational with a register ; 167 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 105 ;
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; -- 3 input functions ; 65 ;
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; -- <=2 input functions ; 107 ;
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-; -- Register only ; 55 ;
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+; -- Register only ; 51 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 220 ;
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@@ -276,7 +276,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; -- Dedicated logic registers ; 218 / 15,408 ( 1 % ) ;
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; -- I/O registers ; 11 / 758 ( 1 % ) ;
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; ; ;
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-; Total LABs: partially or completely used ; 31 / 963 ( 3 % ) ;
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+; Total LABs: partially or completely used ; 30 / 963 ( 3 % ) ;
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; Virtual pins ; 0 ;
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; I/O pins ; 134 / 166 ( 81 % ) ;
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; -- Clock pins ; 4 / 3 ( 133 % ) ;
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@@ -287,19 +287,19 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; Total block memory implementation bits ; 0 / 516,096 ( 0 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % ) ;
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; PLLs ; 2 / 2 ( 100 % ) ;
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-; Global signals ; 5 ;
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-; -- Global clocks ; 5 / 20 ( 25 % ) ;
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+; Global signals ; 6 ;
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+; -- Global clocks ; 6 / 20 ( 30 % ) ;
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; JTAGs ; 0 / 1 ( 0 % ) ;
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; CRC blocks ; 0 / 1 ( 0 % ) ;
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; ASMI blocks ; 0 / 1 ( 0 % ) ;
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; Oscillator blocks ; 0 / 1 ( 0 % ) ;
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; Impedance control blocks ; 0 / 4 ( 0 % ) ;
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-; Average interconnect usage (total/H/V) ; 0.4% / 0.5% / 0.4% ;
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-; Peak interconnect usage (total/H/V) ; 2.9% / 3.2% / 2.6% ;
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+; Average interconnect usage (total/H/V) ; 0.3% / 0.3% / 0.3% ;
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+; Peak interconnect usage (total/H/V) ; 2.2% / 2.5% / 1.7% ;
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; Maximum fan-out ; 90 ;
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-; Highest non-global fan-out ; 76 ;
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-; Total fan-out ; 1634 ;
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-; Average fan-out ; 1.88 ;
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+; Highest non-global fan-out ; 42 ;
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+; Total fan-out ; 1632 ;
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+; Average fan-out ; 1.89 ;
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+---------------------------------------------+----------------------+
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* Register count does not include registers inside RAM blocks or DSP blocks.
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@@ -312,16 +312,16 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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+---------------------------------------------+---------------------+--------------------------------+
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; Difficulty Clustering Region ; Low ; Low ;
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; ; ; ;
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-; Total logic elements ; 326 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % ) ;
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-; -- Combinational with no register ; 108 ; 6 ;
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-; -- Register only ; 55 ; 0 ;
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-; -- Combinational with a register ; 163 ; 0 ;
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+; Total logic elements ; 322 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % ) ;
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+; -- Combinational with no register ; 104 ; 6 ;
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+; -- Register only ; 51 ; 0 ;
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+; -- Combinational with a register ; 167 ; 0 ;
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; ; ; ;
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; Logic element usage by number of LUT inputs ; ; ;
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; -- 4 input functions ; 102 ; 3 ;
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; -- 3 input functions ; 65 ; 0 ;
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; -- <=2 input functions ; 104 ; 3 ;
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-; -- Register only ; 55 ; 0 ;
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+; -- Register only ; 51 ; 0 ;
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; ; ; ;
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; Logic elements by mode ; ; ;
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; -- normal mode ; 214 ; 6 ;
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@@ -331,7 +331,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; -- Dedicated logic registers ; 218 / 15408 ( 1 % ) ; 0 / 15408 ( 0 % ) ;
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; -- I/O registers ; 6 ; 16 ;
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; ; ; ;
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-; Total LABs: partially or completely used ; 31 / 963 ( 3 % ) ; 1 / 963 ( < 1 % ) ;
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+; Total LABs: partially or completely used ; 30 / 963 ( 3 % ) ; 1 / 963 ( < 1 % ) ;
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; ; ; ;
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; Virtual pins ; 0 ; 0 ;
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; I/O pins ; 126 ; 8 ;
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@@ -339,7 +339,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; Total memory bits ; 0 ; 0 ;
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; Total RAM block bits ; 0 ; 0 ;
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; PLL ; 0 / 2 ( 0 % ) ; 2 / 2 ( 100 % ) ;
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-; Clock control block ; 0 / 24 ( 0 % ) ; 5 / 24 ( 20 % ) ;
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+; Clock control block ; 1 / 24 ( 4 % ) ; 5 / 24 ( 20 % ) ;
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; Double Data Rate I/O output circuitry ; 3 / 336 ( < 1 % ) ; 4 / 336 ( 1 % ) ;
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; ; ; ;
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; Connections ; ; ;
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@@ -349,8 +349,8 @@ The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/ma
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; -- Registered Output Connections ; 8 ; 0 ;
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; ; ; ;
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; Internal Connections ; ; ;
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-; -- Total Connections ; 1598 ; 291 ;
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-; -- Registered Connections ; 840 ; 0 ;
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+; -- Total Connections ; 1596 ; 291 ;
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+; -- Registered Connections ; 766 ; 0 ;
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; ; ; ;
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; External Connections ; ; ;
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; -- Top ; 90 ; 247 ;
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@@ -1023,12 +1023,12 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
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+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
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; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
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-; |max80 ; 332 (67) ; 218 (66) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 134 ; 0 ; 114 (1) ; 55 (3) ; 163 (50) ; |max80 ; max80 ; work ;
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-; |hdmitx:hdmitx| ; 119 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 40 (0) ; 69 (0) ; |max80|hdmitx:hdmitx ; hdmitx ; work ;
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-; |altlvds_tx:ALTLVDS_TX_component| ; 119 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 40 (0) ; 69 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ; altlvds_tx ; work ;
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-; |hdmitx_lvds_tx:auto_generated| ; 119 (60) ; 109 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (1) ; 40 (39) ; 69 (20) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ; hdmitx_lvds_tx ; work ;
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-; |hdmitx_cntr:cntr13| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13 ; hdmitx_cntr ; work ;
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-; |hdmitx_cntr:cntr2| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 3 (3) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2 ; hdmitx_cntr ; work ;
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+; |max80 ; 328 (67) ; 218 (66) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 134 ; 0 ; 110 (1) ; 51 (1) ; 167 (50) ; |max80 ; max80 ; work ;
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+; |hdmitx:hdmitx| ; 119 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 41 (0) ; 68 (0) ; |max80|hdmitx:hdmitx ; hdmitx ; work ;
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+; |altlvds_tx:ALTLVDS_TX_component| ; 119 (0) ; 109 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 41 (0) ; 68 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ; altlvds_tx ; work ;
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+; |hdmitx_lvds_tx:auto_generated| ; 119 (61) ; 109 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (1) ; 41 (40) ; 68 (19) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ; hdmitx_lvds_tx ; work ;
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+; |hdmitx_cntr:cntr13| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 3 (3) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13 ; hdmitx_cntr ; work ;
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+; |hdmitx_cntr:cntr2| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2 ; hdmitx_cntr ; work ;
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; |hdmitx_ddio_out1:outclock_ddio| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio ; hdmitx_ddio_out1 ; work ;
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; |hdmitx_ddio_out:ddio_out| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out ; hdmitx_ddio_out ; work ;
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; |hdmitx_shift_reg1:shift_reg23| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23 ; hdmitx_shift_reg1 ; work ;
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@@ -1045,9 +1045,9 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
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; |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; pll_altpll_dyn_phase_le12 ; work ;
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; |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ; pll_altpll_dyn_phase_le1 ; work ;
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; |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ; pll_altpll_dyn_phase_le ; work ;
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-; |tmdsenc:hdmitmds[0].enc| ; 51 (51) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 17 (17) ; |max80|tmdsenc:hdmitmds[0].enc ; tmdsenc ; work ;
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-; |tmdsenc:hdmitmds[1].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 16 (16) ; |max80|tmdsenc:hdmitmds[1].enc ; tmdsenc ; work ;
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-; |tmdsenc:hdmitmds[2].enc| ; 53 (53) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 (35) ; 6 (6) ; 12 (12) ; |max80|tmdsenc:hdmitmds[2].enc ; tmdsenc ; work ;
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+; |tmdsenc:hdmitmds[0].enc| ; 51 (51) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 3 (3) ; 18 (18) ; |max80|tmdsenc:hdmitmds[0].enc ; tmdsenc ; work ;
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+; |tmdsenc:hdmitmds[1].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 3 (3) ; 15 (15) ; |max80|tmdsenc:hdmitmds[1].enc ; tmdsenc ; work ;
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+; |tmdsenc:hdmitmds[2].enc| ; 50 (50) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 3 (3) ; 16 (16) ; |max80|tmdsenc:hdmitmds[2].enc ; tmdsenc ; work ;
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+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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@@ -1292,27 +1292,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
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+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
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; clock_48 ; PIN_M15 ; 1 ; Clock ; no ; -- ; -- ; -- ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; FF_X15_Y26_N19 ; 41 ; Clock enable ; no ; -- ; -- ; -- ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; FF_X23_Y21_N17 ; 41 ; Clock enable ; no ; -- ; -- ; -- ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
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; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; Clock ; yes ; Global Clock ; GCLK7 ; -- ;
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; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; Clock ; yes ; Global Clock ; GCLK9 ; -- ;
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; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked ; PLL_2 ; 13 ; Async. clear ; no ; -- ; -- ; -- ;
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-; rst_n ; FF_X15_Y23_N29 ; 76 ; Async. clear ; no ; -- ; -- ; -- ;
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-; tmdsenc:hdmitmds[0].enc|denreg ; FF_X14_Y23_N27 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
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+; rst_n ; FF_X40_Y27_N27 ; 75 ; Async. clear ; yes ; Global Clock ; GCLK5 ; -- ;
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+; tmdsenc:hdmitmds[0].enc|denreg ; FF_X26_Y23_N7 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
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+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
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-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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-; Global & Other Fast Signals ;
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-+-----------------------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
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-; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
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-+-----------------------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; 0 ; Global Clock ; GCLK3 ; -- ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; 0 ; Global Clock ; GCLK4 ; -- ;
|
|
|
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ;
|
|
|
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; 0 ; Global Clock ; GCLK7 ; -- ;
|
|
|
-; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; 0 ; Global Clock ; GCLK9 ; -- ;
|
|
|
-+-----------------------------------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
+; Global & Other Fast Signals ;
|
|
|
++-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
+; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
|
|
++-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ; PLL_1 ; 82 ; 0 ; Global Clock ; GCLK3 ; -- ;
|
|
|
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1 ; 31 ; 0 ; Global Clock ; GCLK4 ; -- ;
|
|
|
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ;
|
|
|
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_2 ; 45 ; 0 ; Global Clock ; GCLK7 ; -- ;
|
|
|
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; PLL_2 ; 68 ; 0 ; Global Clock ; GCLK9 ; -- ;
|
|
|
+; rst_n ; FF_X40_Y27_N27 ; 75 ; 0 ; Global Clock ; GCLK5 ; -- ;
|
|
|
++-----------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
|
|
|
|
|
|
+------------------------------------------------+
|
|
|
@@ -1320,137 +1321,144 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+-----------------------+------------------------+
|
|
|
; Routing Resource Type ; Usage ;
|
|
|
+-----------------------+------------------------+
|
|
|
-; Block interconnects ; 264 / 47,787 ( < 1 % ) ;
|
|
|
-; C16 interconnects ; 8 / 1,804 ( < 1 % ) ;
|
|
|
-; C4 interconnects ; 114 / 31,272 ( < 1 % ) ;
|
|
|
-; Direct links ; 65 / 47,787 ( < 1 % ) ;
|
|
|
-; Global clocks ; 5 / 20 ( 25 % ) ;
|
|
|
-; Local interconnects ; 214 / 15,408 ( 1 % ) ;
|
|
|
-; R24 interconnects ; 9 / 1,775 ( < 1 % ) ;
|
|
|
-; R4 interconnects ; 158 / 41,310 ( < 1 % ) ;
|
|
|
+; Block interconnects ; 241 / 47,787 ( < 1 % ) ;
|
|
|
+; C16 interconnects ; 5 / 1,804 ( < 1 % ) ;
|
|
|
+; C4 interconnects ; 72 / 31,272 ( < 1 % ) ;
|
|
|
+; Direct links ; 89 / 47,787 ( < 1 % ) ;
|
|
|
+; Global clocks ; 6 / 20 ( 30 % ) ;
|
|
|
+; Local interconnects ; 205 / 15,408 ( 1 % ) ;
|
|
|
+; R24 interconnects ; 5 / 1,775 ( < 1 % ) ;
|
|
|
+; R4 interconnects ; 103 / 41,310 ( < 1 % ) ;
|
|
|
+-----------------------+------------------------+
|
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
|
; LAB Logic Elements ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; Number of Logic Elements (Average = 10.71) ; Number of LABs (Total = 31) ;
|
|
|
+; Number of Logic Elements (Average = 10.93) ; Number of LABs (Total = 30) ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; 1 ; 3 ;
|
|
|
-; 2 ; 2 ;
|
|
|
-; 3 ; 0 ;
|
|
|
-; 4 ; 2 ;
|
|
|
-; 5 ; 1 ;
|
|
|
+; 1 ; 5 ;
|
|
|
+; 2 ; 1 ;
|
|
|
+; 3 ; 1 ;
|
|
|
+; 4 ; 0 ;
|
|
|
+; 5 ; 0 ;
|
|
|
; 6 ; 0 ;
|
|
|
-; 7 ; 2 ;
|
|
|
-; 8 ; 0 ;
|
|
|
+; 7 ; 1 ;
|
|
|
+; 8 ; 1 ;
|
|
|
; 9 ; 0 ;
|
|
|
-; 10 ; 2 ;
|
|
|
+; 10 ; 3 ;
|
|
|
; 11 ; 0 ;
|
|
|
-; 12 ; 2 ;
|
|
|
+; 12 ; 0 ;
|
|
|
; 13 ; 3 ;
|
|
|
-; 14 ; 4 ;
|
|
|
-; 15 ; 1 ;
|
|
|
-; 16 ; 9 ;
|
|
|
+; 14 ; 2 ;
|
|
|
+; 15 ; 2 ;
|
|
|
+; 16 ; 11 ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+-------------------------------------------------------------------+
|
|
|
; LAB-wide Signals ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
-; LAB-wide Signals (Average = 1.52) ; Number of LABs (Total = 31) ;
|
|
|
+; LAB-wide Signals (Average = 1.37) ; Number of LABs (Total = 30) ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
-; 1 Async. clear ; 11 ;
|
|
|
-; 1 Clock ; 21 ;
|
|
|
-; 1 Clock enable ; 3 ;
|
|
|
-; 1 Sync. clear ; 4 ;
|
|
|
-; 1 Sync. load ; 1 ;
|
|
|
-; 2 Clocks ; 7 ;
|
|
|
+; 1 Async. clear ; 10 ;
|
|
|
+; 1 Clock ; 18 ;
|
|
|
+; 1 Clock enable ; 2 ;
|
|
|
+; 1 Sync. clear ; 3 ;
|
|
|
+; 2 Clocks ; 8 ;
|
|
|
+------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------------+
|
|
|
; LAB Signals Sourced ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
-; Number of Signals Sourced (Average = 17.45) ; Number of LABs (Total = 31) ;
|
|
|
+; Number of Signals Sourced (Average = 17.93) ; Number of LABs (Total = 30) ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
; 0 ; 0 ;
|
|
|
-; 1 ; 1 ;
|
|
|
-; 2 ; 3 ;
|
|
|
+; 1 ; 3 ;
|
|
|
+; 2 ; 2 ;
|
|
|
; 3 ; 1 ;
|
|
|
-; 4 ; 0 ;
|
|
|
+; 4 ; 1 ;
|
|
|
; 5 ; 0 ;
|
|
|
; 6 ; 0 ;
|
|
|
-; 7 ; 2 ;
|
|
|
-; 8 ; 1 ;
|
|
|
-; 9 ; 1 ;
|
|
|
+; 7 ; 1 ;
|
|
|
+; 8 ; 0 ;
|
|
|
+; 9 ; 0 ;
|
|
|
; 10 ; 0 ;
|
|
|
; 11 ; 0 ;
|
|
|
; 12 ; 0 ;
|
|
|
; 13 ; 0 ;
|
|
|
-; 14 ; 2 ;
|
|
|
+; 14 ; 0 ;
|
|
|
; 15 ; 0 ;
|
|
|
-; 16 ; 0 ;
|
|
|
+; 16 ; 1 ;
|
|
|
; 17 ; 0 ;
|
|
|
; 18 ; 0 ;
|
|
|
-; 19 ; 3 ;
|
|
|
-; 20 ; 2 ;
|
|
|
-; 21 ; 0 ;
|
|
|
-; 22 ; 2 ;
|
|
|
-; 23 ; 5 ;
|
|
|
+; 19 ; 4 ;
|
|
|
+; 20 ; 1 ;
|
|
|
+; 21 ; 2 ;
|
|
|
+; 22 ; 0 ;
|
|
|
+; 23 ; 4 ;
|
|
|
; 24 ; 2 ;
|
|
|
; 25 ; 1 ;
|
|
|
-; 26 ; 1 ;
|
|
|
-; 27 ; 1 ;
|
|
|
-; 28 ; 1 ;
|
|
|
-; 29 ; 0 ;
|
|
|
+; 26 ; 2 ;
|
|
|
+; 27 ; 0 ;
|
|
|
+; 28 ; 2 ;
|
|
|
+; 29 ; 1 ;
|
|
|
; 30 ; 1 ;
|
|
|
-; 31 ; 0 ;
|
|
|
-; 32 ; 1 ;
|
|
|
+; 31 ; 1 ;
|
|
|
+----------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+--------------------------------------------------------------------------------+
|
|
|
; LAB Signals Sourced Out ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
-; Number of Signals Sourced Out (Average = 4.39) ; Number of LABs (Total = 31) ;
|
|
|
+; Number of Signals Sourced Out (Average = 4.80) ; Number of LABs (Total = 30) ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
; 0 ; 1 ;
|
|
|
-; 1 ; 3 ;
|
|
|
-; 2 ; 8 ;
|
|
|
-; 3 ; 5 ;
|
|
|
-; 4 ; 3 ;
|
|
|
+; 1 ; 9 ;
|
|
|
+; 2 ; 4 ;
|
|
|
+; 3 ; 4 ;
|
|
|
+; 4 ; 2 ;
|
|
|
; 5 ; 1 ;
|
|
|
-; 6 ; 1 ;
|
|
|
-; 7 ; 2 ;
|
|
|
-; 8 ; 2 ;
|
|
|
-; 9 ; 2 ;
|
|
|
-; 10 ; 2 ;
|
|
|
+; 6 ; 0 ;
|
|
|
+; 7 ; 1 ;
|
|
|
+; 8 ; 1 ;
|
|
|
+; 9 ; 0 ;
|
|
|
+; 10 ; 1 ;
|
|
|
; 11 ; 1 ;
|
|
|
+; 12 ; 2 ;
|
|
|
+; 13 ; 1 ;
|
|
|
+; 14 ; 1 ;
|
|
|
+; 15 ; 1 ;
|
|
|
+-------------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------------+
|
|
|
; LAB Distinct Inputs ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
-; Number of Distinct Inputs (Average = 7.00) ; Number of LABs (Total = 31) ;
|
|
|
+; Number of Distinct Inputs (Average = 6.57) ; Number of LABs (Total = 30) ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
; 0 ; 0 ;
|
|
|
; 1 ; 0 ;
|
|
|
-; 2 ; 5 ;
|
|
|
-; 3 ; 5 ;
|
|
|
-; 4 ; 1 ;
|
|
|
-; 5 ; 5 ;
|
|
|
-; 6 ; 1 ;
|
|
|
+; 2 ; 6 ;
|
|
|
+; 3 ; 8 ;
|
|
|
+; 4 ; 0 ;
|
|
|
+; 5 ; 3 ;
|
|
|
+; 6 ; 0 ;
|
|
|
; 7 ; 0 ;
|
|
|
-; 8 ; 0 ;
|
|
|
+; 8 ; 4 ;
|
|
|
; 9 ; 0 ;
|
|
|
-; 10 ; 4 ;
|
|
|
+; 10 ; 1 ;
|
|
|
; 11 ; 1 ;
|
|
|
-; 12 ; 3 ;
|
|
|
-; 13 ; 2 ;
|
|
|
-; 14 ; 1 ;
|
|
|
-; 15 ; 2 ;
|
|
|
+; 12 ; 1 ;
|
|
|
+; 13 ; 1 ;
|
|
|
+; 14 ; 0 ;
|
|
|
+; 15 ; 1 ;
|
|
|
+; 16 ; 1 ;
|
|
|
+; 17 ; 1 ;
|
|
|
+; 18 ; 0 ;
|
|
|
+; 19 ; 0 ;
|
|
|
+; 20 ; 1 ;
|
|
|
+---------------------------------------------+------------------------------+
|
|
|
|
|
|
|
|
|
@@ -1693,7 +1701,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|
|
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
|
|
|
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
|
|
|
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
|
|
|
-; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 6.4 ;
|
|
|
+; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 15.3 ;
|
|
|
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
|
|
|
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
|
|
|
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
|
|
|
@@ -1704,25 +1712,41 @@ This will disable optimization of problematic paths and expose them for further
|
|
|
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
|
|
|
; Source Register ; Destination Register ; Delay Added in ns ;
|
|
|
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2] ; 0.584 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3] ; 0.584 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4] ; 0.584 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0] ; 0.584 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1] ; 0.584 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2] ; 0.584 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3] ; 0.584 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.433 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4] ; 0.330 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1] ; 0.302 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3] ; 0.298 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0] ; 0.273 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1] ; 0.242 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.185 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.185 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.185 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.185 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.185 ;
|
|
|
-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.185 ;
|
|
|
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; 0.579 ;
|
|
|
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1] ; 0.579 ;
|
|
|
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2] ; 0.579 ;
|
|
|
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4] ; 0.579 ;
|
|
|
+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4] ; 0.579 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.430 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4] ; 0.276 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1] ; 0.275 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3] ; 0.275 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1] ; 0.275 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2] ; 0.182 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.044 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.044 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2] ; 0.044 ;
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+; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4] ; 0.043 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; 0.025 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; 0.025 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; 0.025 ;
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@@ -1730,9 +1754,8 @@ This will disable optimization of problematic paths and expose them for further
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; 0.025 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; 0.025 ;
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; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; 0.025 ;
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-; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3] ; 0.024 ;
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+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
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-Note: This table only shows the top 27 path(s) that have the largest delay added for hold.
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+Note: This table only shows the top 42 path(s) that have the largest delay added for hold.
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|
+-----------------+
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@@ -1806,13 +1829,37 @@ Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(1
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Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
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Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
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Info (332050): run_legacy_fitter_flow File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
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-Critical Warning (332012): Synopsys Design Constraints File file not found: 'max80.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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-Info (332144): No user constrained generated clocks found in the design
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-Info (332144): No user constrained base clocks found in the design
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-Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
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|
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
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+Info (332104): Reading SDC File: 'max80.sdc'
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+Info (332110): Deriving PLL clocks
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+ Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[0]} {pll|altpll_component|auto_generated|pll1|clk[0]}
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+ Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[1]} {pll|altpll_component|auto_generated|pll1|clk[1]}
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+ Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 4 -multiply_by 3 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[2]} {pll|altpll_component|auto_generated|pll1|clk[2]}
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+ Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -multiply_by 5 -phase -90.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]}
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+ Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -phase -18.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]}
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|
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+Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
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|
|
+Warning (332174): Ignored filter at max80.sdc(30): *|synchronizer:*|qreg0* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 30
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+Warning (332049): Ignored set_multicycle_path at max80.sdc(31): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
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+ Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
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+ -start -setup 2 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
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|
+Warning (332049): Ignored set_multicycle_path at max80.sdc(33): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
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|
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+ Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
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|
+ -start -hold -1 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
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+Warning (332174): Ignored filter at max80.sdc(37): sld_signaltap:* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
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+Warning (332049): Ignored set_false_path at max80.sdc(37): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
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+ Info (332050): set_false_path -to [get_registers sld_signaltap:*] File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
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|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
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-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
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|
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
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|
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+Info (332111): Found 8 clocks
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|
+ Info (332111): Period Clock Name
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+ Info (332111): ======== ============
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+ Info (332111): 20.834 clock_48
|
|
|
+ Info (332111): 5.555 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]
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+ Info (332111): 27.778 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]
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+ Info (332111): 10.417 pll|altpll_component|auto_generated|pll1|clk[0]
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+ Info (332111): 10.417 pll|altpll_component|auto_generated|pll1|clk[1]
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+ Info (332111): 27.778 pll|altpll_component|auto_generated|pll1|clk[2]
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|
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+ Info (332111): 10.417 rst_n
|
|
|
+ Info (332111): 30517.579 rtc_32khz
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|
Info (176353): Automatically promoted node hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock (placed in counter C0 of PLL_1) File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 891
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Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
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Info (176353): Automatically promoted node hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] (placed in counter C1 of PLL_1) File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 891
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|
@@ -1823,6 +1870,10 @@ Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_a
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Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
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|
Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C1 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
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|
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
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|
+Info (176353): Automatically promoted node rst_n File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 110
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|
+ Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
|
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|
+ Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
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|
+ Info (176357): Destination node rst_ctr[0]~12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 137
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|
|
Info (176233): Starting register packing
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|
|
Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
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|
Info (176235): Finished register packing
|
|
|
@@ -1846,7 +1897,7 @@ Warning (15705): Ignored locations or region assignments to the following nodes
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Warning (15706): Node "xabc_op[2]" is assigned to location or region, but does not exist in design
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Warning (15706): Node "xabc_xio_n" is assigned to location or region, but does not exist in design
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|
Warning (15706): Node "xabc_xm_n" is assigned to location or region, but does not exist in design
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-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
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+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
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Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
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|
Info (170189): Fitter placement preparation operations beginning
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Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
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|
@@ -1855,12 +1906,12 @@ Info (170137): Fitter placement was successful
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Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
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Info (170193): Fitter routing operations beginning
|
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Info (170195): Router estimated average interconnect usage is 0% of the available device resources
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- Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X10_Y20 to location X20_Y29
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+ Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
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Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
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Info (170201): Optimizations that may affect the design's routability were skipped
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Info (170200): Optimizations that may affect the design's timing were skipped
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Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
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-Info (11888): Total time spent on timing analysis during the Fitter is 0.17 seconds.
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+Info (11888): Total time spent on timing analysis during the Fitter is 0.12 seconds.
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Info (334003): Started post-fitting delay annotation
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Info (334004): Delay annotation completed successfully
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Info (334003): Started post-fitting delay annotation
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@@ -2000,10 +2051,10 @@ Warning (169064): Following 45 pins have no output enable or a GND or VCC output
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Info (169065): Pin hdmi_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
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Info (169065): Pin hdmi_hpd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 101
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Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
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-Info: Quartus Prime Fitter was successful. 0 errors, 35 warnings
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- Info: Peak virtual memory: 1345 megabytes
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- Info: Processing ended: Wed Jul 28 12:56:07 2021
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- Info: Elapsed time: 00:00:08
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+Info: Quartus Prime Fitter was successful. 0 errors, 39 warnings
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+ Info: Peak virtual memory: 1333 megabytes
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+ Info: Processing ended: Thu Jul 29 01:11:26 2021
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+ Info: Elapsed time: 00:00:09
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Info: Total CPU time (on all processors): 00:00:09
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H. Peter Anvin