usb: use showahead on the Rx FIFO, but not the Tx FIFO

The CPU moves ahead before the Rx FIFO has advanced the data, so use a
showahead Rx FIFO and advance the data after the read cycle.

However, the Tx FIFO does not want to work this way.

PUN80 networking works now (on ACM1).

Make the liveness spinner a bit less obnoxious.

fpga/ip/cdc_fifo.qip → fpga/ip/cdc_rxfifo.qip

@@ -1,6 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "FIFO"
 set_global_assignment -name IP_TOOL_VERSION "21.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cdc_fifo.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cdc_fifo_inst.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cdc_fifo_bb.v"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cdc_rxfifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cdc_rxfifo_bb.v"]

fpga/ip/cdc_rxfifo.v

@@ -0,0 +1,204 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: cdc_rxfifo.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module cdc_rxfifo (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdfull,
+	rdusedw,
+	wrempty,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[7:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[7:0]  q;
+	output	  rdempty;
+	output	  rdfull;
+	output	[9:0]  rdusedw;
+	output	  wrempty;
+	output	  wrfull;
+	output	[9:0]  wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire  sub_wire1;
+	wire  sub_wire2;
+	wire [9:0] sub_wire3;
+	wire  sub_wire4;
+	wire  sub_wire5;
+	wire [9:0] sub_wire6;
+	wire [7:0] q = sub_wire0[7:0];
+	wire  rdempty = sub_wire1;
+	wire  rdfull = sub_wire2;
+	wire [9:0] rdusedw = sub_wire3[9:0];
+	wire  wrempty = sub_wire4;
+	wire  wrfull = sub_wire5;
+	wire [9:0] wrusedw = sub_wire6[9:0];
+
+	dcfifo	dcfifo_component (
+				.aclr (aclr),
+				.data (data),
+				.rdclk (rdclk),
+				.rdreq (rdreq),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.q (sub_wire0),
+				.rdempty (sub_wire1),
+				.rdfull (sub_wire2),
+				.rdusedw (sub_wire3),
+				.wrempty (sub_wire4),
+				.wrfull (sub_wire5),
+				.wrusedw (sub_wire6),
+				.eccstatus ());
+	defparam
+		dcfifo_component.intended_device_family = "Cyclone IV E",
+		dcfifo_component.lpm_numwords = 1024,
+		dcfifo_component.lpm_showahead = "ON",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 8,
+		dcfifo_component.lpm_widthu = 10,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.rdsync_delaypipe = 5,
+		dcfifo_component.read_aclr_synch = "OFF",
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON",
+		dcfifo_component.write_aclr_synch = "ON",
+		dcfifo_component.wrsync_delaypipe = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "8"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo_bb.v TRUE

fpga/ip/cdc_txfifo.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cdc_txfifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cdc_txfifo_bb.v"]

fpga/ip/cdc_fifo.v → fpga/ip/cdc_txfifo.v

@@ -4,12 +4,12 @@
 // MODULE: dcfifo 
 
 // ============================================================
-// File Name: cdc_fifo.v
+// File Name: cdc_txfifo.v
 // Megafunction Name(s):
 // 			dcfifo
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@@ -37,7 +37,7 @@
 // synopsys translate_off
 `timescale 1 ps / 1 ps
 // synopsys translate_on
-module cdc_fifo (
+module cdc_txfifo (
 	aclr,
 	data,
 	rdclk,
@@ -115,7 +115,7 @@ module cdc_fifo (
 		dcfifo_component.read_aclr_synch = "ON",
 		dcfifo_component.underflow_checking = "ON",
 		dcfifo_component.use_eab = "ON",
-		dcfifo_component.write_aclr_synch = "ON",
+		dcfifo_component.write_aclr_synch = "OFF",
 		dcfifo_component.wrsync_delaypipe = 5;
 
 
@@ -168,7 +168,7 @@ endmodule
 // Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
 // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
 // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
@@ -196,10 +196,9 @@ endmodule
 // Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
 // Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo_inst.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo_bb.v TRUE

fpga/max80.qpf

@@ -19,14 +19,14 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 17:34:30  January 18, 2022
+# Date created = 00:01:58  January 19, 2022
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "17:34:30  January 18, 2022"
+DATE = "00:01:58  January 19, 2022"
 
 # Revisions
 
-PROJECT_REVISION = "v2"
 PROJECT_REVISION = "v1"
+PROJECT_REVISION = "v2"

fpga/max80.qsf

@@ -290,7 +290,9 @@ set_global_assignment -name SYSTEMVERILOG_FILE v2.sv
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name VERILOG_FILE ip/fifo.v
 set_global_assignment -name VERILOG_FILE ip/ddufifo.v
-set_global_assignment -name VERILOG_FILE ip/cdc_fifo.v
-set_global_assignment -name QIP_FILE ip/cdc_fifo.qip
+set_global_assignment -name VERILOG_FILE ip/cdc_txfifo.v
+set_global_assignment -name VERILOG_FILE ip/cdc_rxfifo.v
+set_global_assignment -name QIP_FILE ip/cdc_txfifo.qip
+set_global_assignment -name QIP_FILE ip/cdc_rxfifo.qip
 
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/usb/usb_serial/src_v/usb_cdc_core.sv

@@ -119,18 +119,20 @@ module usb_cdc_channel
    always @(posedge sys_clk)
      begin
 	fifo_access_q <= fifo_access;
-	fifo_read_q   <= fifo_access & ~cpu_wstrb[0];
+	fifo_read_q   <= fifo_access & ~|cpu_wstrb;
      end
 
    wire		        txempty;
    wire		        txfull;
-   wire [fifo_bits-1:0] txused;
-   wire [water_bits:0]	txused_msb = txused[fifo_bits-1:fifo_bits-water_bits];
+   wire [fifo_bits-1:0]  txused;
+   wire [water_bits-1:0] txused_msb = txused[fifo_bits-1:fifo_bits-water_bits];
    wire		        inport_empty_w;
    reg			inport_valid_q;
    reg			flush_tx_data;
 
-   cdc_fifo txfifo (
+   // cdc_txfifo does not have lookahead data output,
+   // aclr assumed synchronous with wrclk
+   cdc_txfifo txfifo (
 		    .aclr    ( flush_tx_data ),
 
 		    .wrclk   ( sys_clk ),
@@ -184,7 +186,7 @@ module usb_cdc_channel
    wire		        rxfull;
    reg			flush_rx_data;
    wire [fifo_bits-1:0] rxused;
-   wire [water_bits:0]	rxused_msb = rxused[fifo_bits-1:fifo_bits-water_bits];
+   wire [water_bits-1:0] rxused_msb = rxused[fifo_bits-1:fifo_bits-water_bits];
    wire [fifo_bits-1:0] outport_used_w;
    wire			outport_full_w;
 
@@ -194,12 +196,14 @@ module usb_cdc_channel
    assign data_ep.d.rx_space = ~outport_full_w &
 			       (outport_used_w < fifo_size - packet_size);
 
-   cdc_fifo rxfifo (
+   // cdc_rxfifo has lookahead data output, aclr assumed synchronous with
+   // rdclk
+   cdc_rxfifo rxfifo (
 		    .aclr    ( flush_rx_data ),
 
 		    .rdclk   ( sys_clk ),
 		    .q       ( rdata_fifo ),
-		    .rdreq   ( fifo_access & ~fifo_access_q & ~|cpu_wstrb ),
+		    .rdreq   ( ~fifo_access & fifo_read_q ),
 		    .rdempty ( rxempty ),
 		    .rdfull  ( rxfull ),
 		    .rdusedw ( rxused ),
@@ -217,10 +221,10 @@ module usb_cdc_channel
 
    always @(posedge sys_clk)
      begin
-	if (start_of_frame_s)
-	  had_rxdata <= { had_rxdata[0], 1'b1 };
 	if (rxempty)
 	  had_rxdata <= 2'b00;
+	else if (start_of_frame_s)
+	  had_rxdata <= { had_rxdata[0], 1'b1 };
      end
 
    wire [15:0] status_mask = 16'b0001_1111_1111_1111; // Implemented bit mask
@@ -754,7 +758,7 @@ module usb_cdc_core
 	.utmi_linestate_i(utmi_linestate_i),
 
 	.reg_chirp_en_i(utmi_chirp_en_w),
-	.reg_int_en_sof_i(1'b0),
+	.reg_int_en_sof_i(1'b1),
 
 	.reg_dev_addr_i(device_addr_q),
 

rv32/system.c

@@ -71,9 +71,11 @@ IRQHANDLER(sysclock,0)
     count++;
     timer_irq_count = count;
     if ( MINITESTS ) {
+	static const char spinner[4] = "/-\\|";
 	if (!(count & (TIMER_HZ-1))) {
 	    uint32_t seconds = count >> TIMER_SHIFT;
-	    CON_DATA = (seconds & 63) + '0'; /* Liveness... */
+	    CON_DATA = spinner[seconds & 3];
+	    CON_DATA = '\b';
 	}
     }
 }