sdram: fix op_cycle counter overflow

A burst write cycle takes 24 cycles, and st_init takes 22, so op_cycle
would overflow for those operations. Fix.

Ideally the width of this counter should be explicitly computed.

output_files/max80.map

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0xF75F29AE
+- Data checksum for this conversion is 0xF75F281E
 
 - All the addresses in this file are byte addresses
 

sdram.sv

@@ -196,7 +196,9 @@ module sdram (
    // State machine and counters
    reg [t_ref:0]	    rfsh_ctr;  // Refresh timer
    reg [t_p:t_ref]	    init_ctr;  // Reset to init counter
-   reg [burst:0]	    op_cycle;  // Cycles into the current operation
+
+   // XXX: compute the necessary width of this field elsewhere
+   reg [4:0]	            op_cycle;	// Cycles into the current operation
 
    // The actual values are unimportant; the compiler will optimize
    // the state machine implementation for us.