fpga: set HDMI pixel clock to 56 MHz; correct PLL and HDMITX settings

fpga/ip/hdmitx.v

@@ -80,14 +80,14 @@ module hdmitx (
 		ALTLVDS_TX_component.center_align_msb = "UNUSED",
 		ALTLVDS_TX_component.common_rx_tx_pll = "ON",
 		ALTLVDS_TX_component.coreclock_divide_by = 2,
-		ALTLVDS_TX_component.data_rate = "336.0 Mbps",
+		ALTLVDS_TX_component.data_rate = "560.0 Mbps",
 		ALTLVDS_TX_component.deserialization_factor = 10,
 		ALTLVDS_TX_component.differential_drive = 0,
 		ALTLVDS_TX_component.enable_clock_pin_mode = "UNUSED",
 		ALTLVDS_TX_component.implement_in_les = "ON",
 		ALTLVDS_TX_component.inclock_boost = 0,
 		ALTLVDS_TX_component.inclock_data_alignment = "EDGE_ALIGNED",
-		ALTLVDS_TX_component.inclock_period = 14881,
+		ALTLVDS_TX_component.inclock_period = 17857,
 		ALTLVDS_TX_component.inclock_phase_shift = 0,
 		ALTLVDS_TX_component.intended_device_family = "Cyclone IV E",
 		ALTLVDS_TX_component.lpm_hint = "CBX_MODULE_PREFIX=hdmitx",
@@ -100,7 +100,7 @@ module hdmitx (
 		ALTLVDS_TX_component.outclock_multiply_by = 2,
 		ALTLVDS_TX_component.outclock_phase_shift = 0,
 		ALTLVDS_TX_component.outclock_resource = "AUTO",
-		ALTLVDS_TX_component.output_data_rate = 336,
+		ALTLVDS_TX_component.output_data_rate = 560,
 		ALTLVDS_TX_component.pll_compensation_mode = "AUTO",
 		ALTLVDS_TX_component.pll_self_reset_on_loss_lock = "ON",
 		ALTLVDS_TX_component.preemphasis_setting = 0,
@@ -121,15 +121,15 @@ endmodule
 // Retrieval info: PRIVATE: CNX_CLOCK_CHOICES STRING "tx_coreclock"
 // Retrieval info: PRIVATE: CNX_CLOCK_MODE NUMERIC "0"
 // Retrieval info: PRIVATE: CNX_COMMON_PLL NUMERIC "1"
-// Retrieval info: PRIVATE: CNX_DATA_RATE STRING "336.0"
+// Retrieval info: PRIVATE: CNX_DATA_RATE STRING "560.0"
 // Retrieval info: PRIVATE: CNX_DESER_FACTOR NUMERIC "10"
 // Retrieval info: PRIVATE: CNX_EXT_PLL STRING "OFF"
 // Retrieval info: PRIVATE: CNX_LE_SERDES STRING "ON"
 // Retrieval info: PRIVATE: CNX_NUM_CHANNEL NUMERIC "3"
 // Retrieval info: PRIVATE: CNX_OUTCLOCK_DIVIDE_BY NUMERIC "10"
 // Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "1"
-// Retrieval info: PRIVATE: CNX_PLL_FREQ STRING "67.20"
-// Retrieval info: PRIVATE: CNX_PLL_PERIOD STRING "14.881"
+// Retrieval info: PRIVATE: CNX_PLL_FREQ STRING "56.00"
+// Retrieval info: PRIVATE: CNX_PLL_PERIOD STRING "17.857"
 // Retrieval info: PRIVATE: CNX_REG_INOUT NUMERIC "1"
 // Retrieval info: PRIVATE: CNX_TX_CORECLOCK STRING "ON"
 // Retrieval info: PRIVATE: CNX_TX_LOCKED STRING "ON"
@@ -145,14 +145,14 @@ endmodule
 // Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
 // Retrieval info: CONSTANT: CORECLOCK_DIVIDE_BY NUMERIC "2"
 // Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
-// Retrieval info: CONSTANT: DATA_RATE STRING "336.0 Mbps"
+// Retrieval info: CONSTANT: DATA_RATE STRING "560.0 Mbps"
 // Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
 // Retrieval info: CONSTANT: DIFFERENTIAL_DRIVE NUMERIC "0"
 // Retrieval info: CONSTANT: ENABLE_CLOCK_PIN_MODE STRING "UNUSED"
 // Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "ON"
 // Retrieval info: CONSTANT: INCLOCK_BOOST NUMERIC "0"
 // Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "EDGE_ALIGNED"
-// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "14881"
+// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "17857"
 // Retrieval info: CONSTANT: INCLOCK_PHASE_SHIFT NUMERIC "0"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
@@ -165,7 +165,7 @@ endmodule
 // Retrieval info: CONSTANT: OUTCLOCK_MULTIPLY_BY NUMERIC "2"
 // Retrieval info: CONSTANT: OUTCLOCK_PHASE_SHIFT NUMERIC "0"
 // Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
-// Retrieval info: CONSTANT: OUTPUT_DATA_RATE NUMERIC "336"
+// Retrieval info: CONSTANT: OUTPUT_DATA_RATE NUMERIC "560"
 // Retrieval info: CONSTANT: PLL_COMPENSATION_MODE STRING "AUTO"
 // Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "ON"
 // Retrieval info: CONSTANT: PREEMPHASIS_SETTING NUMERIC "0"

fpga/ip/pll.v

@@ -143,7 +143,7 @@ module pll (
 		altpll_component.clk1_duty_cycle = 50,
 		altpll_component.clk1_multiply_by = 7,
 		altpll_component.clk1_phase_shift = "0",
-		altpll_component.clk2_divide_by = 5,
+		altpll_component.clk2_divide_by = 6,
 		altpll_component.clk2_duty_cycle = 50,
 		altpll_component.clk2_multiply_by = 7,
 		altpll_component.clk2_phase_shift = "0",
@@ -232,7 +232,7 @@ endmodule
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "6"
 // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "5"
 // Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "2"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
@@ -242,7 +242,7 @@ endmodule
 // Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "168.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "84.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "67.199997"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "56.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "134.399994"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "168.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
@@ -279,13 +279,13 @@ endmodule
 // Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "14"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "7"
 // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "14"
 // Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "7"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "168.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "84.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "60.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "56.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "168.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
@@ -362,7 +362,7 @@ endmodule
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "6"
 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "7"
 // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"

fpga/max80.sv

@@ -133,7 +133,7 @@ module max80 (
 	    .inclk0 ( clock_48 ),
 	    .c0 ( sdram_out_clk ),	// SDRAM external clock (168 MHz)
 	    .c1 ( sys_clk ),		// System clock (84 MHz)
-	    .c2 ( vid_clk ),		// Video pixel clock (48 MHz)
+	    .c2 ( vid_clk ),		// Video pixel clock (56 MHz)
 	    .c3 ( flash_clk ),		// Serial flash ROM clock (134 MHz)
 	    .c4 ( sdram_clk ),		// SDRAM internal clock (168 MHz)
 	    .locked ( pll_locked[0] ),

fpga/video.sv

@@ -14,9 +14,23 @@ module video (
    assign hdmi_sda = 1'bz;
    assign hdmi_hpd = 1'bz;
 
-   // 1024x768x60 with a 67.2 MHz pixel clock
-   // Htiming: 1024 128 112 140  = 1404
-   // Vtiming:  768   3   4  23  =  798
+   //
+   // 1024x768x60 with a 56 MHz pixel clock
+   //
+   // Htiming: 1024 48 32 80 = 1184 = 47.297 kHz
+   // Vtiming:  768  4  4 12 =  788 = 60.022 Hz
+   //
+
+   localparam [10:0] xact   = 11'd1024;
+   localparam [10:0] xback  = 11'd48;
+   localparam [10:0] xsync  = 11'd32;
+   localparam [10:0] xfront = 11'd80;
+
+   localparam [ 9:0] yact   = 10'd768;
+   localparam [ 9:0] yback  = 10'd4;
+   localparam [ 9:0] ysync  = 10'd4;
+   localparam [ 9:0] yfront = 10'd12;
+
    reg [10:0]	    x;
    reg [ 9:0]	    y;
 
@@ -51,19 +65,20 @@ module video (
 	  b <= pixbar & {8{x[7]}};
 
 	  x <= x + 1'b1;
-	  if (x >= 11'd1403)
+	  if (x >= (xact+xback+xsync+xfront-1'b1))
 	    begin
 	       x <= 11'd0;
 	       y <= y + 1'b1;
-	       if (y >= 10'd797)
+	       if (y >= (yact+yback+ysync+yfront-1'b1))
 		 y <= 10'd0;
 	    end
 
-	  hblank <= x[10];
-	  vblank <= &y[9:8];
+	  hblank <= x >= xact;
+	  vblank <= y >= yact;
+
+	  hsync  <= (x >= (xact+xback) && x < (xact+xback+xsync));
+	  vsync  <= (y >= (yact+yback) && y < (yact+yback+ysync));
 
-	  hsync  <= (x >= 11'd1152 && x < 11'd1264);
-	  vsync  <= (y >= 10'd771 && y < 10'd775);
        end // else: !if(~rst_n)
 
    wire [7:0] hdmi_data[0:2];