fpga: parameterize the rtc_32khz workaround

Make the rtc_32khz clock workaround a module parameter to make it
easily changeable; resulting .sdc changes.

More conservative thermal model settings.

fpga/max80.qsf

@@ -64,8 +64,8 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name VCCA_USER_VOLTAGE 2.5V
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
 set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
@@ -243,4 +243,9 @@ set_global_assignment -name SOURCE_FILE max80.pins
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name VERILOG_FILE ip/fifo.v
 set_global_assignment -name VERILOG_FILE ip/ddufifo.v
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS ON
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
+set_global_assignment -name POWER_USE_TA_VALUE 35
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/max80.sdc

@@ -2,16 +2,17 @@
 
 # Clock constraints
 
-# Note: round up
+# Input master clock for all PLLs
 create_clock -name "clock_48" -period 20.834ns [get_ports {clock_48}]
-
-# rtc_32khz is technically a clock, but it is treated as an input signal
-# generating strobes - Quartus gets confused about a clock that slow
-# create_clock -name "rtc_32khz" -period 30517.579ns [get_ports {rtc_32khz}]
-
-# Automatically constrain PLL and other generated clocks
 derive_pll_clocks
 
+# Handle both the RTC input clock and the internal workaround
+# The internal workaround clock should still be treated an asynchronous
+create_clock -name "rtc_32khz" -period 30517.578ns [get_ports {rtc_32khz}]
+create_clock -name "ctr_32khz" -period 30517.578ns [get_registers {ctr_32khz}]
+set_clock_groups -asynchronous -group {rtc_32khz}
+set_clock_groups -asynchronous -group {ctr_32khz}
+
 # Automatically calculate clock uncertainty to jitter and other effects.
 derive_clock_uncertainty
 

fpga/max80.sv

@@ -8,7 +8,11 @@
 // Sharing JTAG pins (via JTAGEN)
 `undef SHARED_JTAG
 
-module max80 (
+module max80
+#(
+  // Pull-up installed on RTC 32 kHz line
+  parameter rtc_32khz_rework = 1'b0
+) (
 	      // Clock oscillator
 	      input	    clock_48, // 48 MHz
 
@@ -768,13 +772,14 @@ module max80 (
 
    // System local clock (not an RTC, but settable from one)
    // Also provides a periodic interrupt (set to 32 Hz)
+   //
    // XXX: the RTC 32 kHz signal is missing a pull-up,
-   // so it will require board rework. For now, use an
+   // so unless the board has been reworked, use a
    // divider down from the 84 MHz system clock. The
    // error is about 200 ppm; a proper NCO could do better.
 
-   reg [10:0]  ctr_64khz;
-   reg	       ctr_32khz;
+   reg		ctr_32khz;
+   reg [10:0]	ctr_64khz;
    always @(posedge sys_clk)
      begin
 	if (~|ctr_64khz)
@@ -786,11 +791,14 @@ module max80 (
 	  ctr_64khz <= ctr_64khz - 1'b1;
      end
 
+   // 32kHz clock synchronized with sys_clk
+   wire clk_32kHz = rtc_32khz_rework ? rtc_32khz : ctr_32khz;
+
    sysclock #(.PERIODIC_HZ_LG2 ( 5 ))
    sysclock (
 		      .rst_n ( rst_n ),
 		      .sys_clk ( sys_clk ),
-		      .rtc_clk ( ctr_32khz ),
+		      .rtc_clk ( clk_32kHz ),
 
 		      .wdata   ( cpu_mem_wdata ),
 		      .rdata   ( iodev_rdata_sysclock ),
@@ -836,7 +844,7 @@ module max80 (
 `else // !`ifdef REALLY_ESP32
    reg [5:-13] esp_ctr;		// 32768 * 2^-13 = 4 Hz
 
-   always @(posedge ctr_32khz)
+   always @(posedge clk_32kHz)
      esp_ctr <= esp_ctr + 1'b1;
 
    assign spi_clk        = esp_ctr[0];