tty: don't require DTR#; v2: output some clocks on gpio[135]

- Don't require DTR# to be asserted for serial output; this makes v2
  debugging easier.

- For v2 debugging, output:

  gpio[1]: 84 MHz
  gpio[3]: 48 MHz
  gpio[5]:  4 Hz

fpga/clkbuf.sv

@@ -0,0 +1,35 @@
+//
+// clkbuf.sv
+//
+// Clock output using a DDIO output buffer; can optionally be
+// overridden to not use DDIO e.g. for temporary testing.
+//
+
+module clk_buf
+  #(
+    parameter bit invert = 1'b0,
+    parameter bit noddio = 1'b0
+    )
+   (
+    input  clk,
+    output pin
+    );
+
+   generate
+      if ( noddio )
+	begin
+	   assign pin = clk ^ invert;
+	end
+      else
+	begin
+	   ddio_out ddiobuf (
+			     .aclr     ( 1'b0 ),
+			     .datain_h ( ~invert ),
+			     .datain_l (  invert ),
+			     .outclock ( clk ),
+			     .dataout  ( ddio_pin )
+			     );
+	end // else: !if( noddio )
+   endgenerate
+
+endmodule // clk_buf

fpga/max80.qpf

@@ -19,14 +19,14 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 05:39:58  December 27, 2021
+# Date created = 14:03:58  December 29, 2021
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "05:39:58  December 27, 2021"
+DATE = "14:03:58  December 29, 2021"
 
 # Revisions
 
-PROJECT_REVISION = "v1"
 PROJECT_REVISION = "v2"
+PROJECT_REVISION = "v1"

fpga/max80.qsf

@@ -275,6 +275,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
 set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv
 set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
 set_global_assignment -name SYSTEMVERILOG_FILE spirom.sv
+set_global_assignment -name SYSTEMVERILOG_FILE clkbuf.sv
 set_global_assignment -name VERILOG_FILE ip/ddio_out.v
 set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
 set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl

fpga/max80.sv

@@ -13,115 +13,123 @@ module max80
     parameter logic [7:0] fpga_ver)
    (
     // Clock oscillator
-    input	  master_clk,		// 336 MHz from PLL2
-    input	  master_pll_locked,	// PLL2 is locked, master_clk is good
-    output	  reset_plls,		// Reset all PLLs including PLL2
+    input 	  master_clk, // 336 MHz from PLL2
+    input 	  master_pll_locked, // PLL2 is locked, master_clk is good
+    output 	  reset_plls, // Reset all PLLs including PLL2
 
-    input	  board_id, // This better match the firmware
+    input 	  board_id, // This better match the firmware
 
     // ABC-bus
-    inout	  abc_clk, // ABC-bus 3 MHz clock
+    inout 	  abc_clk, // ABC-bus 3 MHz clock
     inout [15:0]  abc_a, // ABC address bus
     inout [7:0]   abc_d, // ABC data bus
-    output	  abc_d_oe, // Data bus output enable
-    inout	  abc_rst_n, // ABC bus reset strobe
-    inout	  abc_cs_n, // ABC card select strobe
+    output 	  abc_d_oe, // Data bus output enable
+    inout 	  abc_rst_n, // ABC bus reset strobe
+    inout 	  abc_cs_n, // ABC card select strobe
     inout [4:0]   abc_out_n, // OUT, C1-C4 strobe
     inout [1:0]   abc_inp_n, // INP, STATUS strobe
-    inout	  abc_xmemfl_n, // Memory read strobe
-    inout	  abc_xmemw800_n, // Memory write strobe (ABC800)
-    inout	  abc_xmemw80_n, // Memory write strobe (ABC80)
-    inout	  abc_xinpstb_n, // I/O read strobe (ABC800)
-    inout	  abc_xoutpstb_n, // I/O write strobe (ABC80)
+    inout 	  abc_xmemfl_n, // Memory read strobe
+    inout 	  abc_xmemw800_n, // Memory write strobe (ABC800)
+    inout 	  abc_xmemw80_n, // Memory write strobe (ABC80)
+    inout 	  abc_xinpstb_n, // I/O read strobe (ABC800)
+    inout 	  abc_xoutpstb_n, // I/O write strobe (ABC80)
     // The following are inverted versus the bus IF
     // the corresponding MOSFETs are installed
-    inout	  abc_rdy_x, // RDY = WAIT#
-    inout	  abc_resin_x, // System reset request
-    inout	  abc_int80_x, // System INT request (ABC80)
-    inout	  abc_int800_x, // System INT request (ABC800)
-    inout	  abc_nmi_x, // System NMI request (ABC800)
-    inout	  abc_xm_x, // System memory override (ABC800)
+    inout 	  abc_rdy_x, // RDY = WAIT#
+    inout 	  abc_resin_x, // System reset request
+    inout 	  abc_int80_x, // System INT request (ABC80)
+    inout 	  abc_int800_x, // System INT request (ABC800)
+    inout 	  abc_nmi_x, // System NMI request (ABC800)
+    inout 	  abc_xm_x, // System memory override (ABC800)
     // Host/device control
-    output	  abc_host, // 1 = host, 0 = target
+    output 	  abc_host, // 1 = host, 0 = target
 
     // ABC-bus extension header
     // (Note: cannot use an array here because HC and HH are
     // input only.)
-    inout	  exth_ha,
-    inout	  exth_hb,
-    input	  exth_hc,
-    inout	  exth_hd,
-    inout	  exth_he,
-    inout	  exth_hf,
-    inout	  exth_hg,
-    input	  exth_hh,
+    inout 	  exth_ha,
+    inout 	  exth_hb,
+    input 	  exth_hc,
+    inout 	  exth_hd,
+    inout 	  exth_he,
+    inout 	  exth_hf,
+    inout 	  exth_hg,
+    input 	  exth_hh,
 
     // SDRAM bus
-    output	  sr_clk,
+    output 	  sr_clk,
     output [1:0]  sr_ba, // Bank address
     output [12:0] sr_a, // Address within bank
     inout [15:0]  sr_dq, // Also known as D or IO
     output [1:0]  sr_dqm, // DQML and DQMH
-    output	  sr_cs_n,
-    output	  sr_we_n,
-    output	  sr_cas_n,
-    output	  sr_ras_n,
+    output 	  sr_cs_n,
+    output 	  sr_we_n,
+    output 	  sr_cas_n,
+    output 	  sr_ras_n,
 
     // SD card
-    input	  sd_cd_n,
-    output	  sd_cs_n,
-    output	  sd_clk,
-    output	  sd_di,
-    input	  sd_do,
+    input 	  sd_cd_n,
+    output 	  sd_cs_n,
+    output 	  sd_clk,
+    output 	  sd_di,
+    input 	  sd_do,
 
     // Serial console (naming is FPGA as DCE)
-    input	  tty_txd,
-    output	  tty_rxd,
-    input	  tty_rts,
-    output	  tty_cts,
-    input	  tty_dtr,
+    input 	  tty_txd,
+    output 	  tty_rxd,
+    input 	  tty_rts,
+    output 	  tty_cts,
+    input 	  tty_dtr,
 
     // SPI flash memory (also configuration)
-    output	  flash_cs_n,
-    output	  flash_sck,
+    output 	  flash_cs_n,
+    output 	  flash_sck,
     inout [1:0]   flash_io,
 
     // SPI bus (connected to ESP32 so can be bidirectional)
-    inout	  spi_clk,
-    inout	  spi_miso,
-    inout	  spi_mosi,
-    inout	  spi_cs_esp_n, // ESP32 IO10
-    inout	  spi_cs_flash_n, // ESP32 IO01
+    inout 	  spi_clk,
+    inout 	  spi_miso,
+    inout 	  spi_mosi,
+    inout 	  spi_cs_esp_n, // ESP32 IO10
+    inout 	  spi_cs_flash_n, // ESP32 IO01
 
     // Other ESP32 connections
-    inout	  esp_io0, // ESP32 IO00
-    inout	  esp_int, // ESP32 IO09
+    inout 	  esp_io0, // ESP32 IO00
+    inout 	  esp_int, // ESP32 IO09
 
     // I2C bus (RTC and external)
-    inout	  i2c_scl,
-    inout	  i2c_sda,
-    input	  rtc_32khz,
-    input	  rtc_int_n,
+    inout 	  i2c_scl,
+    inout 	  i2c_sda,
+    input 	  rtc_32khz,
+    input 	  rtc_int_n,
 
     // LED (2 = D23/G, 1 = D22/R, 0 = D17/B)
     output [2:0]  led,
 
     // USB
-    inout	  usb_dp,
-    inout	  usb_dn,
-    output	  usb_pu,
-    input	  usb_rx,
-    input	  usb_rx_ok,
+    inout 	  usb_dp,
+    inout 	  usb_dn,
+    output 	  usb_pu,
+    input 	  usb_rx,
+    input 	  usb_rx_ok,
 
     // HDMI
     output [2:0]  hdmi_d,
-    output	  hdmi_clk,
-    inout	  hdmi_scl,
-    inout	  hdmi_sda,
-    inout	  hdmi_hpd,
+    output 	  hdmi_clk,
+    inout 	  hdmi_scl,
+    inout 	  hdmi_sda,
+    inout 	  hdmi_hpd,
 
     // Unconnected pins with pullups, used for randomness
-    inout [2:0]   rngio
+    inout [2:0]   rngio,
+
+    // Various clocks available to the top level as well as internally
+    output 	  sdram_clk,	// 168 MHz SDRAM clock
+    output 	  sys_clk,	//  84 MHz System clock
+    output 	  flash_clk,	// 134 MHz Serial flash ROM clock
+    output 	  usb_clk,	//  48 MHz USB clock
+    output 	  vid_clk,	//  56 MHz Video pixel clock
+    output 	  vid_hdmiclk	// 280 MHz HDMI serializer clock = vid_clk x 5
     );
 
    // -----------------------------------------------------------------------
@@ -155,10 +163,6 @@ module max80
    //  vid_hdmiclk, vid_clk  - 5:1 ratio
    //
 
-   wire	    sdram_clk;		// 168 MHz SDRAM clock
-   wire	    sys_clk;		//  84 MHz System clock
-   wire     flash_clk;		// 134 MHz Serial flash ROM clock
-   wire     usb_clk;		//  48 MHz USB clock
    pll3 pll3 (
 	      .areset ( ~pll_locked[2] ),
 	      .locked ( pll_locked[3] ),
@@ -171,8 +175,6 @@ module max80
 	      .c4     ( usb_clk )
 	      );
 
-   wire	    vid_clk;		//  56 MHz Video pixel clock
-   wire	    vid_hdmiclk;	// 280 MHz HDMI serializer clock = vid_clk x 5
    pll4 pll4 (
 	      .areset ( ~pll_locked[2] ),
 	      .locked ( pll_locked[4] ),
@@ -697,7 +699,7 @@ module max80
    wire        tty_rts_in;	// RTS# received from outside
 
    assign tty_data_in      = tty_txd;
-   assign tty_rxd          = ~tty_dtr ? tty_data_out : 1'bz;
+   assign tty_rxd          = tty_data_out;
    assign tty_rts_in       = ~tty_rts;
    assign tty_cts          = ~tty_cts_out;
 

fpga/v2.sv

@@ -116,11 +116,6 @@ module v2
    // gpio[2] - RxD
    // gpio[4] - DTR#
 
-   // Permanently unused
-   assign gpio[1] = 1'bz;
-   assign gpio[3] = 1'bz;
-   assign gpio[5] = 1'bz;
-
    // Master PLL: 16 -> 336 MHz
    wire		  reset_plls;
    wire		  master_pll_locked;
@@ -133,6 +128,8 @@ module v2
 		 .c0 ( master_clk )
 		 );
 
+   wire		  usb_clk;
+   wire		  sys_clk;
 
    max80 #(.x_mosfet(6'b000000),
 	   .fpga_ver(8'd2))
@@ -213,7 +210,33 @@ module v2
 	  .hdmi_scl               ( hdmi_scl ),
 	  .hdmi_sda               ( hdmi_sda ),
 	  .hdmi_hpd               ( hdmi_hpd ),
-	  .rngio                  ( rngio )
+	  .rngio                  ( rngio ),
+
+	  .sys_clk		  ( sys_clk ),
+	  .usb_clk		  ( usb_clk )
 	  );
 
+   // sys_clk and usb_clk to GPIO
+   clk_buf sys_clk_buf ( .clk ( sys_clk ), .pin ( gpio[1] ) );
+   clk_buf usb_clk_buf ( .clk ( usb_clk ), .pin ( gpio[3] ) );
+
+   // 4 Hz test signal on gpio[5], derived from sys_clk (84 MHz)
+   reg [23:0]	  ctr_8hz;
+   reg		  test_4hz;
+
+   always @(posedge sys_clk)
+     begin
+	if (ctr_8hz >= 24'd10_500_000)
+	  begin
+	     ctr_8hz <= 24'd1;
+	     test_4hz <= ~test_4hz;
+	  end
+	else
+	  begin
+	     ctr_8hz <= ctr_8hz + 1'b1;
+	  end
+     end // always @ (posedge sys_clk)
+
+   assign gpio[5] = test_4hz;
+
 endmodule // v2