Switch PLL to high bandwidth

ip/pll.v

@@ -126,7 +126,7 @@ module pll (
 				.vcooverrange (),
 				.vcounderrange ());
 	defparam
-		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.bandwidth_type = "HIGH",
 		altpll_component.clk0_divide_by = 1,
 		altpll_component.clk0_duty_cycle = 50,
 		altpll_component.clk0_multiply_by = 2,
@@ -201,9 +201,9 @@ endmodule
 // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
@@ -306,7 +306,7 @@ endmodule
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"

max80.qsf

@@ -278,4 +278,8 @@ set_global_assignment -name VERILOG_FILE ip/pll.v
 set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
 set_global_assignment -name SDC_FILE max80.sdc
 set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME max80 -section_id eda_simulation
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

max80.sv

@@ -105,9 +105,9 @@ module max80 (
    parameter [6:1] mosfet_installed = 6'b000_000;
 
    // PLL and reset
-   parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles
-   reg [reset_pow2-1:0]	    rst_ctr;
-   reg 			    rst_n;   // Internal reset
+   parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles after PLL lock
+   reg [reset_pow2-1:0]     rst_ctr = 1'b0;
+   reg 			    rst_n   = 1'b0;   // Internal reset
    wire 		    pll_locked;
    wire 		    clk; // System clock
    wire 		    vid_clk;

output_files/max80.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for max80
-Thu Jul 29 09:27:00 2021
+Thu Jul 29 09:58:03 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -39,7 +39,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Jul 29 09:27:00 2021 ;
+; Assembler Status      ; Successful - Thu Jul 29 09:58:03 2021 ;
 ; Revision Name         ; max80                                 ;
 ; Top-level Entity Name ; max80                                 ;
 ; Family                ; Cyclone IV E                          ;
@@ -89,7 +89,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 09:26:58 2021
+    Info: Processing started: Thu Jul 29 09:58:02 2021
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
@@ -97,9 +97,9 @@ Info (115030): Assembler is generating device programming files
 Info (210117): Created JAM or JBC file for the specified chain: 
 Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 904 megabytes
-    Info: Processing ended: Thu Jul 29 09:27:00 2021
-    Info: Elapsed time: 00:00:02
+    Info: Peak virtual memory: 903 megabytes
+    Info: Processing ended: Thu Jul 29 09:58:03 2021
+    Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:02
 
 

output_files/max80.done

@@ -1 +1 @@
-Thu Jul 29 09:27:15 2021
+Thu Jul 29 09:58:10 2021

output_files/max80.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for max80
-Thu Jul 29 09:27:08 2021
+Thu Jul 29 09:58:10 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Jul 29 09:27:08 2021 ;
+; EDA Netlist Writer Status ; Successful - Thu Jul 29 09:58:10 2021 ;
 ; Revision Name             ; max80                                 ;
 ; Top-level Entity Name     ; max80                                 ;
 ; Family                    ; Cyclone IV E                          ;
@@ -53,11 +53,13 @@ https://fpgasoftware.intel.com/eula.
 ; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
 ; Generate functional simulation netlist                                                            ; On                        ;
 ; Truncate long hierarchy paths                                                                     ; Off                       ;
-; Map illegal HDL characters                                                                        ; Off                       ;
+; Map illegal HDL characters                                                                        ; On                        ;
 ; Flatten buses into individual nodes                                                               ; Off                       ;
 ; Maintain hierarchy                                                                                ; Off                       ;
 ; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
-; Enable glitch filtering                                                                           ; Off                       ;
+; Enable glitch filtering                                                                           ; On                        ;
+; Generate Power Estimate Scripts                                                                   ; All output signals        ;
+; Test Bench design instance name                                                                   ; max80                     ;
 ; Do not write top level VHDL entity                                                                ; Off                       ;
 ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
 ; Architecture name in VHDL output netlist                                                          ; structure                 ;
@@ -66,13 +68,14 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------------------------------------+---------------------------+
 
 
-+--------------------------------------------------------------+
-; Simulation Generated Files                                   ;
-+--------------------------------------------------------------+
-; Generated Files                                              ;
-+--------------------------------------------------------------+
-; /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80.vo ;
-+--------------------------------------------------------------+
++----------------------------------------------------------------------------------+
+; Simulation Generated Files                                                       ;
++----------------------------------------------------------------------------------+
+; Generated Files                                                                  ;
++----------------------------------------------------------------------------------+
+; /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80.vo                     ;
+; /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl ;
++----------------------------------------------------------------------------------+
 
 
 +-----------------------------+
@@ -81,14 +84,15 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 09:27:07 2021
+    Info: Processing started: Thu Jul 29 09:58:09 2021
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
+Info (204020): Writing VCD Dump Commands for all nodes to /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 1125 megabytes
-    Info: Processing ended: Thu Jul 29 09:27:08 2021
+    Info: Peak virtual memory: 1128 megabytes
+    Info: Processing ended: Thu Jul 29 09:58:10 2021
     Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
+    Info: Total CPU time (on all processors): 00:00:00
 
 

output_files/max80.fit.rpt

@@ -1,5 +1,5 @@
 Fitter report for max80
-Thu Jul 29 09:26:56 2021
+Thu Jul 29 09:58:01 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -73,7 +73,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                   ;
 +------------------------------------+---------------------------------------------+
-; Fitter Status                      ; Successful - Thu Jul 29 09:26:56 2021       ;
+; Fitter Status                      ; Successful - Thu Jul 29 09:58:01 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -166,7 +166,7 @@ https://fpgasoftware.intel.com/eula.
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.8%      ;
+;     Processor 2            ;   0.6%      ;
 +----------------------------+-------------+
 
 
@@ -1910,7 +1910,7 @@ Warning (15705): Ignored locations or region assignments to the following nodes
     Warning (15706): Node "xabc_op[2]" is assigned to location or region, but does not exist in design
     Warning (15706): Node "xabc_xio_n" is assigned to location or region, but does not exist in design
     Warning (15706): Node "xabc_xm_n" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
 Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -1929,7 +1929,7 @@ Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
 Warning (169180): Following 1 pins must use external clamping diodes.
     Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 71
@@ -2065,10 +2065,10 @@ Warning (169064): Following 45 pins have no output enable or a GND or VCC output
     Info (169065): Pin hdmi_hpd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 101
 Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 39 warnings
-    Info: Peak virtual memory: 1345 megabytes
-    Info: Processing ended: Thu Jul 29 09:26:57 2021
-    Info: Elapsed time: 00:00:11
-    Info: Total CPU time (on all processors): 00:00:11
+    Info: Peak virtual memory: 1339 megabytes
+    Info: Processing ended: Thu Jul 29 09:58:01 2021
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:10
 
 
 +----------------------------+

output_files/max80.fit.summary

@@ -1,4 +1,4 @@
-Fitter Status : Successful - Thu Jul 29 09:26:56 2021
+Fitter Status : Successful - Thu Jul 29 09:58:01 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for max80
-Thu Jul 29 09:27:08 2021
+Thu Jul 29 09:58:10 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Thu Jul 29 09:27:08 2021       ;
+; Flow Status                        ; Successful - Thu Jul 29 09:58:10 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 07/29/2021 09:26:33 ;
+; Start date & time ; 07/29/2021 09:57:39 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; max80               ;
 +-------------------+---------------------+
@@ -76,14 +76,18 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                      ; 180546899331588.162757599302772        ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID                      ; 180546899331588.162757785904250        ; --            ; --          ; --                                ;
+; EDA_ENABLE_GLITCH_FILTERING                ; On                                     ; --            ; --          ; eda_simulation                    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_symbol           ;
+; EDA_MAP_ILLEGAL_CHARACTERS                 ; On                                     ; --            ; --          ; eda_simulation                    ;
 ; EDA_OUTPUT_DATA_FORMAT                     ; Verilog Hdl                            ; --            ; --          ; eda_simulation                    ;
 ; EDA_SIMULATION_TOOL                        ; ModelSim-Altera (Verilog)              ; <None>        ; --          ; --                                ;
+; EDA_TEST_BENCH_DESIGN_INSTANCE_NAME        ; max80                                  ; --            ; --          ; eda_simulation                    ;
 ; EDA_TIME_SCALE                             ; 1 ps                                   ; --            ; --          ; eda_simulation                    ;
+; EDA_WRITE_NODES_FOR_POWER_ESTIMATION       ; ALL_NODES                              ; --            ; --          ; eda_simulation                    ;
 ; FLOW_ENABLE_POWER_ANALYZER                 ; On                                     ; Off           ; --          ; --                                ;
 ; HDL_MESSAGE_LEVEL                          ; Level3                                 ; Level2        ; --          ; --                                ;
 ; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 1                                 ;
@@ -125,13 +129,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:14     ; 1.0                     ; 1030 MB             ; 00:00:28                           ;
-; Fitter               ; 00:00:10     ; 1.0                     ; 1345 MB             ; 00:00:10                           ;
-; Assembler            ; 00:00:02     ; 1.0                     ; 904 MB              ; 00:00:02                           ;
-; Power Analyzer       ; 00:00:03     ; 1.0                     ; 1263 MB             ; 00:00:02                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 892 MB              ; 00:00:03                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 1125 MB             ; 00:00:01                           ;
-; Total                ; 00:00:32     ; --                      ; --                  ; 00:00:46                           ;
+; Analysis & Synthesis ; 00:00:13     ; 1.0                     ; 1029 MB             ; 00:00:28                           ;
+; Fitter               ; 00:00:09     ; 1.0                     ; 1339 MB             ; 00:00:09                           ;
+; Assembler            ; 00:00:01     ; 1.0                     ; 903 MB              ; 00:00:02                           ;
+; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1265 MB             ; 00:00:02                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 895 MB              ; 00:00:02                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 1128 MB             ; 00:00:00                           ;
+; Total                ; 00:00:28     ; --                      ; --                  ; 00:00:43                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 

output_files/max80.map.rpt

@@ -1,5 +1,5 @@
 Analysis & Synthesis report for max80
-Thu Jul 29 09:26:46 2021
+Thu Jul 29 09:57:52 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -67,7 +67,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Thu Jul 29 09:26:46 2021       ;
+; Analysis & Synthesis Status        ; Successful - Thu Jul 29 09:57:52 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -1093,7 +1093,7 @@ Note: In order to hide this table in the UI and the text report file, please set
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 09:26:32 2021
+    Info: Processing started: Thu Jul 29 09:57:39 2021
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
@@ -1508,9 +1508,9 @@ Info (21057): Implemented 476 device resources after synthesis - the final resou
     Info (21061): Implemented 340 logic cells
     Info (21065): Implemented 2 PLLs
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 208 warnings
-    Info: Peak virtual memory: 1079 megabytes
-    Info: Processing ended: Thu Jul 29 09:26:46 2021
-    Info: Elapsed time: 00:00:14
+    Info: Peak virtual memory: 1078 megabytes
+    Info: Processing ended: Thu Jul 29 09:57:52 2021
+    Info: Elapsed time: 00:00:13
     Info: Total CPU time (on all processors): 00:00:28
 
 

output_files/max80.map.summary

@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Thu Jul 29 09:26:46 2021
+Analysis & Synthesis Status : Successful - Thu Jul 29 09:57:52 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.pow.rpt

@@ -1,5 +1,5 @@
 Power Analyzer report for max80
-Thu Jul 29 09:27:03 2021
+Thu Jul 29 09:58:06 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------------+
 ; Power Analyzer Summary                                                                    ;
 +----------------------------------------+--------------------------------------------------+
-; Power Analyzer Status                  ; Successful - Thu Jul 29 09:27:03 2021            ;
+; Power Analyzer Status                  ; Successful - Thu Jul 29 09:58:06 2021            ;
 ; Quartus Prime Version                  ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition      ;
 ; Revision Name                          ; max80                                            ;
 ; Top-level Entity Name                  ; max80                                            ;
@@ -383,7 +383,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Power Analyzer
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 09:27:00 2021
+    Info: Processing started: Thu Jul 29 09:58:04 2021
 Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (21077): Low junction temperature is 0 degrees C
@@ -424,9 +424,9 @@ Info (334004): Delay annotation completed successfully
 Info (215049): Average toggle rate for this design is 11.008 millions of transitions / sec
 Info (215031): Total thermal power estimate for the design is 214.72 mW
 Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 1263 megabytes
-    Info: Processing ended: Thu Jul 29 09:27:03 2021
-    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:03
+    Info: Peak virtual memory: 1265 megabytes
+    Info: Processing ended: Thu Jul 29 09:58:06 2021
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
 
 

output_files/max80.pow.summary

@@ -1,4 +1,4 @@
-Power Analyzer Status : Successful - Thu Jul 29 09:27:03 2021
+Power Analyzer Status : Successful - Thu Jul 29 09:58:06 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.sta.rpt

@@ -1,5 +1,5 @@
 Timing Analyzer report for max80
-Thu Jul 29 09:27:06 2021
+Thu Jul 29 09:58:09 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -118,12 +118,12 @@ https://fpgasoftware.intel.com/eula.
 ; Number detected on machine ; 4           ;
 ; Maximum allowed            ; 2           ;
 ;                            ;             ;
-; Average used               ; 1.02        ;
+; Average used               ; 1.03        ;
 ; Maximum used               ; 2           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   2.4%      ;
+;     Processor 2            ;   2.8%      ;
 +----------------------------+-------------+
 
 
@@ -132,7 +132,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------+--------+--------------------------+
 ; SDC File Path ; Status ; Read at                  ;
 +---------------+--------+--------------------------+
-; max80.sdc     ; OK     ; Thu Jul 29 09:27:04 2021 ;
+; max80.sdc     ; OK     ; Thu Jul 29 09:58:07 2021 ;
 +---------------+--------+--------------------------+
 
 
@@ -711,14 +711,14 @@ No paths to report.
 ; 0.645 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.936      ;
 ; 0.645 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.936      ;
 ; 0.646 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.936      ;
-; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.937      ;
 ; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.937      ;
 ; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
 ; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
 ; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
-; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.938      ;
+; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.937      ;
 ; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.938      ;
 ; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.938      ;
+; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.938      ;
 ; 0.649 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.940      ;
 ; 0.652 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.943      ;
 ; 0.652 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.943      ;
@@ -1045,8 +1045,8 @@ No paths to report.
 ; 2.730 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.164     ; 2.663      ;
 ; 2.741 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 2.650      ;
 ; 2.742 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.166     ; 2.649      ;
-; 2.856 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.631      ;
 ; 2.856 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFLO   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.110     ; 2.465      ;
+; 2.856 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.631      ;
 ; 2.900 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.586      ;
 ; 2.959 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.528      ;
 ; 2.978 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]      ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.509      ;
@@ -1807,9 +1807,9 @@ No paths to report.
 ; 3.870 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFHI   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.056     ; 1.378      ;
 ; 3.876 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFHI   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.063     ; 1.365      ;
 ; 4.012 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                               ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.090     ; 1.440      ;
+; 4.049 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFLO   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.063     ; 1.383      ;
 ; 4.049 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.458      ;
 ; 4.049 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.458      ;
-; 4.049 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFLO   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.063     ; 1.383      ;
 ; 4.050 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.457      ;
 ; 4.051 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.456      ;
 ; 4.052 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                     ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.035     ; 1.455      ;
@@ -2184,10 +2184,10 @@ No paths to report.
 ; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.374      ;
 ; 0.255 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.375      ;
 ; 0.255 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.375      ;
-; 0.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.375      ;
 ; 0.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.376      ;
 ; 0.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.376      ;
 ; 0.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.376      ;
+; 0.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.375      ;
 ; 0.257 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.376      ;
 ; 0.258 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.378      ;
 ; 0.259 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.379      ;
@@ -2214,8 +2214,8 @@ No paths to report.
 ; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
 ; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
 ; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.494      ;
-; 0.303 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.422      ;
 ; 0.303 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.423      ;
+; 0.303 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.422      ;
 ; 0.305 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.497      ;
 ; 0.305 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.497      ;
 ; 0.306 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.498      ;
@@ -2274,18 +2274,15 @@ No paths to report.
 +-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
 ; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
 +-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
-; 0.194 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.314      ;
 ; 0.194 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.314      ;
 ; 0.292 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.412      ;
-; 0.293 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
-; 0.293 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
 ; 0.293 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
 ; 0.293 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
 ; 0.293 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
 ; 0.293 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
-; 0.294 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
-; 0.294 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
-; 0.294 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.293 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
+; 0.293 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
 ; 0.294 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
 ; 0.294 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
 ; 0.294 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
@@ -2293,8 +2290,9 @@ No paths to report.
 ; 0.294 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
 ; 0.294 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
 ; 0.294 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
-; 0.295 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
-; 0.295 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.294 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
 ; 0.295 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
 ; 0.295 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
 ; 0.295 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
@@ -2304,12 +2302,14 @@ No paths to report.
 ; 0.295 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
 ; 0.295 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
 ; 0.295 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
-; 0.296 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
-; 0.296 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
-; 0.296 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.295 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
 ; 0.296 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
 ; 0.296 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
 ; 0.296 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
+; 0.296 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
 ; 0.297 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.416      ;
 ; 0.297 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.416      ;
 ; 0.297 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.416      ;
@@ -2318,62 +2318,62 @@ No paths to report.
 ; 0.365 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.485      ;
 ; 0.392 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.512      ;
 ; 0.441 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.561      ;
-; 0.442 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
-; 0.442 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
 ; 0.442 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
 ; 0.442 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
 ; 0.442 ; led_ctr[10]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
 ; 0.442 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
-; 0.443 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
-; 0.443 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
+; 0.442 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
+; 0.442 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
 ; 0.443 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
 ; 0.443 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
 ; 0.443 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
 ; 0.443 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
 ; 0.443 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
-; 0.444 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
+; 0.443 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
+; 0.443 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
 ; 0.444 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
 ; 0.444 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
+; 0.444 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
 ; 0.445 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.564      ;
-; 0.452 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
 ; 0.452 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
 ; 0.452 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
 ; 0.452 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
-; 0.453 ; rst_ctr[0]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
-; 0.453 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.452 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
 ; 0.453 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.453 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.453 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.453 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
 ; 0.453 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.453 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
-; 0.454 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
-; 0.454 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.453 ; rst_ctr[0]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.453 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.454 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
 ; 0.454 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
-; 0.455 ; rst_ctr[5]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
+; 0.454 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.454 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
 ; 0.455 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.574      ;
 ; 0.455 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.574      ;
 ; 0.455 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.574      ;
 ; 0.455 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
 ; 0.455 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
 ; 0.455 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
-; 0.456 ; rst_ctr[0]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
-; 0.456 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.455 ; rst_ctr[5]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
 ; 0.456 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.456 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.456 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.456 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.456 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.575      ;
 ; 0.456 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.575      ;
-; 0.457 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
-; 0.457 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.456 ; rst_ctr[0]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.456 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.457 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
 ; 0.457 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
+; 0.457 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.457 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
 ; 0.458 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.577      ;
 ; 0.458 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.577      ;
 ; 0.504 ; led_ctr[14]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.624      ;
-; 0.505 ; rst_ctr[4]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.625      ;
+; 0.505 ; led_ctr[12]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.625      ;
 +-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
 
 
@@ -3203,7 +3203,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 09:27:04 2021
+    Info: Processing started: Thu Jul 29 09:58:07 2021
 Info: Command: quartus_sta max80 -c max80
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -3325,9 +3325,9 @@ Info (332146): Worst-case minimum pulse width slack is 2.564
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings
-    Info: Peak virtual memory: 892 megabytes
-    Info: Processing ended: Thu Jul 29 09:27:06 2021
+    Info: Peak virtual memory: 895 megabytes
+    Info: Processing ended: Thu Jul 29 09:58:09 2021
     Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
+    Info: Total CPU time (on all processors): 00:00:02