max80.sdc: add back output delay for sr_clk

Vet inte varför den försvann...

fpga/max80.sdc

@@ -32,7 +32,7 @@ set vid_clk   [get_clocks pll|*|clk\[2\]]
 set sr_data_out [remove_from_collection [get_ports sr_*] sr_clk]
 set sr_data_in  [get_ports sr_dq\[*\]]
 set_max_skew -to [get_ports sr_*] 0.100ns
-# set_output_delay -clock $sdram_clk 1.500ns [get_ports sr_clk]
+set_output_delay -clock $sdram_clk 1.500ns [get_ports sr_clk]
 set_input_delay  -clock $sdram_clk 0.500ns  $sr_data_in
 
 # Anything that feeds into a synchronizer is by definition