sdram: fix 8-bit ports; rename fw/ to rv32/ to avoid confusion

Fix bug that caused data input to get lost for an 8-bit port.

The fw/ directory is too easy to confuse with the name of the git tree
itself; furthermore there should be esp32 firmware added at some
point. Rename it to rv32/.

Makefile

@@ -1,4 +1,4 @@
-SUBDIRS = tools fw fpga
+SUBDIRS = tools rv32 fpga
 
 all clean spotless :
 	$(MAKE) local.$@ $(SUBDIRS) goal=$@

fpga/Makefile

@@ -52,7 +52,7 @@ $(outdir)/%.pow.rpt: $(outdir)/%.sta.rpt
 	$(QPOW) $*
 
 # XXX: do all .sof -> conversions using quartus_cpf
-$(outdir)/%.jic:  %jic.cof $(outdir)/%.sof ../fw/dram.hex
+$(outdir)/%.jic:  %jic.cof $(outdir)/%.sof ../rv32/dram.hex
 	$(QCPF) --convert $<
 
 # Clean out SignalTap

fpga/ip/fastmem_ip.v

@@ -97,7 +97,7 @@ module fastmem_ip (
 		altsyncram_component.byte_size = 8,
 		altsyncram_component.clock_enable_input_a = "BYPASS",
 		altsyncram_component.clock_enable_output_a = "BYPASS",
-		altsyncram_component.init_file = "../fw/boot.mif",
+		altsyncram_component.init_file = "../rv32/boot.mif",
 		altsyncram_component.intended_device_family = "Cyclone IV E",
 		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
 		altsyncram_component.lpm_type = "altsyncram",
@@ -136,7 +136,7 @@ endmodule
 // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "../fw/boot.mif"
+// Retrieval info: PRIVATE: MIFfilename STRING "../rv32/boot.mif"
 // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
@@ -154,7 +154,7 @@ endmodule
 // Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: INIT_FILE STRING "../fw/boot.mif"
+// Retrieval info: CONSTANT: INIT_FILE STRING "../rv32/boot.mif"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

fpga/max80.qsf

@@ -275,7 +275,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE abcbus.sv
 set_global_assignment -name VERILOG_FILE ip/abcmapram.v
 set_global_assignment -name VERILOG_FILE ip/fastmem_ip.v
 set_global_assignment -name SYSTEMVERILOG_FILE fast_mem.sv
-set_global_assignment -name MIF_FILE ../fw/boot.mif
+set_global_assignment -name MIF_FILE ../rv32/boot.mif
 set_global_assignment -name VERILOG_FILE picorv32.v
 set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
 set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv

fpga/max80.sv

@@ -494,7 +494,7 @@ module max80 (
    //
    wire [31:0] fast_mem_rdata;
 
-   fast_mem // #(.bits(cpu_fast_mem_bits), .mif("../fw/boot"))
+   fast_mem // #(.bits(cpu_fast_mem_bits), .mif("../rv32/boot"))
    fast_mem(
 	    .rst_n ( rst_n ),
 	    .clk   ( sys_clk ),

fpga/max80jic.cof

@@ -14,7 +14,7 @@
 		</bit0>
 	</sof_data>
 	<hex_block>
-		<hex_filename>../fw/dram.hex</hex_filename>
+		<hex_filename>../rv32/dram.hex</hex_filename>
 		<hex_addressing>relative</hex_addressing>
 		<hex_offset>1048576</hex_offset>
 		<hex_little_endian>0</hex_little_endian>

fpga/sdram.sv

@@ -150,7 +150,7 @@ module dram_port
 
    genvar i;
    generate
-      for (i = 0; i < (width >> 4); i++)
+      for (i = 0; i < ((width + 15) >> 4); i++)
 	begin : w
 	   always @(posedge bus.clk)
 	     if (started & ~ready & bus.rstrb[i])