Add *.qip files

Quartus likes to add *.qip files to the .qsf file, so humor it and
add them in.

.gitignore

@@ -13,7 +13,6 @@ greybox_tmp/
 *.cmp
 *.inc
 *.ppf
-*.qip
 *.qws
 *.pins.qsf
 *.nopins.qsf

fpga/ip/abcmapram.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "abcmapram.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "abcmapram_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "abcmapram_bb.v"]

fpga/ip/ddio_out.qip

@@ -0,0 +1,10 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddio_out.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out.ppf"]

fpga/ip/ddufifo.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddufifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddufifo_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddufifo_bb.v"]

fpga/ip/fastmem_ip.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fastmem_ip.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fastmem_ip_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fastmem_ip_bb.v"]

fpga/ip/fifo.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_bb.v"]

fpga/ip/hdmitx.qip

@@ -0,0 +1,10 @@
+set_global_assignment -name IP_TOOL_NAME "ALTLVDS_TX"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hdmitx.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.ppf"]

fpga/ip/int_osc/synthesis/int_osc.qip

@@ -0,0 +1,41 @@
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "int_osc" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../int_osc.sopcinfo"]
+set_global_assignment -entity "int_osc" -library "int_osc" -name SLD_INFO "QSYS_NAME int_osc HAS_SOPCINFO 1 GENERATION_ID 1638379169"
+set_global_assignment -library "int_osc" -name MISC_FILE [file join $::quartus(qip_path) "../int_osc.cmp"]
+set_global_assignment -library "int_osc" -name SLD_FILE [file join $::quartus(qip_path) "int_osc.debuginfo"]
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_QSYS_MODE "STANDALONE"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "int_osc" -name MISC_FILE [file join $::quartus(qip_path) "../../int_osc.qsys"]
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_NAME "aW50X29zYw=="
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_DISPLAY_NAME "aW50X29zYw=="
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYzODM3OTE2OQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxNUYxN0M4::QXV0byBERVZJQ0U="
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_NAME "YWx0ZXJhX2ludF9vc2M="
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_DISPLAY_NAME "SW50ZXJuYWwgT3NjaWxsYXRvcg=="
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_VERSION "MjAuMQ=="
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_DESCRIPTION "SW50ZXJuYWwgT3NjaWxsYXRvciBwcm92aWRlcyBpbnRlcm5hbCBjbG9jayBzb3VyY2UgZm9yIGRlYnVnZ2luZyBwdXJwb3NlLg=="
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "SU5GT1JNQVRJT04=::VGhlIG1heGltdW0gb3V0cHV0IGZyZXF1ZW5jeSBpcyA4ME1Ieg==::SU5GT1JNQVRJT04="
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBJViBF::RGV2aWNlIGZhbWlseQ=="
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "UEFSVF9OQU1F::RVA0Q0UxNUYxN0M4::RGV2aWNl"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "REVWSUNFX0lE::VU5LTk9XTg==::REVWSUNFX0lE"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfRlJFUVVFTkNZ::VU5LTk9XTg==::Q0xPQ0tfRlJFUVVFTkNZ"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "Q0JYX0FVVE9fQkxBQ0tCT1g=::QUxM::Q0JYX0FVVE9fQkxBQ0tCT1g="
+
+set_global_assignment -library "int_osc" -name VERILOG_FILE [file join $::quartus(qip_path) "int_osc.v"]
+set_global_assignment -library "int_osc" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_int_osc.v"]
+
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_NAME "altera_int_osc"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_ENV "Qsys"

fpga/ip/pll2.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll2.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2.ppf"]

fpga/ip/pll3.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll3.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll3_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll3.ppf"]

fpga/ip/pll3.v

@@ -119,7 +119,7 @@ module pll3 (
 		altpll_component.clk0_divide_by = 2,
 		altpll_component.clk0_duty_cycle = 50,
 		altpll_component.clk0_multiply_by = 7,
-		altpll_component.clk0_phase_shift = "186",
+		altpll_component.clk0_phase_shift = "372",
 		altpll_component.clk1_divide_by = 2,
 		altpll_component.clk1_duty_cycle = 50,
 		altpll_component.clk1_multiply_by = 7,
@@ -263,7 +263,7 @@ endmodule
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "11.25000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "22.50000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
@@ -315,7 +315,7 @@ endmodule
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "186"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "372"
 // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"

fpga/ip/pll4.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll4.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll4_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll4.ppf"]

fpga/ip/statusram.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "statusram.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "statusram_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "statusram_bb.v"]