sdram: rewrite as parameterized ports; usb: add USB core for testing

The sdram interface is rewritten using a general ports mechanism, so
that adding sdram users becomes a simple matter of instantiating a new
port object, and connect a single dram_bus object to the controller.

Add a USB core. This USB core is more low-level than we probably want,
but it might be useful for testing. As configured, it uses gpio[1,3,5]
as an upstream USB bus implementing a CDC copy of the console tty.

Fix some software bugs in the sdcard code which would cause hangs when
started without an sdcard in the slot.

fpga/abcbus.sv

@@ -57,12 +57,10 @@ module abcbus (
 	       // SDRAM interface
 	       output [24:0]	 sdram_addr,
 	       input [7:0]	 sdram_rd,
-	       output reg	 sdram_rrq,
-	       input		 sdram_rack,
-	       input		 sdram_rready,
+	       output reg	 sdram_valid,
+	       input		 sdram_ready,
 	       output [7:0]	 sdram_wd,
-	       output reg	 sdram_wrq,
-	       input		 sdram_wack
+	       output reg	 sdram_wstrb
 	       );
 
    // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
@@ -291,12 +289,6 @@ module abcbus (
    reg	      abc_memwr_en;
    reg	      abc_do_memrd;
    reg	      abc_do_memwr;
-   reg	      abc_racked;
-   reg	      abc_wacked;
-
-   wire       abc_rack;
-   wire       abc_wack;
-   wire       abc_rready;
 
    always @(posedge sdram_clk or negedge rst_n)
      if (~rst_n)
@@ -305,10 +297,8 @@ module abcbus (
 	  abc_memwr_en   <= 1'b0;
 	  abc_do_memrd   <= 1'b0;
 	  abc_do_memwr   <= 1'b0;
-	  sdram_rrq      <= 1'b0;
-	  sdram_wrq      <= 1'b0;
-	  abc_racked     <= 1'b0;
-	  abc_wacked     <= 1'b0;
+	  sdram_valid    <= 1'b0;
+	  sdram_wstrb    <= 1'b0;
        end
      else
        begin
@@ -320,11 +310,9 @@ module abcbus (
 
 	  abc_do_memrd  <= abc_rden & abc_memrd_en;
 	  abc_do_memwr  <= abc_wren & abc_memwr_en;
-	  abc_racked    <= abc_do_memrd & (sdram_rack | abc_racked);
-	  abc_wacked    <= abc_do_memwr & (sdram_wack | abc_wacked);
 
-	  sdram_rrq     <= abc_do_memrd & ~abc_racked;
-	  sdram_wrq     <= abc_do_memwr & ~abc_wacked;
+	  sdram_valid   <= abc_do_memrd | abc_do_memwr;
+	  sdram_wstrb   <= abc_do_memwr;
        end // else: !if(~rst_n)
 
    assign sdram_addr = abc_memaddr;
@@ -359,7 +347,7 @@ module abcbus (
    reg [3:0] bus_change_mask;
 
    wire [9:0] is_io = { abc_inp[1:0], abc_rst, 1'b0,
-			  abc_out[4:1], abc_cs, abc_out[0] };
+			abc_out[4:1], abc_cs, abc_out[0] };
 
    wire [9:0] busy_io = is_io & busy_mask;
    wire       is_busy = |(busy_status & busy_mask);
@@ -414,14 +402,14 @@ module abcbus (
      if (~rst_n)
        begin
 	  abc_d_oe <= 1'b0;
-	  abc_do    <= 8'bx;
+	  abc_do   <= 8'bx;
        end
      else
        begin
 	  abc_d_oe <= 1'b0;
-	  abc_do    <= 8'bx;
+	  abc_do   <= 8'bx;
 
-	  if (abc_xmemrd & sdram_rready)
+	  if (abc_do_memrd & sdram_ready)
 	    begin
 	       abc_d_oe <= 1'b1;
 	       abc_do   <= sdram_rd;

fpga/max80.qsf

@@ -1,12 +1,12 @@
 # -------------------------------------------------------------------------- #
 #
 # Copyright (C) 2019  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and any partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
 # Subscription Agreement, the Intel Quartus Prime License Agreement,
 # the Intel FPGA IP License Agreement, or other applicable license
 # agreement, including, without limitation, that your use is for
@@ -57,7 +57,7 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name DEVICE_MIGRATION_LIST "EP4CE15F17C8,EP4CE6F17C8,EP4CE10F17C8"
+set_global_assignment -name DEVICE_MIGRATION_LIST EP4CE15F17C8
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
@@ -190,13 +190,12 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_cs_esp_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_cs_flash_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_miso
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_mosi
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[5]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[4]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[3]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[2]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[1]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[0]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[5]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_clk
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_inp_n[1]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[13]
@@ -222,6 +221,16 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
 set_global_assignment -name POWER_USE_TA_VALUE 35
 
 
+set_global_assignment -name VERILOG_FILE usb/usb_fs_phy/src_v/usb_fs_phy.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_device_core.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_defs.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_crc16.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usb_desc_rom.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usb_cdc_top.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usb_cdc_core.v
+set_global_assignment -name SYSTEMVERILOG_FILE usb/usb.sv
 set_global_assignment -name VERILOG_FILE ip/statusram.v
 set_global_assignment -name VERILOG_INCLUDE_FILE iodevs.vh
 set_global_assignment -name SYSTEMVERILOG_FILE tty.sv
@@ -253,4 +262,6 @@ set_global_assignment -name SOURCE_FILE max80.pins
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name VERILOG_FILE ip/fifo.v
 set_global_assignment -name VERILOG_FILE ip/ddufifo.v
+
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/max80.sdc

@@ -6,12 +6,9 @@
 create_clock -name "clock_48" -period 20.834ns [get_ports {clock_48}]
 derive_pll_clocks
 
-# Handle both the RTC input clock and the internal workaround
-# The internal workaround clock should still be treated an asynchronous
+# RTC clock; asynchronous with all others
 create_clock -name "rtc_32khz" -period 30517.578ns [get_ports {rtc_32khz}]
-create_clock -name "ctr_32khz" -period 30517.578ns [get_registers {ctr_32khz}]
 set_clock_groups -asynchronous -group {rtc_32khz}
-set_clock_groups -asynchronous -group {ctr_32khz}
 
 # Automatically calculate clock uncertainty to jitter and other effects.
 derive_clock_uncertainty
@@ -43,7 +40,7 @@ set_clock_groups -asynchronous \
 # asynchronous, but encode it as allowing multicycle of one
 # clock, to limit the possible skew (but it is of course not possible
 # to eliminate it...)
-set synchro_inputs [get_registers *|synchronizer:*|qreg0*] 
+set synchro_inputs [get_registers *|synchronizer:*|qreg0*]
 set_multicycle_path -from [all_clocks] -to $synchro_inputs \
     -start -setup 2
 set_multicycle_path -from [all_clocks] -to $synchro_inputs \
@@ -62,6 +59,13 @@ set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
 set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
     -start -hold 0
 
+# -------- SDRAM multicycle paths (ready is retarded) --------
+
+set_multicycle_path -from [get_registers {dram_port:cpu_dram_port|rd[*]}] \
+    -to $sys_clk -setup 2
+set_multicycle_path -from [get_registers {dram_port:cpu_dram_port|rd[*]}] \
+    -to $sys_clk -hold 2
+
 # -------- SPI ROM multicycle paths --------
 
 # the load of the spi_data_ctr register happens no less than 2 target

fpga/max80.sv

@@ -219,28 +219,50 @@ module max80 (
    //
    // SDRAM
    //
+   localparam dram_port_count = 2;
+   dram_bus sr_bus[1:dram_port_count] ( );
 
    // ABC interface
    wire [24:0] abc_sr_addr;
    wire [ 7:0] abc_sr_rd;
-   wire        abc_sr_rrq;
-   wire        abc_sr_rack;
-   wire        abc_sr_rready;
+   wire        abc_sr_valid;
+   wire        abc_sr_ready;
    wire [ 7:0] abc_sr_wd;
-   wire        abc_sr_wrq;
-   wire        abc_sr_wack;
+   wire        abc_sr_wstrb;
+
+   dram_port #(8)
+   abc_dram_port (
+		  .bus   ( sr_bus[1] ),
+		  .prio  ( 2'd3 ),
+		  .addr  ( abc_sr_addr ),
+		  .rd    ( abc_sr_rd ),
+		  .valid ( abc_sr_valid ),
+		  .ready ( abc_sr_ready ),
+		  .wd    ( abc_sr_wd ),
+		  .wstrb ( abc_sr_wstrb )
+		  );
 
    // CPU interface
-   wire [31:0] sdram_rd;
-   wire        sdram_rack;
-   wire        sdram_rready;
-   wire        sdram_wack;
-   reg	       sdram_acked;
-   wire        sdram_valid = cpu_mem_quad[1];
-   wire        sdram_req = sdram_valid & ~sdram_acked;
+   wire [31:0] sdram_mem_rdata;
+   wire        sdram_ready;
+   reg	       sdram_mem_ready;
 
-   always @(posedge sdram_clk)
-     sdram_acked <= sdram_valid & (sdram_acked | sdram_rack | sdram_wack);
+   // Retard sdram_ready by one sys_clk (multicycle path for the data,
+   // see max80.sdc)
+   always @(posedge sys_clk)
+     sdram_mem_ready <= sdram_ready;
+
+   dram_port #(32)
+   cpu_dram_port (
+		  .bus   ( sr_bus[2] ),
+		  .prio  ( 2'd1 ),
+		  .addr  ( cpu_mem_addr[24:0] ),
+		  .rd    ( sdram_mem_rdata ),
+		  .valid ( cpu_mem_quad[1] ),
+		  .ready ( sdram_ready ),
+		  .wd    ( cpu_mem_wdata ),
+		  .wstrb ( cpu_mem_wstrb )
+		  );
 
    // Romcopy interface
    wire [15:0] sdram_rom_wd;
@@ -248,45 +270,30 @@ module max80 (
    wire [ 1:0] sdram_rom_wrq;
    wire        sdram_rom_wacc;
 
-   sdram sdram (
-		.rst_n    ( rst_n ),
-		.clk      ( sdram_clk ), // Internal clock
-		.out_clk  ( sdram_out_clk ), // External clock (phase shifted)
-
-		.sr_clk   ( sr_clk ),    // Output clock buffer
-		.sr_cke   ( sr_cke ),
-		.sr_cs_n  ( sr_cs_n ),
-		.sr_ras_n ( sr_ras_n ),
-		.sr_cas_n ( sr_cas_n ),
-		.sr_we_n  ( sr_we_n ),
-		.sr_dqm   ( sr_dqm ),
-		.sr_ba    ( sr_ba ),
-		.sr_a     ( sr_a ),
-		.sr_dq    ( sr_dq ),
-
-		.a0       ( abc_sr_addr ),
-		.rd0      ( abc_sr_rd ),
-		.rrq0     ( abc_sr_rrq ),
-		.rack0    ( abc_sr_rack ),
-		.rready0  ( abc_sr_rready ),
-		.wd0      ( abc_sr_wd ),
-		.wrq0     ( abc_sr_wrq ),
-		.wack0    ( abc_sr_wack ),
-
-		.a1       ( cpu_mem_addr[24:2] ),
-		.rd1      ( sdram_rd ),
-		.rrq1     ( sdram_req & ~|cpu_mem_wstrb ),
-		.rack1    ( sdram_rack ),
-		.rready1  ( sdram_rready ),
-		.wd1      ( cpu_mem_wdata ),
-		.wstrb1   ( {4{sdram_req}} & cpu_mem_wstrb ),
-		.wack1    ( sdram_wack ),
-
-		.a2       ( sdram_rom_waddr ),
-		.wd2      ( sdram_rom_wd ),
-		.wrq2     ( sdram_rom_wrq ),
-		.wacc2    ( sdram_rom_wacc )
-		);
+   sdram #(.port1_count(dram_port_count))
+   sdram (
+	  .rst_n    ( rst_n ),
+	  .clk      ( sdram_clk ), // Internal clock
+	  .out_clk  ( sdram_out_clk ), // External clock (phase shifted)
+
+	  .sr_clk   ( sr_clk ),    // Output clock buffer
+	  .sr_cke   ( sr_cke ),
+	  .sr_cs_n  ( sr_cs_n ),
+	  .sr_ras_n ( sr_ras_n ),
+	  .sr_cas_n ( sr_cas_n ),
+	  .sr_we_n  ( sr_we_n ),
+	  .sr_dqm   ( sr_dqm ),
+	  .sr_ba    ( sr_ba ),
+	  .sr_a     ( sr_a ),
+	  .sr_dq    ( sr_dq ),
+
+	  .port1    ( sr_bus ),
+
+	  .a2       ( sdram_rom_waddr ),
+	  .wd2      ( sdram_rom_wd ),
+	  .wrq2     ( sdram_rom_wrq ),
+	  .wacc2    ( sdram_rom_wacc )
+	  );
 
    //
    // ABC-bus interface
@@ -338,14 +345,12 @@ module max80 (
 		  .exth_hg ( exth_hg ),
 		  .exth_hh ( exth_hh ),
 
-		  .sdram_addr ( abc_sr_addr ),
-		  .sdram_rd ( abc_sr_rd ),
-		  .sdram_rrq ( abc_sr_rrq ),
-		  .sdram_rack ( abc_sr_rack ),
-		  .sdram_rready ( abc_sr_rready ),
-		  .sdram_wd ( abc_sr_wd ),
-		  .sdram_wrq ( abc_sr_wrq ),
-		  .sdram_wack ( abc_sr_wack )
+		  .sdram_addr  ( abc_sr_addr ),
+		  .sdram_rd    ( abc_sr_rd ),
+		  .sdram_valid ( abc_sr_valid ),
+		  .sdram_ready ( abc_sr_ready ),
+		  .sdram_wd    ( abc_sr_wd ),
+		  .sdram_wstrb ( abc_sr_wstrb )
 		  );
 
    // GPIO
@@ -433,24 +438,6 @@ module max80 (
 	.eoi ( cpu_eoi )
 	);
 
-   // cpu_mem_ready is always true for fast memory; for SDRAM we have to
-   // wait either for a write ack or a low-high transition on the
-   // read ready signal.
-   reg sdram_rready_q;
-   reg sdram_mem_ready;
-   reg [31:0] sdram_rdata;
-   always @(posedge sys_clk)
-     begin
-	sdram_rready_q <= sdram_rready;
-	if (cpu_mem_quad[1])
-	  sdram_mem_ready <= sdram_mem_ready | sdram_wack |
-			     (sdram_rready & ~sdram_rready_q);
-	else
-	  sdram_mem_ready <= 1'b0;
-
-	sdram_rdata <= sdram_rd;
-     end
-
    // Add a mandatory wait state to iodevs to reduce the size
    // of the CPU memory input MUX (it hurts timing on memory
    // accesses...)
@@ -489,10 +476,10 @@ module max80 (
    reg [31:0]  iodev_rdata_q;
 
    // Read data MUX
-   always @(*)
+   always_comb
      case ( cpu_mem_quad )
        4'b0001: cpu_mem_rdata = fast_mem_rdata;
-       4'b0010: cpu_mem_rdata = sdram_rdata;
+       4'b0010: cpu_mem_rdata = sdram_mem_rdata;
        4'b1000: cpu_mem_rdata = iodev_rdata_q;
        default: cpu_mem_rdata = 32'hxxxx_xxxx;
      endcase
@@ -512,7 +499,7 @@ module max80 (
    //    [0] - RTC 32 kHz pullup and serial port RxD/TxD swap
    // [15:1] - reserved
    //
-   wire        rtc_32khz_rework;
+   wire        rtc_32khz_rework = 1'b1;
 
    wire [ 7:0] max80_major = 8'd1;
    wire [ 7:0] max80_minor = 8'd0;
@@ -601,40 +588,22 @@ module max80 (
 	    .tty_txd ( tty_data_out ) // DTE -> DCE
 	    );
 
-`ifdef WORKAROUNDS
-   reg [1:0]   tty_dtr_q;
-   always @(posedge sys_clk)
-     begin
-	tty_dtr_q[0] <= tty_dtr;
-	tty_dtr_q[1] <= gpio[4];
-     end
-
-   //
-   // Route data to the two output ports
-   //
-
-   // tty_rxd because pins are DCE named
-   assign tty_data_in = (tty_txd | tty_dtr_q[0]) &
-			(gpio[0] | tty_dtr_q[1]);
-
-   assign tty_rxd = tty_dtr_q[0] ? 1'bz : tty_data_out;
-   assign gpio[1] = tty_dtr_q[1] ? 1'bz : tty_data_out;
-
-   assign tty_rts_in = (tty_rts | tty_dtr_q[0]) &
-		       (gpio[2] | tty_dtr_q[1]);
-
-   assign tty_cts = tty_dtr_q[0] ? 1'bz : tty_cts_out;
-   assign gpio[3] = tty_dtr_q[1] ? 1'bz : tty_cts_out;
+`ifdef USB
+   max80_usb usb (
+		  .rst_n   ( rst_n ),
+		  .clock48 ( clock_48 ),
+		  .tty_rxd ( ),
+		  .tty_txd ( tty_data_out ),
+		  .usb_dp  ( gpio[3] ),
+		  .usb_dn  ( gpio[5] ),
+		  .usb_pu  ( gpio[1] )
+		  );
+`endif
 
-   // DTR on GPIO -> assume RTC 32 kHz output is nonfunctional
-   assign rtc_32khz_rework = tty_dtr_q[1];
-`else
    assign tty_data_in      = tty_txd;
    assign tty_rxd          = tty_data_out;
    assign tty_rts_in       = tty_rts;
    assign tty_cts          = tty_cts_out;
-   assign rtc_32khz_rework = 1'b1;
-`endif
 
    // SD card
    sdcard #(
@@ -662,31 +631,7 @@ module max80 (
 
    // System local clock (not an RTC, but settable from one)
    // Also provides a periodic interrupt (set to 32 Hz)
-   //
-   // XXX: the RTC 32 kHz signal is missing a pull-up,
-   // so unless the board has been reworked, use a
-   // divider down from the 84 MHz system clock. The
-   // error is about 200 ppm; a proper NCO could do better.
-
-`ifdef WORKAROUNDS
-   reg		ctr_32khz;
-   reg [10:0]	ctr_64khz;
-   always @(posedge sys_clk)
-     begin
-	if (~|ctr_64khz)
-	  begin
-	     ctr_32khz <= ~ctr_32khz;
-	     ctr_64khz <= 11'd1280;
-	  end
-	else
-	  ctr_64khz <= ctr_64khz - 1'b1;
-     end
-
-   // 32kHz clock synchronized with sys_clk
-   wire clk_32kHz = rtc_32khz_rework ? ~rtc_32khz : ctr_32khz;
-`else // !`ifdef WORKAROUNDS
    wire clk_32kHz = ~rtc_32khz;
-`endif
 
    sysclock #(.PERIODIC_HZ_LG2 ( TIMER_SHIFT ))
    sysclock (

fpga/output_files/max80.jdi

@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="15b66488aa38b60892ec"/>
+    <hash md5_digest_80b="3d94b4a70488ee842ac5"/>
   </project>
   <file_info>
     <file device="EP4CE15F17C8" path="max80.sof" usercode="0xFFFFFFFF"/>

fpga/sdram.sv

@@ -16,12 +16,14 @@
 //  Very simple non-parallelizing SDRAM controller.
 //
 //
-//  Two ports are provided: port 0 is single byte per transaction,
-//  and has highest priority; it is intended for transactions from the
-//  ABC-bus. Port 1 does aligned 4-byte accesses with byte enables.
+//  Two ports are provided:
+//  Port 1 does aligned 4-byte accesses with byte enables.
 //  Port 2 does aligned 8-byte accesses, write only, with no byte
 //  enables; it supports streaming from a FIFO.
 //
+//  Port 1 is multiplexed via an arbiter, which receives a bus
+//  defined by the sdram_bus interface.
+//
 //  All signals are in the sdram clock domain.
 //
 //  [rw]ack is asserted at the beginning of a read- or write cycle and
@@ -30,8 +32,215 @@
 //  transaction is complete and rack is deasserted.
 //
 
+//
+// The interface to the port modules. The read data is 16 bits
+// at a time, and is only valid in the cycle rstrb[x] is asserted.
+//
+// The only output signal that is unique to this port
+// is "start". All other signals are broadcast.
+//
+interface dram_bus;
+   logic [1:0]	prio;		// Priority vs refresh
+   logic        rst_n;
+   logic        clk;
+   logic [24:0] addr;
+   logic	addr0;		// addr[0] latched at transaction start
+   logic [15:0] rd;
+   logic	req;
+   logic  [1:0]	rstrb;		// Data read strobe
+   logic [31:0] wd;
+   logic  [3:0] wstrb;
+   logic	start;		// Transaction start
+   logic	wrack;		// Transaction is a write
+
+   // Upstream direction
+   modport ustr (
+		input  prio,
+		output rst_n,
+		output clk,
+		input  addr,
+		output addr0,
+		output rd,
+		input  req,
+		output rstrb,
+		input  wd,
+		input  wstrb,
+		output start,
+		output wrack
+		);
+
+   // Downstream direction
+   modport dstr (
+		output prio,
+		input  rst_n,
+		input  clk,
+		output addr,
+		input  addr0,
+		input  rd,
+		output req,
+		input  rstrb,
+		output wd,
+		output wstrb,
+		input  start,
+		input  wrack
+		 );
+endinterface // dram_bus
+
+// Port into the DRAM
+module dram_port
+  #(parameter width = 32)
+  (
+   dram_bus.dstr            bus,
+   input             [1:0]  prio,
+
+   input             [24:0] addr,
+   output reg   [width-1:0] rd,
+   input	            valid,
+   output reg               ready,
+   input        [width-1:0] wd,
+   input [(width >> 3)-1:0] wstrb
+   );
+
+   reg started;
+
+   assign bus.prio  = prio;
+   assign bus.addr  = addr;
+   assign bus.req   = valid & ~started;
+
+   always_comb
+     begin
+	bus.wd    = 32'hxxxx_xxxx;
+	bus.wstrb = 4'b0000;
+
+	if (width == 8)
+	  begin
+	     bus.wd[15:0]   = { wd, wd };
+	     bus.wstrb[1:0] = { wstrb[0] & addr[0], wstrb[0] & ~addr[0] };
+	  end
+	else
+	  begin
+	     bus.wd[width-1:0]           = wd;
+	     bus.wstrb[(width >> 3)-1:0] = wstrb;
+	  end
+     end
+
+   always @(negedge bus.rst_n or posedge bus.clk)
+     if (~bus.rst_n)
+       begin
+	  ready   <= 1'b0;
+	  started <= 1'b0;
+       end
+     else
+       begin
+	  if (~valid)
+	    begin
+	       ready   <= 1'b0;
+	       started <= 1'b0;
+	    end
+	  else if (bus.start)
+	    begin
+	       started <= 1'b1;
+	       ready   <= |bus.wstrb; // All write data latched
+	    end
+	  else if (started & ~ready)
+	    begin
+	       ready <= bus.rstrb[(width - 1) >> 4];
+	    end
+       end // else: !if(~bus.rst_n)
+
+   genvar i;
+   generate
+      for (i = 0; i < (width >> 4); i++)
+	begin : w
+	   always @(posedge bus.clk)
+	     if (started & ~ready & bus.rstrb[i])
+	       begin
+		  if (width == 8)
+		    rd <= bus.addr0 ? bus.rd[15:8] : bus.rd[7:0];
+		  else
+		    rd[i*16+15:i*16] <= bus.rd;
+	       end
+	end
+   endgenerate
+endmodule // dram_port
+
+module dram_arbiter
+  #(parameter port_count = 1)
+   (
+    dram_bus.ustr ustr [1:port_count],
+    dram_bus.dstr dstr,
+    input [1:0] rfsh_prio,
+    output logic do_rfsh
+    );
+
+   logic [port_count:0] requesting;
+   logic [24:0] addr  [1:port_count];
+   logic [31:0] wd    [1:port_count];
+   logic [3:0]  wstrb [1:port_count];
+   logic [1:0]	prio  [1:port_count];
+
+   always_comb
+     requesting[0] = 1'b0;
+
+   genvar  i;
+   generate
+      for (i = 1; i <= port_count; i++)
+	begin : u
+	   always_comb
+	     begin
+		ustr[i].rst_n = dstr.rst_n;
+		ustr[i].clk   = dstr.clk;
+		ustr[i].addr0 = dstr.addr0;
+		ustr[i].rd    = dstr.rd;
+		ustr[i].rstrb = dstr.rstrb;
+		ustr[i].wrack = dstr.wrack;
+		ustr[i].start = 1'b0;
+
+		addr[i]       = ustr[i].addr;
+		wd[i]         = ustr[i].wd;
+		wstrb[i]      = ustr[i].wstrb;
+		prio[i]       = ustr[i].prio;
+
+		if (~|requesting[i-1:0] & ustr[i].req)
+		  begin
+		     requesting[i] = 1'b1;
+		     ustr[i].start = dstr.start & (ustr[i].prio >= rfsh_prio);
+		  end
+		else
+		  begin
+		     requesting[i] = 1'b0;
+		     ustr[i].start = 1'b0;
+		  end
+	     end // always_comb
+	end // for (i = 1; i <= port_count; i++)
+   endgenerate
+
+   always_comb
+     begin
+	dstr.req   = 1'b0;
+	dstr.addr  = 25'bx;
+	dstr.wd    = 32'bx;
+	dstr.wstrb = 4'bx;
+	do_rfsh    = |rfsh_prio;
+
+	for (int j = 1; j <= port_count; j++)
+	  begin
+	     if (requesting[j])
+	       begin
+		  dstr.req   = 1'b1;
+		  dstr.addr  = addr[j];
+		  dstr.wd    = wd[j];
+		  dstr.wstrb = wstrb[j];
+		  do_rfsh    = prio[j] < rfsh_prio;
+	       end
+	  end // for (int j = 1; j <= port_count; j++)
+     end // always_comb
+endmodule // dram_arbiter
+
 module sdram
 #( parameter
+   port1_count     =  1,
+
    //  Timing parameters
    //  The parameters are hardcoded for Micron MT48LC16M16A2-6A,
    //  per datasheet:
@@ -84,29 +293,8 @@ module sdram
 	      output [12:0]	sr_a, // SDRAM address bus
 	      inout [15:0]	sr_dq, // SDRAM data bus
 
-	      // Port 0: single byte, high priority
-	      input [24:0]	a0, // Address, must be stable until ack
-
-	      output reg [7:0]	rd0, // Data from SDRAM
-	      input		rrq0, // Read request
-	      output reg	rack0, // Read ack (transaction started)
-	      output reg	rready0, // Read data valid
-
-	      input [7:0]	wd0, // Data to SDRAM
-	      input		wrq0, // Write request
-	      output reg	wack0, // Write ack (data latched)
-
 	      // Port 1
-	      input [24:2]	a1,
-
-	      output reg [31:0] rd1,
-	      input		rrq1,
-	      output reg	rack1,
-	      output reg	rready1,
-
-	      input [31:0]	wd1,
-	      input [3:0]	wstrb1,
-	      output reg	wack1,
+              dram_bus.ustr     port1 [1:port1_count],
 
 	      // Port 2
 	      input [24:1]	a2,
@@ -117,8 +305,6 @@ module sdram
 
 `include "functions.sv"		// For modelsim
 
-   wire				wrq1 = |wstrb1;
-
    // Mode register data
    wire			    mrd_wburst = 1'b1;     // Write bursts enabled
    wire [2:0]		    mrd_cl     = t_cl;
@@ -194,6 +380,7 @@ module sdram
    reg [1:0]		    dram_dqm;
    assign		    sr_dqm = dram_dqm;
    reg [15:0]		    dram_d; // Data to DRAM
+   reg [15:0]		    dram_q; // Data from DRAM (I/O buffers)
    reg			    dram_d_en; // Drive data out
    assign		    sr_dq = dram_d_en ? dram_d : 16'hzzzz;
 
@@ -203,9 +390,22 @@ module sdram
    reg			      rfsh_ctr_last_msb;
    wire			      rfsh_tick = rfsh_ctr_last_msb & ~rfsh_ctr_msb;
    reg [t_p_lg2:t_refi_lg2-1] init_ctr;  // Reset to init counter
-   reg [1:0]		      rfsh_prio; // Refresh priority
-					 // Bit 0 - refresh if opportune
-					 // Bit 1 - refresh urgent
+   reg [1:0]		      rfsh_prio; // Refresh priority (0-3)
+
+   // Port1 and refresh arbiter
+   dram_bus                   p1 ();
+   wire			      do_rfsh;
+
+   assign p1.rst_n = rst_n;
+   assign p1.clk   = clk;
+
+   dram_arbiter #(.port_count(port1_count))
+   arbiter (
+	    .ustr      ( port1 ),
+	    .dstr      ( p1.dstr ),
+	    .rfsh_prio ( rfsh_prio ),
+	    .do_rfsh   ( do_rfsh )
+	    );
 
    // The actual values are unimportant; the compiler will optimize
    // the state machine implementation.
@@ -216,11 +416,9 @@ module sdram
 	 st_idle,		// Idle state: all banks precharged
 	 st_rfsh,
 	 st_rd_wr,		// Port 0/1 transaction
-	 st_pre_idle,
 	 st_wr2			// Port 2 write (burstable)
    } state_t;
    state_t state = st_reset;
-   reg		is_write;
 
    always @(posedge clk or negedge rst_n)
      if (~rst_n)
@@ -234,11 +432,11 @@ module sdram
 	  rfsh_ctr           <= rfsh_ctr + 1'b1;
 	  rfsh_ctr_last_msb  <= rfsh_ctr_msb;
 
-	  // Refresh priority management
+	  // Refresh priority management: saturating 2-bit counter
 	  if (is_rfsh)
 	    rfsh_prio <= 2'b00; // This is a refresh cycle
-	  else if (rfsh_tick)
-	    rfsh_prio <= { rfsh_prio[0], 1'b1 };
+	  else
+	    rfsh_prio <= rfsh_prio + (rfsh_tick & ~&rfsh_prio);
 
 	  // The refresh counter is also used as a prescaler
 	  // for the initialization counter.
@@ -247,7 +445,7 @@ module sdram
 	  init_ctr <= init_ctr + rfsh_tick;
        end // else: !if(~rst_n)
 
-   reg [5:0] op_ctr;		// Cycle into the current state
+   reg  [5:0] op_ctr;		// Cycle into the current state
    wire [3:0] op_cycle    = op_ctr[3:0]; // Cycle into the current command
    wire [1:0] init_op_ctr = op_ctr[5:4]; // Init operation counter
    reg	      op_zero;		// op_cycle wrap around (init_op_ctr changed)
@@ -257,6 +455,10 @@ module sdram
    reg [ 9:0] col_addr;
    reg	      wrq2_more;
 
+   assign p1.start = (state == st_idle);
+   assign p1.addr0 = col_addr[0];
+   assign p1.rd = dram_q;
+
    //
    // Careful with the timing here... there is one cycle between
    // registers and wires, and the DRAM observes the clock 1/2
@@ -273,22 +475,17 @@ module sdram
 	  dram_ba       <= 2'bxx;
 	  dram_dqm      <= 2'b00;
 	  dram_d        <= 16'hxxxx;
+	  dram_q        <= 16'hxxxx;
 	  dram_d_en     <= 1'b1; // Don't float except during read
 
 	  op_ctr        <= 6'h0;
 	  op_zero       <= 1'b0;
 	  state         <= st_reset;
-	  is_write      <= 1'bx;
-
-	  rack0         <= 1'b0;
-	  rready0       <= 1'b1;
-	  wack0         <= 1'b0;
+	  p1.wrack      <= 1'bx;
+	  p1.rd         <= 16'hxxxx;
+	  p1.rstrb      <= 2'b00;
 
-	  rack1         <= 1'b0;
-	  rready1       <= 1'b1;
-	  wack1         <= 1'b0;
 	  wacc2         <= 1'b0;
-
 	  wrq2_more     <= 1'bx;
 
 	  wdata_q       <= 32'hxxxx_xxxx;
@@ -299,22 +496,16 @@ module sdram
        begin
 	  // Default values
 	  // Note: dram_ba are preserved
-	  dram_a        <= 13'hxxxx;
+	  dram_a        <= 13'b0;
 	  dram_dqm      <= 2'b00;
 	  dram_d        <= 16'haaaa;
 	  dram_cmd      <= cmd_nop;
 
 	  dram_d_en     <= 1'b1; // Don't float except during read
 
-	  if (state != st_rd_wr)
-	    begin
-	       rack0 <= 1'b0;
-	       wack0 <= 1'b0;
-	       rack1 <= 1'b0;
-	       wack1 <= 1'b0;
-	    end
-
-	  wacc2 <= 1'b0;
+	  dram_q        <= sr_dq;
+	  p1.rstrb      <= 2'b00;
+	  wacc2         <= 1'b0;
 
 	  if (state == st_reset || state == st_idle)
 	    begin
@@ -365,7 +556,7 @@ module sdram
 
 	    st_idle:
 	      begin
-		 is_write <= 1'bx;
+		 p1.wrack <= 1'bx;
 		 be_q     <= 4'bxxxx;
 		 wdata_q  <= 32'hxxxx_xxxx;
 
@@ -380,73 +571,35 @@ module sdram
 		 dram_ba <= 2'bxx;
 		 dram_d  <= 16'hbbbb;
 
-		 casez ( {rrq0|wrq0, rrq1|wrq1, wrq2[0], rfsh_prio} )
-		   5'b1????:
-		     begin
-			// Begin port 0 transaction
-			dram_cmd     <= cmd_act;
-			dram_a       <= a0[24:12];
-			dram_ba      <= a0[11:10];
-			col_addr     <= a0[9:0];
-			if ( wrq0 )
-			  begin
-			     state    <= st_rd_wr;
-			     wack0    <= 1'b1;
-			     wdata_q  <= {16'hxxxx, wd0, wd0};
-			     be_q     <= {2'b00, a0[0], ~a0[0]};
-			     is_write <= 1'b1;
-			  end
-			else
-			  begin
-			     state    <= st_rd_wr;
-			     rack0    <= 1'b1;
-			     rready0  <= 1'b0;
-			     is_write <= 1'b0;
-			  end
-		     end
-		   5'b01?0?:
-		     begin
-			// Begin port 1 transaction
-			dram_cmd     <= cmd_act;
-			dram_a       <= a1[24:12];
-			dram_ba      <= a1[11:10];
-			col_addr     <= { a1[9:2], 2'b00 };
-			if ( wrq1 )
-			  begin
-			     state    <= st_rd_wr;
-			     wack1    <= 1'b1;
-			     wdata_q  <= wd1;
-			     be_q     <= wstrb1;
-			     is_write <= 1'b1;
-			  end
-			else
-			  begin
-			     state    <= st_rd_wr;
-			     rack1    <= 1'b1;
-			     rready1  <= 1'b0;
-			     is_write <= 1'b0;
-			  end
-		     end
-		   5'b0??1?, 5'b00?01:
-		     begin
-			// Begin refresh transaction
-			dram_cmd    <= cmd_ref;
-			state       <= st_rfsh;
-		     end
-		   5'b00100:
-		     begin
-			// Begin port 2 write
-			dram_cmd    <= cmd_act;
-			dram_a      <= a2[24:12];
-			dram_ba     <= a2[11:10];
-			state       <= st_wr2;
-		     end
-		   default:
-		     begin
-			dram_cmd    <= cmd_desl;
-			state       <= st_idle;
-		     end
-		 endcase // casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_prio} )
+		 if (do_rfsh)
+		   begin
+		      dram_cmd    <= cmd_ref;
+		      state       <= st_rfsh;
+		   end
+		 else if (p1.req)
+		   begin
+		      dram_cmd     <= cmd_act;
+		      dram_a       <= p1.addr[24:12];
+		      dram_ba      <= p1.addr[11:10];
+		      col_addr     <= p1.addr[9:0];
+		      p1.wrack     <= |p1.wstrb;
+		      wdata_q      <= p1.wd;
+		      be_q         <= p1.wstrb;
+		      state        <= st_rd_wr;
+		   end // if (p1.req)
+		 else if (wrq2[0])
+		   begin
+		      // Begin port 2 write
+		      dram_cmd    <= cmd_act;
+		      dram_a      <= a2[24:12];
+		      dram_ba     <= a2[11:10];
+		      state       <= st_wr2;
+		   end
+		 else
+		   begin
+		      dram_cmd    <= cmd_desl;
+		      state       <= st_idle;
+		   end
 	      end // case: st_idle
 
 	    st_rfsh:
@@ -457,9 +610,12 @@ module sdram
 
 	    st_rd_wr:
 	      begin
-		 dram_d_en <= is_write;
-		 dram_dqm  <= {2{is_write}};
-		 dram_d <= 16'hcccc;
+		 dram_d_en <= p1.wrack;
+		 dram_dqm  <= {2{p1.wrack}};
+		 dram_d    <= 16'hcccc ^ {16{p1.wrack}};
+
+		 if (op_cycle < 7)
+		   dram_q <= op_cycle * 16'h1111;
 
 		 // Commands
 		 //
@@ -476,17 +632,13 @@ module sdram
 		   2: begin
 		      dram_a[10]   <= 1'b0; // No auto precharge
 		      dram_a[8:0]  <= col_addr[9:1];
-		      dram_cmd     <= is_write ? cmd_wr : cmd_rd;
+		      dram_cmd     <= p1.wrack ? cmd_wr : cmd_rd;
 		      dram_d       <= wdata_q[15:0];
-		      dram_dqm     <= {2{is_write}} & ~be_q[1:0];
-		      wdata_q      <= { 16'hdddd, wdata_q[31:16] };
-		      be_q         <= { 2'hxx, be_q[3:2] };
+		      dram_dqm     <= {2{p1.wrack}} & ~be_q[1:0];
 		   end
 		   3: begin
-		      dram_d       <= wdata_q[15:0];
-		      dram_dqm     <= {2{is_write}} & ~be_q[1:0];
-		      wdata_q      <= { 16'heeee, wdata_q[31:16] };
-		      be_q         <= 4'bxxxx;
+		      dram_d       <= wdata_q[31:16];
+		      dram_dqm     <= {2{p1.wrack}} & ~be_q[3:2];
 		   end
 		   6: begin
 		      // Earliest legal cycle to precharge
@@ -498,32 +650,17 @@ module sdram
 		   // CL+2 cycles after the read command
 		   // The +2 accounts for internal and I/O delays
 		   7: begin
-		      if (rack0)
-			rd0 <= col_addr[0] ? sr_dq[15:8] : sr_dq[7:0];
-		      rready0 <= rready0 | rack0;
-		      if (rack1)
-			rd1[15:0] <= sr_dq;
+		      p1.rstrb[0] <= ~p1.wrack;
 		   end
 		   8: begin
-		      if (rack1)
-			rd1[31:16] <= sr_dq;
-		      rready1 <= rready1 | rack1;
-
-		      state <= st_pre_idle;
+		      p1.rstrb[1] <= ~p1.wrack;
+		   end
+		   9: begin
+		      state <= st_idle;
 		   end
 		 endcase // case (op_cycle)
 	      end // case: st_rd_wr
 
-	    st_pre_idle:
-	      begin
-		 // Last cycle before tRC is a separate state
-		 // so that rack/wack will be cleared
-
-		 dram_d_en <= is_write;
-		 dram_dqm  <= {2{is_write}};
-		 state <= st_idle;
-	      end
-
 	    st_wr2:
 	      begin
 		 // Streamable write from flash ROM
@@ -548,8 +685,7 @@ module sdram
 		   end
 		   4: begin
 		      dram_cmd  <= cmd_wr;
-		      if (wrq2_more &
-			  ~(rrq0|wrq0|rrq1|wrq1|(|rfsh_prio)|(&dram_a[8:2])))
+		      if (wrq2_more & ~(p1.req | do_rfsh))
 			begin
 			   // Burst can continue
 			   wacc2       <= 1'b1;

fpga/spirom.sv

@@ -9,30 +9,30 @@
 //
 
 module spirom (
-	       input 		 rst_n,
-	       input 		 rom_clk,
-	       input 		 ram_clk,
-	       input 		 sys_clk,
+	       input		 rst_n,
+	       input		 rom_clk,
+	       input		 ram_clk,
+	       input		 sys_clk,
 
 	       /* SPI ROM interface */
-	       output 		 spi_sck,
-	       inout [1:0] 	 spi_io,
-	       output reg 	 spi_cs_n,
+	       output		 spi_sck,
+	       inout [1:0]	 spi_io,
+	       output reg	 spi_cs_n,
 
 	       /* SDRAM interface */
-	       output [15:0] 	 wd, // Data to RAM
+	       output [15:0]	 wd, // Data to RAM
 	       (* syn_preserve = 1 *)	// Don't merge into FIFO
-	       output [24:1] 	 waddr, // RAM address
+	       output [24:1]	 waddr, // RAM address
 	       output reg [1:0]  wrq, // Write request (min 4/8 bytes)
-	       input 		 wacc, // Data accepted (ready for next data)
+	       input		 wacc, // Data accepted (ready for next data)
 
 	       /* CPU control interface */
 	       output reg [31:0] cpu_rdata,
-	       input [31:0] 	 cpu_wdata,
-	       input 		 cpu_valid,
-	       input [3:0] 	 cpu_wstrb,
-	       input [1:0] 	 cpu_addr,
-	       output reg 	 irq
+	       input [31:0]	 cpu_wdata,
+	       input		 cpu_valid,
+	       input [3:0]	 cpu_wstrb,
+	       input [1:0]	 cpu_addr,
+	       output reg	 irq
 	       );
 
    reg [24:3] ramstart;

fpga/usb/usb.sv

@@ -0,0 +1,106 @@
+//
+// usb.sv
+//
+// For now, just instantiate a USB <-> serial bridge and attach it
+// to the output of the tty
+//
+
+module max80_usb (
+		  input  rst_n,
+		  input  clock48,
+		  
+		  output tty_rxd,
+		  input  tty_txd,
+
+		  inout  usb_dp,
+		  inout  usb_dn,
+		  output usb_pu	// driver for 1.5 kohm pullup
+		  );
+
+   //
+   // UTMI interface to PHY
+   //
+   wire [7:0] 		 utmi_data_out;
+   wire [1:0] 		 utmi_op_mode;
+   wire [1:0] 		 utmi_xcvrselect;
+   wire 		 utmi_termselect;
+   wire 		 utmi_dppulldown;
+   wire 		 utmi_dmpulldown;
+   wire [7:0] 		 utmi_data_in;
+   wire 		 utmi_txvalid;
+   wire 		 utmi_txready;
+   wire 		 utmi_rxvalid;
+   wire 		 utmi_rxactive;
+   wire 		 utmi_rxerror;
+   wire [1:0] 		 utmi_linestate;
+
+   //
+   // USB hardware interface to PHY
+   //
+   wire 		 usb_rx_rcv   = usb_dp & ~usb_dn;
+   wire 		 usb_rx_dp    = usb_dp;
+   wire 		 usb_rx_dn    = usb_dn;
+   wire 		 usb_tx_dp;
+   wire 		 usb_tx_dn;
+   wire 		 usb_tx_oen;
+   wire 		 usb_en;
+
+   assign usb_dp = ( rst_n & ~usb_tx_oen ) ? usb_tx_dp : 1'bz;
+   assign usb_dn = ( rst_n & ~usb_tx_oen ) ? usb_tx_dn : 1'bz;
+   assign usb_pu = ( rst_n & usb_en )      ? 1'b1 : 1'bz;
+
+   usb_fs_phy usb_phy (
+		       .clk_i ( clock48 ),
+		       .rst_i ( ~rst_n ),
+
+		       .utmi_data_out_i ( utmi_data_out ),
+		       .utmi_txvalid_i  ( utmi_txvalid ),
+		       .utmi_op_mode_i  ( utmi_op_mode ),
+		       .utmi_xcvrselect_i ( utmi_xcvrselect ),
+		       .utmi_termselect_i ( utmi_termselect ),
+		       .utmi_dppulldown_i ( utmi_dppulldown ),
+		       .utmi_dmpulldown_i ( utmi_dmpulldown ),
+
+		       .usb_rx_rcv_i     ( usb_rx_rcv ),
+		       .usb_rx_dp_i      ( usb_rx_dp ),
+		       .usb_rx_dn_i      ( usb_rx_dn ),
+		       .usb_reset_assert_i ( 1'b0 ),
+
+		       .utmi_data_in_o     ( utmi_data_in ),
+		       .utmi_txready_o     ( utmi_txready ),
+		       .utmi_rxvalid_o     ( utmi_rxvalid ),
+		       .utmi_rxactive_o    ( utmi_rxactive ),
+		       .utmi_rxerror_o     ( utmi_rxerror ),
+		       .utmi_linestate_o   ( utmi_linestate ),
+
+		       .usb_tx_dp_o        ( usb_tx_dp ),
+		       .usb_tx_dn_o        ( usb_tx_dn ),
+		       .usb_tx_oen_o       ( usb_tx_oen ),
+		       .usb_reset_detect_o ( ),
+		       .usb_en_o           ( usb_en )
+		       );
+   
+   usb_cdc_top #(.BAUDRATE(115200))
+   usb_serial (
+	       .clk_i             ( clock48 ),
+	       .rst_i             ( ~rst_n ),
+
+	       .utmi_data_out_o   ( utmi_data_out ),
+	       .utmi_txvalid_o    ( utmi_txvalid ),
+	       .utmi_op_mode_o    ( utmi_op_mode ),
+	       .utmi_xcvrselect_o ( utmi_xcvrselect ),
+	       .utmi_termselect_o ( utmi_termselect ),
+	       .utmi_dppulldown_o ( utmi_dppulldown ),
+	       .utmi_dmpulldown_o ( utmi_dmpulldown ),
+
+	       .utmi_data_in_i    ( utmi_data_in ),
+	       .utmi_txready_i    ( utmi_txready ),
+	       .utmi_rxvalid_i    ( utmi_rxvalid ),
+	       .utmi_rxactive_i   ( utmi_rxactive ),
+	       .utmi_rxerror_i    ( utmi_rxerror ),
+	       .utmi_linestate_i  ( utmi_linestate ),
+
+	       .tx_i ( tty_txd ),
+	       .rx_o ( tty_rxd )
+	       );
+endmodule // max80_usb

fpga/usb/usb_fs_phy/LICENSE

@@ -0,0 +1,504 @@
+                  GNU LESSER GENERAL PUBLIC LICENSE
+                       Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
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fpga/usb/usb_fs_phy/README.md

@@ -0,0 +1,114 @@
+### USB Full Speed PHY
+
+Github:   [http://github.com/ultraembedded/core_usb_fs_phy](https://github.com/ultraembedded/core_usb_fs_phy)
+
+This component implements the low level USB1.1 / FS / 12Mbit/s USB signalling (SOP,DATA,EOP) with the required bitstuffing.
+
+##### Features
+* UTMI PHY interface.
+* Connection to a transceiver (e.g. USB1T11A) or can drive the FPGA pins directly as USB D+/D-.
+
+##### Configuration / Requirements
+* Top: usb_fs_phy
+* Clock: clk_i - 48MHz
+* Reset: rst_i - Asynchronous, active high
+
+##### Testing
+Tested with various FPGA + USB based projects.
+
+##### FPGA Transceiver
+To avoid external components, you can drive the USB D+/D- pins directly from the FPGA fabric.
+The USB1.1 bit rate is low enough (12MHz) for this to be not too problematic with short cables!
+
+```
+module usb_fs_phy_wrapper
+(
+     input           clk_i
+    ,input           rst_i
+
+    ,input  [  7:0]  utmi_data_out_i
+    ,input           utmi_txvalid_i
+    ,input  [  1:0]  utmi_op_mode_i
+    ,input  [  1:0]  utmi_xcvrselect_i
+    ,input           utmi_termselect_i
+    ,input           utmi_dppulldown_i
+    ,input           utmi_dmpulldown_i
+    ,output [  7:0]  utmi_data_in_o
+    ,output          utmi_txready_o
+    ,output          utmi_rxvalid_o
+    ,output          utmi_rxactive_o
+    ,output          utmi_rxerror_o
+    ,output [  1:0]  utmi_linestate_o
+
+    // USB D+ / D-
+    ,inout          usb_dp_io
+    ,inout          usb_dn_io
+);
+
+wire           usb_pads_rx_rcv_w;
+wire           usb_pads_rx_dn_w;
+wire           usb_pads_rx_dp_w;
+wire           usb_pads_tx_dn_w;
+wire           usb_pads_tx_dp_w;
+wire           usb_pads_tx_oen_w;
+
+usb_transceiver u_usb_xcvr
+(
+    // Inputs
+     .usb_phy_tx_dp_i(usb_pads_tx_dp_w)
+    ,.usb_phy_tx_dn_i(usb_pads_tx_dn_w)
+    ,.usb_phy_tx_oen_i(usb_pads_tx_oen_w)
+    ,.mode_i(1'b1)
+
+    // Outputs
+    ,.usb_dp_io(usb_dp_io)
+    ,.usb_dn_io(usb_dn_io)
+    ,.usb_phy_rx_rcv_o(usb_pads_rx_rcv_w)
+    ,.usb_phy_rx_dp_o(usb_pads_rx_dp_w)
+    ,.usb_phy_rx_dn_o(usb_pads_rx_dn_w)
+);
+
+usb_fs_phy u_usb_phy
+(
+    // Inputs
+     .clk_i(clk_i)
+    ,.rst_i(rst_i)
+    ,.utmi_data_out_i(utmi_data_out_i)
+    ,.utmi_txvalid_i(utmi_txvalid_i)
+    ,.utmi_op_mode_i(utmi_op_mode_i)
+    ,.utmi_xcvrselect_i(utmi_xcvrselect_i)
+    ,.utmi_termselect_i(utmi_termselect_i)
+    ,.utmi_dppulldown_i(utmi_dppulldown_i)
+    ,.utmi_dmpulldown_i(utmi_dmpulldown_i)
+    ,.usb_rx_rcv_i(usb_pads_rx_rcv_w)
+    ,.usb_rx_dp_i(usb_pads_rx_dp_w)
+    ,.usb_rx_dn_i(usb_pads_rx_dn_w)
+    ,.usb_reset_assert_i(1'b0)
+
+    // Outputs
+    ,.utmi_data_in_o(utmi_data_in_o)
+    ,.utmi_txready_o(utmi_txready_o)
+    ,.utmi_rxvalid_o(utmi_rxvalid_o)
+    ,.utmi_rxactive_o(utmi_rxactive_o)
+    ,.utmi_rxerror_o(utmi_rxerror_o)
+    ,.utmi_linestate_o(utmi_linestate_o)
+    ,.usb_tx_dp_o(usb_pads_tx_dp_w)
+    ,.usb_tx_dn_o(usb_pads_tx_dn_w)
+    ,.usb_tx_oen_o(usb_pads_tx_oen_w)
+    ,.usb_reset_detect_o()
+    ,.usb_en_o()
+);
+
+endmodule
+```
+
+Example contraints;
+```
+set_property -dict { PACKAGE_PIN N4    IOSTANDARD LVCMOS33 } [get_ports { usb_dp_io }];
+set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { usb_dn_io }];
+set_property PULLUP TRUE [get_ports usb_dp_io]
+```
+
+##### References
+* [UTMI Specification](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/usb2-transceiver-macrocell-interface-specification.pdf)
+* [USB1T11A](http://www.mouser.com/ds/2/149/fairchild%20semiconductor_usb1t11a-320893.pdf)

fpga/usb/usb_fs_phy/src_v/usb_fs_phy.v

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+//-----------------------------------------------------------------
+//                     USB Full Speed (12mbps) Phy
+//                              V0.2
+//                        Ultra-Embedded.com
+//                          Copyright 2015
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module usb_fs_phy
+(
+    // Inputs
+     input           clk_i
+    ,input           rst_i
+    ,input  [  7:0]  utmi_data_out_i
+    ,input           utmi_txvalid_i
+    ,input  [  1:0]  utmi_op_mode_i
+    ,input  [  1:0]  utmi_xcvrselect_i
+    ,input           utmi_termselect_i
+    ,input           utmi_dppulldown_i
+    ,input           utmi_dmpulldown_i
+    ,input           usb_rx_rcv_i
+    ,input           usb_rx_dp_i
+    ,input           usb_rx_dn_i
+    ,input           usb_reset_assert_i
+
+    // Outputs
+    ,output [  7:0]  utmi_data_in_o
+    ,output          utmi_txready_o
+    ,output          utmi_rxvalid_o
+    ,output          utmi_rxactive_o
+    ,output          utmi_rxerror_o
+    ,output [  1:0]  utmi_linestate_o
+    ,output          usb_tx_dp_o
+    ,output          usb_tx_dn_o
+    ,output          usb_tx_oen_o
+    ,output          usb_reset_detect_o
+    ,output          usb_en_o
+);
+
+
+
+
+//-----------------------------------------------------------------
+// Wires / Registers
+//-----------------------------------------------------------------
+reg         rx_en_q;
+
+// Xilinx placement pragmas:
+//synthesis attribute IOB of out_dp_q is "TRUE"
+//synthesis attribute IOB of out_dn_q is "TRUE"
+reg         out_dp_q;
+reg         out_dn_q;
+
+wire        in_dp_w;
+wire        in_dn_w;
+wire        in_rx_w;
+
+wire        in_j_w;
+wire        in_k_w;
+wire        in_se0_w;
+wire        in_invalid_w;
+
+wire        sample_w;
+
+wire        bit_edge_w;
+wire        bit_transition_w;
+
+reg [2:0]   bit_count_q;
+reg [2:0]   ones_count_q;
+reg [7:0]   data_q;
+reg         send_eop_q;
+
+reg         sync_j_detected_q;
+
+wire        bit_stuff_bit_w;
+wire        next_is_bit_stuff_w;
+
+wire        usb_reset_assert_w = usb_reset_assert_i | 
+                                (utmi_xcvrselect_i == 2'b00 && 
+                                 utmi_termselect_i == 1'b0  && 
+                                 utmi_op_mode_i    == 2'b10 && 
+                                 utmi_dppulldown_i && 
+                                 utmi_dmpulldown_i);
+
+//-----------------------------------------------------------------
+// Resample async signals
+//-----------------------------------------------------------------
+reg         rx_dp_ms;
+reg         rx_dn_ms;
+reg         rxd_ms;
+
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    rx_dp_ms <= 1'b0;
+    rx_dn_ms <= 1'b0;
+    rxd_ms   <= 1'b0;
+end
+else
+begin
+    rx_dp_ms <= in_dp_w;
+    rx_dn_ms <= in_dn_w;
+    rxd_ms   <= in_rx_w;
+end
+
+//-----------------------------------------------------------------
+// Edge Detection
+//-----------------------------------------------------------------
+reg         rx_dp0_q;
+reg         rx_dn0_q;
+reg         rx_dp1_q;
+reg         rx_dn1_q;
+reg         rx_dp_q;
+reg         rx_dn_q;
+reg         rxd0_q;
+reg         rxd1_q;
+reg         rxd_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    rx_dp0_q    <= 1'b0;
+    rx_dn0_q    <= 1'b0;
+    rx_dp1_q    <= 1'b0;
+    rx_dn1_q    <= 1'b0;
+    rx_dp_q     <= 1'b0;
+    rx_dn_q     <= 1'b0;
+    rxd0_q      <= 1'b0;
+    rxd1_q      <= 1'b0;
+    rxd_q       <= 1'b0;
+end
+else
+begin
+    // Glitch free versions
+    if (rx_dp0_q & rx_dp1_q)
+        rx_dp_q     <= 1'b1;
+    else if (!rx_dp0_q & !rx_dp1_q)
+        rx_dp_q     <= 1'b0;
+
+    if (rx_dn0_q & rx_dn1_q)
+        rx_dn_q     <= 1'b1;
+    else if (!rx_dn0_q & !rx_dn1_q)
+        rx_dn_q     <= 1'b0;
+
+    if (rxd0_q & rxd1_q)
+        rxd_q     <= 1'b1;
+    else if (!rxd0_q & !rxd1_q)
+        rxd_q     <= 1'b0;
+
+    // Resyncs
+    rx_dp1_q    <= rx_dp0_q;
+    rx_dp0_q    <= rx_dp_ms;
+
+    rx_dn1_q    <= rx_dn0_q;
+    rx_dn0_q    <= rx_dn_ms;
+
+    rxd1_q      <= rxd0_q;
+    rxd0_q      <= rxd_ms;
+end
+
+// For Full Speed USB:
+// SE0 = D+ = 0 && D- = 0
+// J   = D+ = 1 && D- = 0
+// K   = D+ = 0 && D- = 1
+
+assign in_j_w       = in_se0_w ? 1'b0 :  rxd_q;
+assign in_k_w       = in_se0_w ? 1'b0 : ~rxd_q;
+assign in_se0_w     = (!rx_dp_q & !rx_dn_q);
+assign in_invalid_w = (rx_dp_q & rx_dn_q);
+
+// Line state matches tx outputs if drivers enabled
+assign utmi_linestate_o = usb_tx_oen_o ? {rx_dn_q, rx_dp_q} : {usb_tx_dn_o, usb_tx_dp_o};
+
+//-----------------------------------------------------------------
+// State Machine
+//-----------------------------------------------------------------
+localparam STATE_W              = 4;
+localparam STATE_IDLE           = 4'd0;
+localparam STATE_RX_DETECT      = 4'd1;
+localparam STATE_RX_SYNC_J      = 4'd2;
+localparam STATE_RX_SYNC_K      = 4'd3;
+localparam STATE_RX_ACTIVE      = 4'd4;
+localparam STATE_RX_EOP0        = 4'd5;
+localparam STATE_RX_EOP1        = 4'd6;
+localparam STATE_TX_SYNC        = 4'd7;
+localparam STATE_TX_ACTIVE      = 4'd8;
+localparam STATE_TX_EOP_STUFF   = 4'd9;
+localparam STATE_TX_EOP0        = 4'd10;
+localparam STATE_TX_EOP1        = 4'd11;
+localparam STATE_TX_EOP2        = 4'd12;
+localparam STATE_TX_RST         = 4'd13;
+
+// Current state
+reg [STATE_W-1:0] state_q;
+
+reg [STATE_W-1:0] next_state_r;
+always @ *
+begin
+    next_state_r = state_q;
+
+    case (state_q)
+    //-----------------------------------------
+    // STATE_IDLE
+    //-----------------------------------------
+    STATE_IDLE :
+    begin
+        if (in_k_w)
+            next_state_r    = STATE_RX_DETECT;
+        else if (utmi_txvalid_i)
+            next_state_r    = STATE_TX_SYNC;
+        else if (usb_reset_assert_w)
+            next_state_r    = STATE_TX_RST;
+    end
+    //-----------------------------------------
+    // STATE_RX_DETECT
+    //-----------------------------------------
+    STATE_RX_DETECT :
+    begin
+        if (in_k_w && sample_w)
+            next_state_r    = STATE_RX_SYNC_K;
+        else if (sample_w)
+            next_state_r    = STATE_IDLE;
+    end
+    //-----------------------------------------
+    // STATE_RX_SYNC_J
+    //-----------------------------------------
+    STATE_RX_SYNC_J :
+    begin
+        if (in_k_w && sample_w)
+            next_state_r    = STATE_RX_SYNC_K;
+        // K glitch followed by multiple J's - return to idle
+        else if ((bit_count_q == 3'd1) && sample_w)
+            next_state_r    = STATE_IDLE;
+    end
+    //-----------------------------------------
+    // STATE_RX_SYNC_K
+    //-----------------------------------------
+    STATE_RX_SYNC_K :
+    begin
+        // End of SYNC field ends with 2 K's
+        // Must have seen at least 1 J state first!
+        if (sync_j_detected_q && in_k_w && sample_w)
+            next_state_r    = STATE_RX_ACTIVE;
+        // No J detected since IDLE, must be an error!
+        else if (!sync_j_detected_q && in_k_w && sample_w)
+            next_state_r    = STATE_IDLE;
+        else if (in_j_w && sample_w)
+            next_state_r    = STATE_RX_SYNC_J;
+    end
+    //-----------------------------------------
+    // STATE_RX_ACTIVE
+    //-----------------------------------------
+    STATE_RX_ACTIVE :
+    begin
+        if (in_se0_w && sample_w)
+            next_state_r    = STATE_RX_EOP0;
+        // Error!
+        else if (in_invalid_w && sample_w)
+            next_state_r    = STATE_IDLE;
+    end
+    //-----------------------------------------
+    // STATE_RX_EOP0
+    //-----------------------------------------
+    STATE_RX_EOP0 :
+    begin
+        if (in_se0_w && sample_w)
+            next_state_r    = STATE_RX_EOP1;
+        // Error!
+        else if (sample_w)
+            next_state_r    = STATE_IDLE;
+    end
+    //-----------------------------------------
+    // STATE_RX_EOP1
+    //-----------------------------------------
+    STATE_RX_EOP1 :
+    begin
+        // Return to idle
+        if (in_j_w && sample_w)
+            next_state_r    = STATE_IDLE;
+        // Error!
+        else if (sample_w)
+            next_state_r    = STATE_IDLE;
+    end
+    //-----------------------------------------
+    // STATE_TX_SYNC
+    //-----------------------------------------
+    STATE_TX_SYNC :
+    begin
+        if (bit_count_q == 3'd7 && sample_w)
+            next_state_r    = STATE_TX_ACTIVE;
+    end
+    //-----------------------------------------
+    // STATE_TX_ACTIVE
+    //-----------------------------------------
+    STATE_TX_ACTIVE :
+    begin
+        if (bit_count_q == 3'd7 && sample_w && (!utmi_txvalid_i || send_eop_q) && !bit_stuff_bit_w)
+        begin
+            // Bit stuff required at end of packet?
+            if (next_is_bit_stuff_w)
+                next_state_r    = STATE_TX_EOP_STUFF;
+            else
+                next_state_r    = STATE_TX_EOP0;
+        end
+    end
+    //-----------------------------------------
+    // STATE_TX_EOP_STUFF
+    //-----------------------------------------
+    STATE_TX_EOP_STUFF :
+    begin
+        if (sample_w)
+            next_state_r    = STATE_TX_EOP0;
+    end
+    //-----------------------------------------
+    // STATE_TX_EOP0
+    //-----------------------------------------
+    STATE_TX_EOP0 :
+    begin
+        if (sample_w)
+            next_state_r    = STATE_TX_EOP1;
+    end
+    //-----------------------------------------
+    // STATE_TX_EOP1
+    //-----------------------------------------
+    STATE_TX_EOP1 :
+    begin
+        if (sample_w)
+            next_state_r    = STATE_TX_EOP2;
+    end
+    //-----------------------------------------
+    // STATE_TX_EOP2
+    //-----------------------------------------
+    STATE_TX_EOP2 :
+    begin
+        if (sample_w)
+            next_state_r    = STATE_IDLE;
+    end
+    //-----------------------------------------
+    // STATE_TX_RST
+    //-----------------------------------------
+    STATE_TX_RST :
+    begin
+        if (!usb_reset_assert_w)
+            next_state_r    = STATE_IDLE;
+    end
+    default:
+        ;
+   endcase
+end
+
+// Update state
+always @ (posedge rst_i or posedge clk_i)
+if (rst_i)
+    state_q   <= STATE_IDLE;
+else
+    state_q   <= next_state_r;
+
+//-----------------------------------------------------------------
+// SYNC detect
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    sync_j_detected_q  <= 1'b0;
+// Reset sync detect state in IDLE
+else if (state_q == STATE_IDLE)
+    sync_j_detected_q  <= 1'b0;
+// At least one J detected
+else if (state_q == STATE_RX_SYNC_J)
+    sync_j_detected_q  <= 1'b1;
+
+//-----------------------------------------------------------------
+// Rx Error Detection
+//-----------------------------------------------------------------
+reg rx_error_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rx_error_q  <= 1'b0;
+// Rx bit stuffing error
+else if (ones_count_q == 3'd7)
+    rx_error_q  <= 1'b1;
+// Invalid line state detection
+else if (in_invalid_w && sample_w)
+    rx_error_q  <= 1'b1;
+// Detect invalid SYNC sequence
+else if ((state_q == STATE_RX_SYNC_K) && !sync_j_detected_q && in_k_w && sample_w)
+    rx_error_q  <= 1'b1;
+else
+    rx_error_q  <= 1'b0;
+
+assign utmi_rxerror_o = rx_error_q;
+
+//-----------------------------------------------------------------
+// Edge Detector
+//-----------------------------------------------------------------
+reg rxd_last_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rxd_last_q  <= 1'b0;
+else
+    rxd_last_q  <= in_j_w;
+
+assign bit_edge_w = rxd_last_q ^ in_j_w;
+
+//-----------------------------------------------------------------
+// Sample Timer
+//-----------------------------------------------------------------
+reg [1:0] sample_cnt_q;
+reg       adjust_delayed_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    sample_cnt_q        <= 2'd0;
+    adjust_delayed_q    <= 1'b0;
+end
+// Delayed adjustment
+else if (adjust_delayed_q)
+    adjust_delayed_q    <= 1'b0;
+else if (bit_edge_w && (sample_cnt_q != 2'd0) && (state_q < STATE_TX_SYNC))
+    sample_cnt_q        <= 2'd0;
+// Can't adjust sampling point now?
+else if (bit_edge_w && (sample_cnt_q == 2'd0) && (state_q < STATE_TX_SYNC))
+begin
+    // Want to reset sampling point but need to delay adjustment by 1 cycle!
+    adjust_delayed_q    <= 1'b1;
+    sample_cnt_q        <= sample_cnt_q + 2'd1;
+end
+else
+    sample_cnt_q        <= sample_cnt_q + 2'd1;
+
+assign sample_w = (sample_cnt_q == 2'd0);
+
+//-----------------------------------------------------------------
+// NRZI Receiver
+//-----------------------------------------------------------------
+reg rxd_last_j_q;
+
+// NRZI:
+// 0 = transition between J & K
+// 1 = same state
+// After 6 consequitive 1's, a 0 is inserted to maintain the transitions
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rxd_last_j_q  <= 1'b0;
+else if ((state_q == STATE_IDLE) || sample_w)
+    rxd_last_j_q  <= in_j_w;
+
+assign bit_transition_w = sample_w ? rxd_last_j_q ^ in_j_w : 1'b0;
+
+//-----------------------------------------------------------------
+// Bit Counters
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    ones_count_q <= 3'd1;
+// The packet starts with a double K (no transition)
+else if (state_q == STATE_IDLE)
+    ones_count_q <= 3'd1;
+// Rx
+else if ((state_q == STATE_RX_ACTIVE) && sample_w)
+begin
+    if (bit_transition_w)
+        ones_count_q <= 3'b0;
+    else
+        ones_count_q <= ones_count_q + 3'd1;
+end
+// Tx
+else if ((state_q == STATE_TX_ACTIVE) && sample_w)
+begin
+    // Toggle output data
+    if (!data_q[0] || bit_stuff_bit_w)
+        ones_count_q <= 3'b0;
+    else
+        ones_count_q <= ones_count_q + 3'd1;
+end
+
+assign bit_stuff_bit_w     = (ones_count_q == 3'd6);
+assign next_is_bit_stuff_w = (ones_count_q == 3'd5) && !bit_transition_w;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    bit_count_q <= 3'b0;
+else if ((state_q == STATE_IDLE) || (state_q == STATE_RX_SYNC_K))
+    bit_count_q <= 3'b0;
+else if ((state_q == STATE_RX_ACTIVE || state_q == STATE_TX_ACTIVE) && sample_w && !bit_stuff_bit_w)
+    bit_count_q <= bit_count_q + 3'd1;
+else if (((state_q == STATE_TX_SYNC) || (state_q == STATE_RX_SYNC_J)) && sample_w)
+    bit_count_q <= bit_count_q + 3'd1;
+
+//-----------------------------------------------------------------
+// Shift register
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    data_q  <= 8'b0;
+// Pre-load shift register with SYNC word
+else if (state_q == STATE_IDLE)
+    data_q  <= 8'b00101010;
+else if ((state_q == STATE_RX_ACTIVE) && sample_w && !bit_stuff_bit_w)
+    data_q  <= {~bit_transition_w, data_q[7:1]};
+else if ((state_q == STATE_TX_SYNC) && sample_w)
+begin
+    if (bit_count_q == 3'd7)
+        data_q  <= utmi_data_out_i;
+    else
+        data_q  <= {~bit_transition_w, data_q[7:1]};
+end    
+else if ((state_q == STATE_TX_ACTIVE) && sample_w && !bit_stuff_bit_w)
+begin
+    if (bit_count_q == 3'd7)
+        data_q  <= utmi_data_out_i;
+    else
+        data_q  <= {~bit_transition_w, data_q[7:1]};
+end
+
+// Receive active (SYNC recieved)
+assign utmi_rxactive_o = (state_q == STATE_RX_ACTIVE);
+
+assign utmi_data_in_o  = data_q;
+
+//-----------------------------------------------------------------
+// Rx Ready
+//-----------------------------------------------------------------
+reg rx_ready_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rx_ready_q <= 1'b0;
+else if ((state_q == STATE_RX_ACTIVE) && sample_w && (bit_count_q == 3'd7) && !bit_stuff_bit_w)
+    rx_ready_q <= 1'b1;
+else
+    rx_ready_q <= 1'b0;
+
+assign utmi_rxvalid_o  = rx_ready_q;
+
+//-----------------------------------------------------------------
+// Tx Ready
+//-----------------------------------------------------------------
+reg tx_ready_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    tx_ready_q <= 1'b0;
+else if ((state_q == STATE_TX_SYNC) && sample_w && (bit_count_q == 3'd7))
+    tx_ready_q <= 1'b1;
+else if ((state_q == STATE_TX_ACTIVE) && sample_w && !bit_stuff_bit_w && (bit_count_q == 3'd7) && !send_eop_q)
+    tx_ready_q <= 1'b1;
+else
+    tx_ready_q <= 1'b0;
+
+assign utmi_txready_o  = tx_ready_q;
+
+//-----------------------------------------------------------------
+// EOP pending
+//-----------------------------------------------------------------
+always @ (posedge rst_i or posedge clk_i)
+if (rst_i)
+    send_eop_q  <= 1'b0;
+else if ((state_q == STATE_TX_ACTIVE) && !utmi_txvalid_i)
+    send_eop_q  <= 1'b1;
+else if (state_q == STATE_TX_EOP0)
+    send_eop_q  <= 1'b0;
+
+//-----------------------------------------------------------------
+// Tx
+//-----------------------------------------------------------------
+wire out_bit_w = sample_w ? data_q[0] : 1'bz;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    out_dp_q <= 1'b0;
+    out_dn_q <= 1'b0;
+    rx_en_q  <= 1'b1;
+end
+else if (state_q == STATE_IDLE)
+begin
+    // IDLE
+    out_dp_q <= 1'b1;
+    out_dn_q <= 1'b0;
+
+    if (utmi_txvalid_i || usb_reset_assert_w)
+        rx_en_q <= 1'b0;
+    else
+        rx_en_q <= 1'b1;
+end
+else if ((state_q == STATE_TX_SYNC) && sample_w)
+begin
+    out_dp_q <= data_q[0];
+    out_dn_q <= ~data_q[0];
+end
+else if ((state_q == STATE_TX_ACTIVE || state_q == STATE_TX_EOP_STUFF) && sample_w)
+begin
+    // 0 = toggle, 1 = hold
+    if (!data_q[0] || bit_stuff_bit_w)
+    begin
+        out_dp_q <= ~out_dp_q;
+        out_dn_q <= ~out_dn_q;
+    end
+end
+else if ((state_q == STATE_TX_EOP0 || state_q == STATE_TX_EOP1) && sample_w)
+begin
+    // SE0
+    out_dp_q <= 1'b0;
+    out_dn_q <= 1'b0;
+end
+else if ((state_q == STATE_TX_EOP2) && sample_w)
+begin
+    // IDLE
+    out_dp_q <= 1'b1;
+    out_dn_q <= 1'b0;
+
+    // Set bus to input
+    rx_en_q <= 1'b1;
+end
+else if (state_q == STATE_TX_RST)
+begin
+    // SE0
+    out_dp_q <= 1'b0;
+    out_dn_q <= 1'b0;
+end
+
+//-----------------------------------------------------------------
+// Reset detection
+//-----------------------------------------------------------------
+reg [6:0] se0_cnt_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    se0_cnt_q <= 7'b0;
+else if (in_se0_w)
+begin
+    if (se0_cnt_q != 7'd127)
+        se0_cnt_q <= se0_cnt_q + 7'd1;
+end    
+else
+    se0_cnt_q <= 7'b0;
+
+assign usb_reset_detect_o = (se0_cnt_q == 7'd127);
+
+//-----------------------------------------------------------------
+// Transceiver Interface
+//-----------------------------------------------------------------
+// Tx output enable (active low)
+assign usb_tx_oen_o = rx_en_q;
+
+// Tx +/-
+assign usb_tx_dp_o  = out_dp_q;
+assign usb_tx_dn_o  = out_dn_q;
+
+// Receive D+/D-
+assign in_dp_w = usb_rx_dp_i;
+assign in_dn_w = usb_rx_dn_i;
+
+// Receive data
+assign in_rx_w = usb_rx_rcv_i;
+
+// USB device pull-up enable
+assign usb_en_o = utmi_termselect_i;
+
+
+endmodule

fpga/usb/usb_fs_phy/src_v/usb_transceiver.v

@@ -0,0 +1,162 @@
+//-----------------------------------------------------------------
+//                     USB Full Speed (12mbps) Phy
+//                              V0.2
+//                        Ultra-Embedded.com
+//                          Copyright 2015
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module usb_transceiver
+(
+    // Inputs
+     input           usb_phy_tx_dp_i
+    ,input           usb_phy_tx_dn_i
+    ,input           usb_phy_tx_oen_i
+    ,input           mode_i
+
+    // Outputs
+    ,inout          usb_dp_io
+    ,inout          usb_dn_io
+    ,output          usb_phy_rx_rcv_o
+    ,output          usb_phy_rx_dp_o
+    ,output          usb_phy_rx_dn_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Module: usb_transceiver
+// Emulate standard USB PHY interface and produce a D+/D- outputs.
+// Allows direct connection of USB port to FPGA.
+// Limitations:
+// As no differential amplifier present, no common mode noise
+// rejection occurs.
+// Unlikely to work well with longer connections!
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// Wires
+//-----------------------------------------------------------------
+reg out_dp;
+reg out_dn;
+
+//-----------------------------------------------------------------
+// Assignments
+//-----------------------------------------------------------------
+
+// D+/D- Tristate buffers
+assign usb_dp_io = (usb_phy_tx_oen_i == 1'b0) ? out_dp : 1'bz;
+assign usb_dn_io = (usb_phy_tx_oen_i == 1'b0) ? out_dn : 1'bz;
+
+// Receive D+/D-
+assign usb_phy_rx_dp_o = usb_dp_io;
+assign usb_phy_rx_dn_o = usb_dn_io;
+
+// Receive output
+assign usb_phy_rx_rcv_o = (usb_dp_io == 1'b1 && usb_dn_io == 1'b0) ? 1'b1 : 1'b0;
+
+// PHY Transmit Mode:
+// When phy_tx_mode_i is '0' the outputs are encoded as:
+//     vmo_i, vpo_i
+//      0    0    Differential Logic '0'
+//      0    1    Differential Logic '1'
+//      1    0    Single Ended '0'
+//      1    1    Single Ended '0'
+// When phy_tx_mode_i is '1' the outputs are encoded as:
+//     vmo_i, vpo_i
+//      0    0    Single Ended '0'
+//      0    1    Differential Logic '1'
+//      1    0    Differential Logic '0'
+//      1    1    Illegal State
+always @ (mode_i or usb_phy_tx_dp_i or usb_phy_tx_dn_i)
+begin : MUX
+ case(mode_i)
+    1'b0:
+    begin
+        if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b0)
+        begin
+            // Logic "0"
+            out_dp = 1'b0;
+            out_dn = 1'b1;
+        end
+        else if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b1)
+        begin
+            // SE0 (both low)
+            out_dp = 1'b0;
+            out_dn = 1'b0;
+        end
+        else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b0)
+        begin
+            // Logic "1"
+            out_dp = 1'b1;
+            out_dn = 1'b0;
+        end
+        else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b1)
+        begin
+            // SE0 (both low)
+            out_dp = 1'b0;
+            out_dn = 1'b0;
+        end
+    end
+    1'b1 :
+    begin
+        if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b0)
+        begin
+            // SE0 (both low)
+            out_dp = 1'b0;
+            out_dn = 1'b0;
+        end
+        else if (usb_phy_tx_dp_i == 1'b0 && usb_phy_tx_dn_i == 1'b1)
+        begin
+            // Logic "0"
+            out_dp = 1'b0;
+            out_dn = 1'b1;
+        end
+        else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b0)
+        begin
+            // Logic "1"
+            out_dp = 1'b1;
+            out_dn = 1'b0;
+        end
+        else if (usb_phy_tx_dp_i == 1'b1 && usb_phy_tx_dn_i == 1'b1)
+        begin
+            // Illegal
+            out_dp = 1'b1;
+            out_dn = 1'b1;
+        end
+    end
+ endcase
+end
+
+
+endmodule

fpga/usb/usb_serial/README.md

@@ -0,0 +1,130 @@
+### USB Serial Port Device (USB-CDC)
+
+Github:   [https://github.com/ultraembedded/core_usb_uart](https://github.com/ultraembedded/core_usb_uart)
+
+This component is a simple USB Peripheral Interface (Device) implementation which enumerates as either a high-speed (480Mbit/s) or full-speed (12Mbit/s) CDC-ACM device.
+
+This IP acts as a USB to serial port (UART) converter which can be used to add a UART to a FPGA which has a ULPI interface.
+
+##### Features
+* High or Full speed USB CDC device.
+* Enumeration in hardware - no SW intervention required.
+* ULPI interface (suitable for connection to a ULPI PHY - e.g. Microchip USB3300)
+* Fixed baud rate (param) Rx, Tx pins.
+
+##### Example instantiation (Xilinx)
+```
+module usb_serial
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+    parameter BAUDRATE         = 1000000
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+      output          uart_rx_o
+    , input           uart_tx_i
+
+    // ULPI Interface
+    , output          ulpi_reset_o
+    , inout [7:0]     ulpi_data_io
+    , output          ulpi_stp_o
+    , input           ulpi_nxt_i
+    , input           ulpi_dir_i
+    , input           ulpi_clk60_i
+);
+
+// USB clock / reset
+wire usb_clk_w;
+wire usb_rst_w;
+
+wire clk_bufg_w;
+IBUF u_ibuf ( .I(ulpi_clk60_i), .O(clk_bufg_w) );
+BUFG u_bufg ( .I(clk_bufg_w),   .O(usb_clk_w) );
+
+reg [3:0] count_q = 4'b0;
+reg       rst_q   = 1'b1;
+
+always @(posedge usb_clk_w) 
+if (count_q != 4'hF)
+    count_q <= count_q + 4'd1;
+else
+    rst_q <= 1'b0;
+
+assign usb_rst_w = rst_q;
+
+// ULPI Buffers
+wire [7:0] ulpi_out_w;
+wire [7:0] ulpi_in_w;
+wire       ulpi_stp_w;
+
+genvar i;
+generate  
+for (i=0; i < 8; i=i+1)  
+begin: gen_buf
+    IOBUF 
+    #(
+        .DRIVE(12),
+        .IOSTANDARD("DEFAULT"),
+        .SLEW("FAST")
+    )
+    IOBUF_inst
+    (
+        .T(ulpi_dir_i),
+        .I(ulpi_out_w[i]),
+        .O(ulpi_in_w[i]),
+        .IO(ulpi_data_io[i])
+    );
+end  
+endgenerate  
+
+OBUF 
+#(
+    .DRIVE(12),
+    .IOSTANDARD("DEFAULT"),
+    .SLEW("FAST")
+)
+OBUF_stp
+(
+    .I(ulpi_stp_w),
+    .O(ulpi_stp_o)
+);
+
+// USB Core
+usb_cdc_top
+#( .BAUDRATE(BAUDRATE) )
+u_usb
+(
+     .clk_i(usb_clk_w)
+    ,.rst_i(usb_rst_w)
+
+    // ULPI
+    ,.ulpi_data_out_i(ulpi_in_w)
+    ,.ulpi_dir_i(ulpi_dir_i)
+    ,.ulpi_nxt_i(ulpi_nxt_i)
+    ,.ulpi_data_in_o(ulpi_out_w)
+    ,.ulpi_stp_o(ulpi_stp_w)
+
+    ,.tx_i(uart_tx_i)
+    ,.rx_o(uart_rx_o)
+);
+
+assign ulpi_reset_o = 1'b0;
+
+endmodule
+```
+
+##### Limitations
+* Really basic USB-CDC class device implementation, will ignore encap, line state and line coding change requests!
+* USB suspend/resume will not work correctly.
+
+##### Testing
+Verified under simulation then tested on FPGA against Linux, Windows and MAC OS-X.
+
+##### References
+* [USB 2.0 Specification](https://usb.org/developers/docs/usb20_docs)
+* [ULPI Specification](https://www.sparkfun.com/datasheets/Components/SMD/ULPI_v1_1.pdf)
+* [USB Made Simple](http://www.usbmadesimple.co.uk/)

fpga/usb/usb_serial/src_v/ulpi_wrapper.v

@@ -0,0 +1,444 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module ulpi_wrapper
+(
+    // Inputs
+     input           ulpi_clk60_i
+    ,input           ulpi_rst_i
+    ,input  [  7:0]  ulpi_data_out_i
+    ,input           ulpi_dir_i
+    ,input           ulpi_nxt_i
+    ,input  [  7:0]  utmi_data_out_i
+    ,input           utmi_txvalid_i
+    ,input  [  1:0]  utmi_op_mode_i
+    ,input  [  1:0]  utmi_xcvrselect_i
+    ,input           utmi_termselect_i
+    ,input           utmi_dppulldown_i
+    ,input           utmi_dmpulldown_i
+
+    // Outputs
+    ,output [  7:0]  ulpi_data_in_o
+    ,output          ulpi_stp_o
+    ,output [  7:0]  utmi_data_in_o
+    ,output          utmi_txready_o
+    ,output          utmi_rxvalid_o
+    ,output          utmi_rxactive_o
+    ,output          utmi_rxerror_o
+    ,output [  1:0]  utmi_linestate_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Module: UTMI+ to ULPI Wrapper
+//
+// Description:
+//   - Converts from UTMI interface to reduced pin count ULPI.
+//   - No support for low power mode.
+//   - I/O synchronous to 60MHz ULPI clock input (from PHY)
+//   - Tested against SMSC/Microchip USB3300 in device mode.
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+// States
+//-----------------------------------------------------------------
+localparam STATE_W          = 2;
+localparam STATE_IDLE       = 2'd0;
+localparam STATE_CMD        = 2'd1;
+localparam STATE_DATA       = 2'd2;
+localparam STATE_REG        = 2'd3;
+
+reg [STATE_W-1:0]   state_q;
+
+//-----------------------------------------------------------------
+// Local Params
+//-----------------------------------------------------------------
+localparam REG_FUNC_CTRL = 8'h84;
+localparam REG_OTG_CTRL  = 8'h8a;
+localparam REG_TRANSMIT  = 8'h40;
+localparam REG_WRITE     = 8'h80;
+localparam REG_READ      = 8'hC0;
+
+//-----------------------------------------------------------------
+// UTMI Mode Select
+//-----------------------------------------------------------------
+reg         mode_update_q;
+reg [1:0]   xcvrselect_q;
+reg         termselect_q;
+reg [1:0]   opmode_q;
+reg         phy_reset_q;
+reg         mode_write_q;
+
+// Detect register write completion
+wire mode_complete_w = (state_q == STATE_REG &&
+                        mode_write_q         && 
+                        ulpi_nxt_i           && 
+                        !ulpi_dir_i);           // Not interrupted by a Rx
+
+always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
+if (ulpi_rst_i)
+begin
+    mode_update_q   <= 1'b0;
+    xcvrselect_q    <= 2'b0;
+    termselect_q    <= 1'b0;
+    opmode_q        <= 2'b11;
+    phy_reset_q     <= 1'b1;
+end
+else
+begin
+    xcvrselect_q    <= utmi_xcvrselect_i;
+    termselect_q    <= utmi_termselect_i;
+    opmode_q        <= utmi_op_mode_i;
+
+    if (mode_update_q && mode_complete_w)
+    begin
+        mode_update_q <= 1'b0;
+        phy_reset_q   <= 1'b0;
+    end
+    else if (opmode_q     != utmi_op_mode_i     ||
+             termselect_q != utmi_termselect_i ||
+             xcvrselect_q != utmi_xcvrselect_i)
+        mode_update_q <= 1'b1;
+end
+
+//-----------------------------------------------------------------
+// UTMI OTG Control
+//-----------------------------------------------------------------
+reg otg_update_q;
+reg dppulldown_q;
+reg dmpulldown_q;
+reg otg_write_q;
+
+// Detect register write completion
+wire otg_complete_w  = (state_q == STATE_REG &&
+                        otg_write_q         && 
+                        ulpi_nxt_i           && 
+                        !ulpi_dir_i);           // Not interrupted by a Rx
+
+always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
+if (ulpi_rst_i)
+begin
+    otg_update_q    <= 1'b0;
+    dppulldown_q    <= 1'b1;
+    dmpulldown_q    <= 1'b1;
+end
+else
+begin
+    dppulldown_q    <= utmi_dppulldown_i;
+    dmpulldown_q    <= utmi_dmpulldown_i;
+
+    if (otg_update_q && otg_complete_w)
+        otg_update_q <= 1'b0;
+    else if (dppulldown_q != utmi_dppulldown_i ||
+             dmpulldown_q != utmi_dmpulldown_i)
+        otg_update_q <= 1'b1;
+end
+
+//-----------------------------------------------------------------
+// Bus turnaround detect
+//-----------------------------------------------------------------
+reg ulpi_dir_q;
+
+always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
+if (ulpi_rst_i)
+    ulpi_dir_q <= 1'b0;
+else
+    ulpi_dir_q <= ulpi_dir_i;
+
+wire turnaround_w = ulpi_dir_q ^ ulpi_dir_i;
+
+//-----------------------------------------------------------------
+// Rx - Tx delay
+//-----------------------------------------------------------------
+localparam TX_DELAY_W       = 3;
+localparam TX_START_DELAY   = 3'd7;
+
+reg [TX_DELAY_W-1:0] tx_delay_q;
+
+always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
+if (ulpi_rst_i)
+    tx_delay_q <= {TX_DELAY_W{1'b0}};
+else if (utmi_rxactive_o)
+    tx_delay_q <= TX_START_DELAY;
+else if (tx_delay_q != {TX_DELAY_W{1'b0}})
+    tx_delay_q <= tx_delay_q - 1;
+
+wire tx_delay_complete_w = (tx_delay_q == {TX_DELAY_W{1'b0}});
+
+//-----------------------------------------------------------------
+// Tx Buffer - decouple UTMI Tx from PHY I/O
+//-----------------------------------------------------------------
+reg [7:0] tx_buffer_q[0:1];
+reg       tx_valid_q[0:1];
+reg       tx_wr_idx_q;
+reg       tx_rd_idx_q;
+
+wire      utmi_tx_ready_w;
+wire      utmi_tx_accept_w;
+
+always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
+if (ulpi_rst_i)
+begin
+    tx_buffer_q[0] <= 8'b0;
+    tx_buffer_q[1] <= 8'b0;
+    tx_valid_q[0]  <= 1'b0;
+    tx_valid_q[1]  <= 1'b0;
+    tx_wr_idx_q    <= 1'b0;
+    tx_rd_idx_q    <= 1'b0;
+end    
+else
+begin
+    // Push
+    if (utmi_txvalid_i && utmi_txready_o)
+    begin
+        tx_buffer_q[tx_wr_idx_q] <= utmi_data_out_i;
+        tx_valid_q[tx_wr_idx_q]  <= 1'b1;
+
+        tx_wr_idx_q <= tx_wr_idx_q + 1'b1;
+    end
+
+    // Pop
+    if (utmi_tx_ready_w && utmi_tx_accept_w)
+    begin
+        tx_valid_q[tx_rd_idx_q]  <= 1'b0;
+        tx_rd_idx_q <= tx_rd_idx_q + 1'b1;
+    end
+end
+
+// Tx buffer space (only accept after Rx->Tx turnaround delay)
+assign utmi_txready_o  = ~tx_valid_q[tx_wr_idx_q] & tx_delay_complete_w;
+
+assign utmi_tx_ready_w = tx_valid_q[tx_rd_idx_q];
+
+wire [7:0] utmi_tx_data_w = tx_buffer_q[tx_rd_idx_q];
+
+//-----------------------------------------------------------------
+// Implementation
+//-----------------------------------------------------------------
+
+// Xilinx placement pragmas:
+//synthesis attribute IOB of ulpi_data_q is "TRUE"
+//synthesis attribute IOB of ulpi_stp_q is "TRUE"
+
+reg [7:0]           ulpi_data_q;
+reg                 ulpi_stp_q;
+reg [7:0]           data_q;
+
+reg                 utmi_rxvalid_q;
+reg                 utmi_rxerror_q;
+reg                 utmi_rxactive_q;
+reg [1:0]           utmi_linestate_q;
+reg [7:0]           utmi_data_q;
+
+always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
+if (ulpi_rst_i)
+begin
+    state_q             <= STATE_IDLE;
+    ulpi_data_q         <= 8'b0;
+    data_q              <= 8'b0;
+    ulpi_stp_q          <= 1'b1;
+
+    utmi_rxvalid_q      <= 1'b0;
+    utmi_rxerror_q      <= 1'b0;
+    utmi_rxactive_q     <= 1'b0;
+    utmi_linestate_q    <= 2'b0;
+    utmi_data_q         <= 8'b0;
+
+    mode_write_q        <= 1'b0;
+    otg_write_q         <= 1'b0;
+end
+else
+begin
+    ulpi_stp_q          <= 1'b0;
+    utmi_rxvalid_q      <= 1'b0;
+
+    // Turnaround: Input + NXT - set RX_ACTIVE
+    if (turnaround_w && ulpi_dir_i && ulpi_nxt_i)
+    begin
+        utmi_rxactive_q <= 1'b1;
+
+        // Register write - abort
+        if (state_q == STATE_REG)
+        begin
+            state_q       <= STATE_IDLE;
+            ulpi_data_q   <= 8'b0;  // IDLE
+        end
+    end
+    // Turnaround: Input -> Output - reset RX_ACTIVE
+    else if (turnaround_w && !ulpi_dir_i)
+    begin
+        utmi_rxactive_q <= 1'b0;
+
+        // Register write - abort
+        if (state_q == STATE_REG)
+        begin
+            state_q       <= STATE_IDLE;
+            ulpi_data_q   <= 8'b0;  // IDLE
+        end
+    end
+    // Non-turnaround cycle
+    else if (!turnaround_w)
+    begin
+        //-----------------------------------------------------------------
+        // Input: RX_CMD (status)
+        //-----------------------------------------------------------------
+        if (ulpi_dir_i && !ulpi_nxt_i)
+        begin
+            // Phy status
+            utmi_linestate_q <= ulpi_data_out_i[1:0];
+
+            case (ulpi_data_out_i[5:4])
+            2'b00:
+            begin
+                utmi_rxactive_q <= 1'b0;
+                utmi_rxerror_q  <= 1'b0;
+            end
+            2'b01: 
+            begin
+                utmi_rxactive_q <= 1'b1;
+                utmi_rxerror_q  <= 1'b0;
+            end
+            2'b11:
+            begin
+                utmi_rxactive_q <= 1'b1;
+                utmi_rxerror_q  <= 1'b1;
+            end
+            default:
+                ; // HOST_DISCONNECTED
+            endcase
+        end
+        //-----------------------------------------------------------------
+        // Input: RX_DATA
+        //-----------------------------------------------------------------
+        else if (ulpi_dir_i && ulpi_nxt_i)
+        begin
+            utmi_rxvalid_q  <= 1'b1;
+            utmi_data_q     <= ulpi_data_out_i;
+        end
+        //-----------------------------------------------------------------
+        // Output
+        //-----------------------------------------------------------------
+        else if (!ulpi_dir_i)
+        begin        
+            // IDLE: Pending mode update
+            if ((state_q == STATE_IDLE) && mode_update_q)
+            begin
+                data_q        <= {1'b0, 1'b1, phy_reset_q, opmode_q, termselect_q, xcvrselect_q};
+                ulpi_data_q   <= REG_FUNC_CTRL;
+
+                otg_write_q   <= 1'b0;
+                mode_write_q  <= 1'b1;
+
+                state_q       <= STATE_CMD;
+            end
+            // IDLE: Pending OTG control update
+            else if ((state_q == STATE_IDLE) && otg_update_q)
+            begin
+                data_q        <= {5'b0, dmpulldown_q, dppulldown_q, 1'b0};
+                ulpi_data_q   <= REG_OTG_CTRL;
+
+                otg_write_q   <= 1'b1;
+                mode_write_q  <= 1'b0;
+
+                state_q       <= STATE_CMD;
+            end
+            // IDLE: Pending transmit
+            else if ((state_q == STATE_IDLE) && utmi_tx_ready_w)
+            begin
+                ulpi_data_q <= REG_TRANSMIT | {4'b0, utmi_tx_data_w[3:0]};
+                state_q     <= STATE_DATA;
+            end
+            // Command
+            else if ((state_q == STATE_CMD) && ulpi_nxt_i)
+            begin
+                // Write Register
+                state_q     <= STATE_REG;
+                ulpi_data_q <= data_q;
+            end
+            // Data (register write)
+            else if (state_q == STATE_REG && ulpi_nxt_i)
+            begin
+                state_q       <= STATE_IDLE;
+                ulpi_data_q   <= 8'b0;  // IDLE
+                ulpi_stp_q    <= 1'b1;
+
+                otg_write_q   <= 1'b0;
+                mode_write_q  <= 1'b0;
+            end
+            // Data
+            else if (state_q == STATE_DATA && ulpi_nxt_i)
+            begin
+                // End of packet
+                if (!utmi_tx_ready_w)
+                begin
+                    state_q       <= STATE_IDLE;
+                    ulpi_data_q   <= 8'b0;  // IDLE
+                    ulpi_stp_q    <= 1'b1;
+                end
+                else
+                begin
+                    state_q        <= STATE_DATA;
+                    ulpi_data_q    <= utmi_tx_data_w;
+                end
+            end
+        end
+    end
+end
+
+// Accept from buffer
+assign utmi_tx_accept_w = ((state_q == STATE_IDLE) && !(mode_update_q || otg_update_q || turnaround_w) && !ulpi_dir_i) ||
+                          (state_q == STATE_DATA && ulpi_nxt_i && !ulpi_dir_i);
+
+//-----------------------------------------------------------------
+// Assignments
+//-----------------------------------------------------------------
+// ULPI Interface
+assign ulpi_data_in_o       = ulpi_data_q;
+assign ulpi_stp_o           = ulpi_stp_q;
+
+// UTMI Interface
+assign utmi_linestate_o     = utmi_linestate_q;
+assign utmi_data_in_o       = utmi_data_q;
+assign utmi_rxerror_o       = utmi_rxerror_q;
+assign utmi_rxactive_o      = utmi_rxactive_q;
+assign utmi_rxvalid_o       = utmi_rxvalid_q;
+
+
+
+endmodule

fpga/usb/usb_serial/src_v/usb_cdc_core.v

@@ -0,0 +1,1116 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module usb_cdc_core
+(
+    // Inputs
+     input           clk_i
+    ,input           rst_i
+    ,input           enable_i
+    ,input  [  7:0]  utmi_data_in_i
+    ,input           utmi_txready_i
+    ,input           utmi_rxvalid_i
+    ,input           utmi_rxactive_i
+    ,input           utmi_rxerror_i
+    ,input  [  1:0]  utmi_linestate_i
+    ,input           inport_valid_i
+    ,input  [  7:0]  inport_data_i
+    ,input           outport_accept_i
+
+    // Outputs
+    ,output [  7:0]  utmi_data_out_o
+    ,output          utmi_txvalid_o
+    ,output [  1:0]  utmi_op_mode_o
+    ,output [  1:0]  utmi_xcvrselect_o
+    ,output          utmi_termselect_o
+    ,output          utmi_dppulldown_o
+    ,output          utmi_dmpulldown_o
+    ,output          inport_accept_o
+    ,output          outport_valid_o
+    ,output [  7:0]  outport_data_o
+);
+
+
+
+
+parameter USB_SPEED_HS = "False"; // True or False
+
+//-----------------------------------------------------------------
+// Defines
+//-----------------------------------------------------------------
+// Device class
+`define DEV_CLASS_RESERVED              8'h00
+`define DEV_CLASS_AUDIO                 8'h01
+`define DEV_CLASS_COMMS                 8'h02
+`define DEV_CLASS_HID                   8'h03
+`define DEV_CLASS_MONITOR               8'h04
+`define DEV_CLASS_PHY_IF                8'h05
+`define DEV_CLASS_POWER                 8'h06
+`define DEV_CLASS_PRINTER               8'h07
+`define DEV_CLASS_STORAGE               8'h08
+`define DEV_CLASS_HUB                   8'h09
+`define DEV_CLASS_TMC                   8'hFE
+`define DEV_CLASS_VENDOR_CUSTOM         8'hFF
+
+// Standard requests (via SETUP packets)
+`define REQ_GET_STATUS                  8'h00
+`define REQ_CLEAR_FEATURE               8'h01
+`define REQ_SET_FEATURE                 8'h03
+`define REQ_SET_ADDRESS                 8'h05
+`define REQ_GET_DESCRIPTOR              8'h06
+`define REQ_SET_DESCRIPTOR              8'h07
+`define REQ_GET_CONFIGURATION           8'h08
+`define REQ_SET_CONFIGURATION           8'h09
+`define REQ_GET_INTERFACE               8'h0A
+`define REQ_SET_INTERFACE               8'h0B
+`define REQ_SYNC_FRAME                  8'h0C
+
+// Descriptor types
+`define DESC_DEVICE                     8'h01
+`define DESC_CONFIGURATION              8'h02
+`define DESC_STRING                     8'h03
+`define DESC_INTERFACE                  8'h04
+`define DESC_ENDPOINT                   8'h05
+`define DESC_DEV_QUALIFIER              8'h06
+`define DESC_OTHER_SPEED_CONF           8'h07
+`define DESC_IF_POWER                   8'h08
+
+// Endpoints
+`define ENDPOINT_DIR_MASK               8'h80
+`define ENDPOINT_DIR_R                  7
+`define ENDPOINT_DIR_IN                 1'b1
+`define ENDPOINT_DIR_OUT                1'b0
+`define ENDPOINT_ADDR_MASK              8'h7F
+`define ENDPOINT_TYPE_MASK              8'h3
+`define ENDPOINT_TYPE_CONTROL           0
+`define ENDPOINT_TYPE_ISO               1
+`define ENDPOINT_TYPE_BULK              2
+`define ENDPOINT_TYPE_INTERRUPT         3
+
+// Device Requests (bmRequestType)
+`define USB_RECIPIENT_MASK              8'h1F
+`define USB_RECIPIENT_DEVICE            8'h00
+`define USB_RECIPIENT_INTERFACE         8'h01
+`define USB_RECIPIENT_ENDPOINT          8'h02
+`define USB_REQUEST_TYPE_MASK           8'h60
+`define USB_STANDARD_REQUEST            8'h00
+`define USB_CLASS_REQUEST               8'h20
+`define USB_VENDOR_REQUEST              8'h40
+
+// USB device addresses are 7-bits
+`define USB_ADDRESS_MASK                8'h7F
+
+// USB Feature Selectors
+`define USB_FEATURE_ENDPOINT_STATE      16'h0000
+`define USB_FEATURE_REMOTE_WAKEUP       16'h0001
+`define USB_FEATURE_TEST_MODE           16'h0002
+
+// String Descriptors
+`define UNICODE_LANGUAGE_STR_ID         8'd0
+`define MANUFACTURER_STR_ID             8'd1
+`define PRODUCT_NAME_STR_ID             8'd2
+`define SERIAL_NUM_STR_ID               8'd3
+
+`define CDC_ENDPOINT_BULK_OUT           1
+`define CDC_ENDPOINT_BULK_IN            2
+`define CDC_ENDPOINT_INTR_IN            3
+
+`define CDC_SEND_ENCAPSULATED_COMMAND   8'h00
+`define CDC_GET_ENCAPSULATED_RESPONSE   8'h01
+`define CDC_GET_LINE_CODING             8'h21
+`define CDC_SET_LINE_CODING             8'h20
+`define CDC_SET_CONTROL_LINE_STATE      8'h22
+`define CDC_SEND_BREAK                  8'h23
+
+// Descriptor ROM offsets / sizes
+`define ROM_DESC_DEVICE_ADDR            8'd0
+`define ROM_DESC_DEVICE_SIZE            16'd18
+`define ROM_DESC_CONF_ADDR              8'd18
+`define ROM_DESC_CONF_SIZE              16'd67
+`define ROM_DESC_STR_LANG_ADDR          8'd85
+`define ROM_DESC_STR_LANG_SIZE          16'd4
+`define ROM_DESC_STR_MAN_ADDR           8'd89
+`define ROM_DESC_STR_MAN_SIZE           16'd30
+`define ROM_DESC_STR_PROD_ADDR          8'd119
+`define ROM_DESC_STR_PROD_SIZE          16'd30
+`define ROM_DESC_STR_SERIAL_ADDR        8'd149
+`define ROM_DESC_STR_SERIAL_SIZE        16'd14
+`define ROM_CDC_LINE_CODING_ADDR        8'd163
+`define ROM_CDC_LINE_CODING_SIZE        16'd7
+
+//-----------------------------------------------------------------
+// Wires
+//-----------------------------------------------------------------
+wire         usb_reset_w;
+reg  [6:0]   device_addr_q;
+
+wire         usb_ep0_tx_rd_w;
+wire [7:0]   usb_ep0_tx_data_w;
+wire         usb_ep0_tx_empty_w;
+
+wire         usb_ep0_rx_wr_w;
+wire [7:0]   usb_ep0_rx_data_w;
+wire         usb_ep0_rx_full_w;
+wire         usb_ep1_tx_rd_w;
+wire [7:0]   usb_ep1_tx_data_w;
+wire         usb_ep1_tx_empty_w;
+
+wire         usb_ep1_rx_wr_w;
+wire [7:0]   usb_ep1_rx_data_w;
+wire         usb_ep1_rx_full_w;
+wire         usb_ep2_tx_rd_w;
+wire [7:0]   usb_ep2_tx_data_w;
+wire         usb_ep2_tx_empty_w;
+
+wire         usb_ep2_rx_wr_w;
+wire [7:0]   usb_ep2_rx_data_w;
+wire         usb_ep2_rx_full_w;
+wire         usb_ep3_tx_rd_w;
+wire [7:0]   usb_ep3_tx_data_w;
+wire         usb_ep3_tx_empty_w;
+
+wire         usb_ep3_rx_wr_w;
+wire [7:0]   usb_ep3_rx_data_w;
+wire         usb_ep3_rx_full_w;
+
+// Rx SIE Interface (shared)
+wire        rx_strb_w;
+wire [7:0]  rx_data_w;
+wire        rx_last_w;
+wire        rx_crc_err_w;
+
+// EP0 Rx SIE Interface
+wire        ep0_rx_space_w;
+wire        ep0_rx_valid_w;
+wire        ep0_rx_setup_w;
+
+// EP0 Tx SIE Interface
+wire        ep0_tx_ready_w;
+wire        ep0_tx_data_valid_w;
+wire        ep0_tx_data_strb_w;
+wire [7:0]  ep0_tx_data_w;
+wire        ep0_tx_data_last_w;
+wire        ep0_tx_data_accept_w;
+wire        ep0_tx_stall_w;
+// EP1 Rx SIE Interface
+wire        ep1_rx_space_w;
+wire        ep1_rx_valid_w;
+wire        ep1_rx_setup_w;
+
+// EP1 Tx SIE Interface
+wire        ep1_tx_ready_w;
+wire        ep1_tx_data_valid_w;
+wire        ep1_tx_data_strb_w;
+wire [7:0]  ep1_tx_data_w;
+wire        ep1_tx_data_last_w;
+wire        ep1_tx_data_accept_w;
+wire        ep1_tx_stall_w;
+// EP2 Rx SIE Interface
+wire        ep2_rx_space_w;
+wire        ep2_rx_valid_w;
+wire        ep2_rx_setup_w;
+
+// EP2 Tx SIE Interface
+wire        ep2_tx_ready_w;
+wire        ep2_tx_data_valid_w;
+wire        ep2_tx_data_strb_w;
+wire [7:0]  ep2_tx_data_w;
+wire        ep2_tx_data_last_w;
+wire        ep2_tx_data_accept_w;
+wire        ep2_tx_stall_w;
+// EP3 Rx SIE Interface
+wire        ep3_rx_space_w;
+wire        ep3_rx_valid_w;
+wire        ep3_rx_setup_w;
+
+// EP3 Tx SIE Interface
+wire        ep3_tx_ready_w;
+wire        ep3_tx_data_valid_w;
+wire        ep3_tx_data_strb_w;
+wire [7:0]  ep3_tx_data_w;
+wire        ep3_tx_data_last_w;
+wire        ep3_tx_data_accept_w;
+wire        ep3_tx_stall_w;
+
+wire utmi_chirp_en_w;
+wire usb_hs_w;
+
+//-----------------------------------------------------------------
+// Transceiver Control (high speed)
+//-----------------------------------------------------------------
+generate 
+if (USB_SPEED_HS == "True")
+begin
+
+localparam STATE_W                       = 3;
+localparam STATE_IDLE                    = 3'd0;
+localparam STATE_WAIT_RST                = 3'd1;
+localparam STATE_SEND_CHIRP_K            = 3'd2;
+localparam STATE_WAIT_CHIRP_JK           = 3'd3;
+localparam STATE_FULLSPEED               = 3'd4;
+localparam STATE_HIGHSPEED               = 3'd5;
+reg [STATE_W-1:0] state_q;
+reg [STATE_W-1:0] next_state_r;
+
+// 60MHz clock rate
+`define USB_RST_W  20
+reg [`USB_RST_W-1:0] usb_rst_time_q;
+reg [7:0]            chirp_count_q;
+reg [1:0]            last_linestate_q;
+
+localparam DETACH_TIME    = 20'd60000;  // 1ms -> T0
+localparam ATTACH_FS_TIME = 20'd180000; // T0 + 3ms = T1
+localparam CHIRPK_TIME    = 20'd246000; // T1 + ~1ms
+localparam HS_RESET_TIME  = 20'd600000; // T0 + 10ms = T9
+localparam HS_CHIRP_COUNT = 8'd5;
+
+reg [  1:0]  utmi_op_mode_r;
+reg [  1:0]  utmi_xcvrselect_r;
+reg          utmi_termselect_r;
+reg          utmi_dppulldown_r;
+reg          utmi_dmpulldown_r;
+
+always @ *
+begin
+    next_state_r = state_q;
+
+    // Default - disconnect
+    utmi_op_mode_r    = 2'd1;
+    utmi_xcvrselect_r = 2'd0;
+    utmi_termselect_r = 1'b0;
+    utmi_dppulldown_r = 1'b0;
+    utmi_dmpulldown_r = 1'b0;
+
+    case (state_q)
+    STATE_IDLE:
+    begin
+        // Detached
+        if (enable_i && usb_rst_time_q >= DETACH_TIME)
+            next_state_r = STATE_WAIT_RST;
+    end
+    STATE_WAIT_RST:
+    begin
+        // Assert FS mode, check for SE0 (T0)
+        utmi_op_mode_r    = 2'd0;
+        utmi_xcvrselect_r = 2'd1;
+        utmi_termselect_r = 1'b1;
+        utmi_dppulldown_r = 1'b0;
+        utmi_dmpulldown_r = 1'b0;
+
+        // Wait for SE0 (T1), send device chirp K
+        if (usb_rst_time_q >= ATTACH_FS_TIME)
+            next_state_r = STATE_SEND_CHIRP_K;
+    end
+    STATE_SEND_CHIRP_K:
+    begin
+        // Send chirp K
+        utmi_op_mode_r    = 2'd2;
+        utmi_xcvrselect_r = 2'd0;
+        utmi_termselect_r = 1'b1;
+        utmi_dppulldown_r = 1'b0;
+        utmi_dmpulldown_r = 1'b0;
+
+        // End of device chirp K (T2)
+        if (usb_rst_time_q >= CHIRPK_TIME)
+            next_state_r = STATE_WAIT_CHIRP_JK;
+    end
+    STATE_WAIT_CHIRP_JK:
+    begin
+        // Stop sending chirp K and wait for downstream port chirps
+        utmi_op_mode_r    = 2'd2;
+        utmi_xcvrselect_r = 2'd0;
+        utmi_termselect_r = 1'b1;
+        utmi_dppulldown_r = 1'b0;
+        utmi_dmpulldown_r = 1'b0;
+
+        // Required number of chirps detected, move to HS mode (T7)
+        if (chirp_count_q >= HS_CHIRP_COUNT)
+            next_state_r = STATE_HIGHSPEED;
+        // Time out waiting for chirps, fallback to FS mode
+        else if (usb_rst_time_q >= HS_RESET_TIME)
+            next_state_r = STATE_FULLSPEED;
+    end
+    STATE_FULLSPEED:
+    begin
+        utmi_op_mode_r    = 2'd0;
+        utmi_xcvrselect_r = 2'd1;
+        utmi_termselect_r = 1'b1;
+        utmi_dppulldown_r = 1'b0;
+        utmi_dmpulldown_r = 1'b0;
+
+        // USB reset detected...
+        if (usb_rst_time_q >= HS_RESET_TIME && usb_reset_w)
+            next_state_r = STATE_WAIT_RST;
+    end
+    STATE_HIGHSPEED:
+    begin
+        // Enter HS mode
+        utmi_op_mode_r    = 2'd0;
+        utmi_xcvrselect_r = 2'd0;
+        utmi_termselect_r = 1'b0;
+        utmi_dppulldown_r = 1'b0;
+        utmi_dmpulldown_r = 1'b0;
+
+        // Long SE0 - could be reset or suspend
+        // TODO: Should revert to FS mode and check...
+        if (usb_rst_time_q >= HS_RESET_TIME && usb_reset_w)
+            next_state_r = STATE_WAIT_RST;
+    end
+    default:
+        ;
+    endcase
+end
+
+// Update state
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    state_q   <= STATE_IDLE;
+else
+    state_q   <= next_state_r;
+
+// Time since T0 (start of HS reset)
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    usb_rst_time_q <= `USB_RST_W'b0;
+// Entering wait for reset state
+else if (next_state_r == STATE_WAIT_RST && state_q != STATE_WAIT_RST)
+    usb_rst_time_q <=  `USB_RST_W'b0;
+// Waiting for reset, reset count on line state toggle
+else if (state_q == STATE_WAIT_RST && (utmi_linestate_i != 2'b00))
+    usb_rst_time_q <=  `USB_RST_W'b0;
+else if (usb_rst_time_q != {(`USB_RST_W){1'b1}})
+    usb_rst_time_q <= usb_rst_time_q + `USB_RST_W'd1;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    last_linestate_q   <= 2'b0;
+else
+    last_linestate_q   <= utmi_linestate_i;
+
+// Chirp counter
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    chirp_count_q   <= 8'b0;
+else if (state_q == STATE_SEND_CHIRP_K)
+    chirp_count_q   <= 8'b0;
+else if (state_q == STATE_WAIT_CHIRP_JK && (last_linestate_q != utmi_linestate_i) && chirp_count_q != 8'hFF)
+    chirp_count_q   <= chirp_count_q + 8'd1;
+
+assign utmi_op_mode_o    = utmi_op_mode_r;
+assign utmi_xcvrselect_o = utmi_xcvrselect_r;
+assign utmi_termselect_o = utmi_termselect_r;
+assign utmi_dppulldown_o = utmi_dppulldown_r;
+assign utmi_dmpulldown_o = utmi_dmpulldown_r;
+
+assign utmi_chirp_en_w   = (state_q == STATE_SEND_CHIRP_K);
+assign usb_hs_w          = (state_q == STATE_HIGHSPEED);
+
+end
+else
+begin
+//-----------------------------------------------------------------
+// Transceiver Control
+//-----------------------------------------------------------------
+reg [  1:0]  utmi_op_mode_r;
+reg [  1:0]  utmi_xcvrselect_r;
+reg          utmi_termselect_r;
+reg          utmi_dppulldown_r;
+reg          utmi_dmpulldown_r;
+
+always @ *
+begin
+    if (enable_i)
+    begin
+        utmi_op_mode_r    = 2'd0;
+        utmi_xcvrselect_r = 2'd1;
+        utmi_termselect_r = 1'b1;
+        utmi_dppulldown_r = 1'b0;
+        utmi_dmpulldown_r = 1'b0;
+    end
+    else
+    begin
+        utmi_op_mode_r    = 2'd1;
+        utmi_xcvrselect_r = 2'd0;
+        utmi_termselect_r = 1'b0;
+        utmi_dppulldown_r = 1'b0;
+        utmi_dmpulldown_r = 1'b0;
+    end
+end
+
+assign utmi_op_mode_o    = utmi_op_mode_r;
+assign utmi_xcvrselect_o = utmi_xcvrselect_r;
+assign utmi_termselect_o = utmi_termselect_r;
+assign utmi_dppulldown_o = utmi_dppulldown_r;
+assign utmi_dmpulldown_o = utmi_dmpulldown_r;
+
+assign utmi_chirp_en_w   = 1'b0;
+assign usb_hs_w          = 1'b0;
+
+end
+endgenerate
+
+//-----------------------------------------------------------------
+// Core
+//-----------------------------------------------------------------
+usbf_device_core
+u_core
+(
+    .clk_i(clk_i),
+    .rst_i(rst_i),
+
+    .intr_o(),
+
+    // UTMI interface
+    .utmi_data_o(utmi_data_out_o),
+    .utmi_data_i(utmi_data_in_i),
+    .utmi_txvalid_o(utmi_txvalid_o),
+    .utmi_txready_i(utmi_txready_i),
+    .utmi_rxvalid_i(utmi_rxvalid_i),
+    .utmi_rxactive_i(utmi_rxactive_i),
+    .utmi_rxerror_i(utmi_rxerror_i),
+    .utmi_linestate_i(utmi_linestate_i),
+
+    .reg_chirp_en_i(utmi_chirp_en_w),
+    .reg_int_en_sof_i(1'b0),
+
+    .reg_dev_addr_i(device_addr_q),
+
+    // Rx SIE Interface (shared)
+    .rx_strb_o(rx_strb_w),
+    .rx_data_o(rx_data_w),
+    .rx_last_o(rx_last_w),
+    .rx_crc_err_o(rx_crc_err_w),
+
+    // EP0 Config
+    .ep0_iso_i(1'b0),
+    .ep0_stall_i(ep0_tx_stall_w),
+    .ep0_cfg_int_rx_i(1'b0),
+    .ep0_cfg_int_tx_i(1'b0),
+
+    // EP0 Rx SIE Interface
+    .ep0_rx_setup_o(ep0_rx_setup_w),
+    .ep0_rx_valid_o(ep0_rx_valid_w),
+    .ep0_rx_space_i(ep0_rx_space_w),
+
+    // EP0 Tx SIE Interface
+    .ep0_tx_ready_i(ep0_tx_ready_w),
+    .ep0_tx_data_valid_i(ep0_tx_data_valid_w),
+    .ep0_tx_data_strb_i(ep0_tx_data_strb_w),
+    .ep0_tx_data_i(ep0_tx_data_w),
+    .ep0_tx_data_last_i(ep0_tx_data_last_w),
+    .ep0_tx_data_accept_o(ep0_tx_data_accept_w),
+
+    // EP1 Config
+    .ep1_iso_i(1'b0),
+    .ep1_stall_i(ep1_tx_stall_w),
+    .ep1_cfg_int_rx_i(1'b0),
+    .ep1_cfg_int_tx_i(1'b0),
+
+    // EP1 Rx SIE Interface
+    .ep1_rx_setup_o(ep1_rx_setup_w),
+    .ep1_rx_valid_o(ep1_rx_valid_w),
+    .ep1_rx_space_i(ep1_rx_space_w),
+
+    // EP1 Tx SIE Interface
+    .ep1_tx_ready_i(ep1_tx_ready_w),
+    .ep1_tx_data_valid_i(ep1_tx_data_valid_w),
+    .ep1_tx_data_strb_i(ep1_tx_data_strb_w),
+    .ep1_tx_data_i(ep1_tx_data_w),
+    .ep1_tx_data_last_i(ep1_tx_data_last_w),
+    .ep1_tx_data_accept_o(ep1_tx_data_accept_w),
+
+    // EP2 Config
+    .ep2_iso_i(1'b0),
+    .ep2_stall_i(ep2_tx_stall_w),
+    .ep2_cfg_int_rx_i(1'b0),
+    .ep2_cfg_int_tx_i(1'b0),
+
+    // EP2 Rx SIE Interface
+    .ep2_rx_setup_o(ep2_rx_setup_w),
+    .ep2_rx_valid_o(ep2_rx_valid_w),
+    .ep2_rx_space_i(ep2_rx_space_w),
+
+    // EP2 Tx SIE Interface
+    .ep2_tx_ready_i(ep2_tx_ready_w),
+    .ep2_tx_data_valid_i(ep2_tx_data_valid_w),
+    .ep2_tx_data_strb_i(ep2_tx_data_strb_w),
+    .ep2_tx_data_i(ep2_tx_data_w),
+    .ep2_tx_data_last_i(ep2_tx_data_last_w),
+    .ep2_tx_data_accept_o(ep2_tx_data_accept_w),
+
+    // EP3 Config
+    .ep3_iso_i(1'b0),
+    .ep3_stall_i(ep3_tx_stall_w),
+    .ep3_cfg_int_rx_i(1'b0),
+    .ep3_cfg_int_tx_i(1'b0),
+
+    // EP3 Rx SIE Interface
+    .ep3_rx_setup_o(ep3_rx_setup_w),
+    .ep3_rx_valid_o(ep3_rx_valid_w),
+    .ep3_rx_space_i(ep3_rx_space_w),
+
+    // EP3 Tx SIE Interface
+    .ep3_tx_ready_i(ep3_tx_ready_w),
+    .ep3_tx_data_valid_i(ep3_tx_data_valid_w),
+    .ep3_tx_data_strb_i(ep3_tx_data_strb_w),
+    .ep3_tx_data_i(ep3_tx_data_w),
+    .ep3_tx_data_last_i(ep3_tx_data_last_w),
+    .ep3_tx_data_accept_o(ep3_tx_data_accept_w),
+
+    // Status
+    .reg_sts_rst_clr_i(1'b1),
+    .reg_sts_rst_o(usb_reset_w),
+    .reg_sts_frame_num_o()
+);
+
+assign ep0_rx_space_w = 1'b1;
+
+//-----------------------------------------------------------------
+// USB: Setup packet capture (limited to 8 bytes for USB-FS)
+//-----------------------------------------------------------------
+reg [7:0] setup_packet_q[0:7];
+reg [2:0] setup_wr_idx_q;
+reg       setup_frame_q;
+reg       setup_valid_q;
+reg       setup_data_q;
+reg       status_ready_q; // STATUS response received
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    setup_packet_q[0]  <= 8'b0;
+    setup_packet_q[1]  <= 8'b0;
+    setup_packet_q[2]  <= 8'b0;
+    setup_packet_q[3]  <= 8'b0;
+    setup_packet_q[4]  <= 8'b0;
+    setup_packet_q[5]  <= 8'b0;
+    setup_packet_q[6]  <= 8'b0;
+    setup_packet_q[7]  <= 8'b0;
+    setup_wr_idx_q     <= 3'b0;
+    setup_valid_q      <= 1'b0;
+    setup_frame_q      <= 1'b0;
+    setup_data_q       <= 1'b0;
+    status_ready_q     <= 1'b0;
+end
+// SETUP token received
+else if (ep0_rx_setup_w)
+begin
+    setup_packet_q[0]  <= 8'b0;
+    setup_packet_q[1]  <= 8'b0;
+    setup_packet_q[2]  <= 8'b0;
+    setup_packet_q[3]  <= 8'b0;
+    setup_packet_q[4]  <= 8'b0;
+    setup_packet_q[5]  <= 8'b0;
+    setup_packet_q[6]  <= 8'b0;
+    setup_packet_q[7]  <= 8'b0;
+    setup_wr_idx_q     <= 3'b0;
+    setup_valid_q      <= 1'b0;
+    setup_frame_q      <= 1'b1;
+    setup_data_q       <= 1'b0;
+    status_ready_q     <= 1'b0;
+end
+// Valid DATA for setup frame
+else if (ep0_rx_valid_w && rx_strb_w)
+begin
+    setup_packet_q[setup_wr_idx_q] <= rx_data_w;
+    setup_wr_idx_q      <= setup_wr_idx_q + 3'd1;
+    setup_valid_q       <= setup_frame_q && rx_last_w;
+    setup_data_q        <= !setup_frame_q && rx_last_w;
+    if (rx_last_w)
+        setup_frame_q   <= 1'b0;
+end
+// Detect STATUS stage (ACK for SETUP GET requests)
+// TODO: Not quite correct .... 
+else if (ep0_rx_valid_w && !rx_strb_w && rx_last_w)
+begin
+    setup_valid_q       <= 1'b0;
+    status_ready_q      <= 1'b1;
+end
+else
+    setup_valid_q       <= 1'b0;
+
+//-----------------------------------------------------------------
+// SETUP request decode
+//-----------------------------------------------------------------
+wire [7:0]  bmRequestType_w = setup_packet_q[0];
+wire [7:0]  bRequest_w      = setup_packet_q[1];
+wire [15:0] wValue_w        = {setup_packet_q[3], setup_packet_q[2]};
+wire [15:0] wIndex_w        = {setup_packet_q[5], setup_packet_q[4]};
+wire [15:0] wLength         = {setup_packet_q[7], setup_packet_q[6]};
+
+wire setup_get_w            = setup_valid_q && (bmRequestType_w[`ENDPOINT_DIR_R] == `ENDPOINT_DIR_IN);
+wire setup_set_w            = setup_valid_q && (bmRequestType_w[`ENDPOINT_DIR_R] == `ENDPOINT_DIR_OUT);
+wire setup_no_data_w        = setup_set_w && (wLength == 16'b0);
+
+// For REQ_GET_DESCRIPTOR
+wire [7:0]  bDescriptorType_w  = setup_packet_q[3];
+wire [7:0]  bDescriptorIndex_w = setup_packet_q[2];
+
+//-----------------------------------------------------------------
+// Process setup request
+//-----------------------------------------------------------------
+reg        ctrl_stall_r; // Send STALL
+reg        ctrl_ack_r;   // Send STATUS (ZLP)
+reg [15:0] ctrl_get_len_r;
+
+reg [7:0]  desc_addr_r;
+
+reg        addressed_q;
+reg        addressed_r;
+reg [6:0]  device_addr_r;
+
+reg        configured_q;
+reg        configured_r;
+
+reg        set_with_data_q;
+reg        set_with_data_r;
+wire       data_status_zlp_w;
+
+always @ *
+begin
+    ctrl_stall_r    = 1'b0;
+    ctrl_get_len_r  = 16'b0;
+    ctrl_ack_r      = 1'b0;
+    desc_addr_r     = 8'b0;
+    device_addr_r   = device_addr_q;
+    addressed_r     = addressed_q;
+    configured_r    = configured_q;
+    set_with_data_r = set_with_data_q;
+
+    if (setup_valid_q)
+    begin
+        set_with_data_r = 1'b0;
+
+        case (bmRequestType_w & `USB_REQUEST_TYPE_MASK)
+        `USB_STANDARD_REQUEST:
+        begin
+            case (bRequest_w)
+            `REQ_GET_STATUS:
+            begin
+                $display("GET_STATUS");
+            end
+            `REQ_CLEAR_FEATURE:
+            begin
+                $display("CLEAR_FEATURE");
+                ctrl_ack_r = setup_set_w && setup_no_data_w;
+            end
+            `REQ_SET_FEATURE:
+            begin
+                $display("SET_FEATURE");
+                ctrl_ack_r = setup_set_w && setup_no_data_w;
+            end
+            `REQ_SET_ADDRESS:
+            begin
+                $display("SET_ADDRESS: Set device address %d", wValue_w[6:0]);
+                ctrl_ack_r    = setup_set_w && setup_no_data_w;
+                device_addr_r = wValue_w[6:0];
+                addressed_r   = 1'b1;
+            end
+            `REQ_GET_DESCRIPTOR:
+            begin
+                $display("GET_DESCRIPTOR: Type %d", bDescriptorType_w);
+
+                case (bDescriptorType_w)
+                `DESC_DEVICE:
+                begin
+                    desc_addr_r    = `ROM_DESC_DEVICE_ADDR;
+                    ctrl_get_len_r = `ROM_DESC_DEVICE_SIZE;
+                end
+                `DESC_CONFIGURATION:
+                begin
+                    desc_addr_r    = `ROM_DESC_CONF_ADDR;
+                    ctrl_get_len_r = `ROM_DESC_CONF_SIZE;
+                end
+                `DESC_STRING:
+                begin
+                    case (bDescriptorIndex_w)
+                    `UNICODE_LANGUAGE_STR_ID:
+                    begin
+                        desc_addr_r    = `ROM_DESC_STR_LANG_ADDR;
+                        ctrl_get_len_r = `ROM_DESC_STR_LANG_SIZE;
+                    end
+                    `MANUFACTURER_STR_ID:
+                    begin
+                        desc_addr_r    = `ROM_DESC_STR_MAN_ADDR;
+                        ctrl_get_len_r = `ROM_DESC_STR_MAN_SIZE;
+                    end
+                    `PRODUCT_NAME_STR_ID:
+                    begin
+                        desc_addr_r    = `ROM_DESC_STR_PROD_ADDR;
+                        ctrl_get_len_r = `ROM_DESC_STR_PROD_SIZE;
+                    end
+                    `SERIAL_NUM_STR_ID:
+                    begin
+                        desc_addr_r    = `ROM_DESC_STR_SERIAL_ADDR;
+                        ctrl_get_len_r = `ROM_DESC_STR_SERIAL_SIZE;
+                    end
+                    default:
+                        ;
+                    endcase
+                end
+                default:
+                    ;
+                endcase
+            end
+            `REQ_GET_CONFIGURATION:
+            begin
+                $display("GET_CONF");
+            end
+            `REQ_SET_CONFIGURATION:
+            begin
+                $display("SET_CONF: Configuration %x", wValue_w);
+
+                if (wValue_w == 16'd0)
+                begin
+                    configured_r = 1'b0;
+                    ctrl_ack_r   = setup_set_w && setup_no_data_w;
+                end
+                // Only support one configuration for now
+                else if (wValue_w == 16'd1)
+                begin
+                    configured_r = 1'b1;
+                    ctrl_ack_r   = setup_set_w && setup_no_data_w;
+                end
+                else
+                    ctrl_stall_r = 1'b1;
+            end
+            `REQ_GET_INTERFACE:
+            begin
+                $display("GET_INTERFACE");
+                ctrl_stall_r = 1'b1;
+            end
+            `REQ_SET_INTERFACE:
+            begin
+                $display("SET_INTERFACE: %x %x", wValue_w, wIndex_w);
+                if (wValue_w == 16'd0 && wIndex_w == 16'd0)
+                    ctrl_ack_r   = setup_set_w && setup_no_data_w;
+                else
+                    ctrl_stall_r = 1'b1;
+            end
+            default:
+            begin
+                ctrl_stall_r = 1'b1;
+            end
+            endcase
+        end
+        `USB_VENDOR_REQUEST:
+        begin
+            // None supported
+            ctrl_stall_r = 1'b1;
+        end
+        `USB_CLASS_REQUEST:
+        begin
+            case (bRequest_w)
+            `CDC_GET_LINE_CODING:
+            begin
+                $display("CDC_GET_LINE_CODING");
+                desc_addr_r    = `ROM_CDC_LINE_CODING_ADDR;
+                ctrl_get_len_r = `ROM_CDC_LINE_CODING_SIZE;
+            end
+            default:
+            begin
+                ctrl_ack_r      = setup_set_w && setup_no_data_w;
+                set_with_data_r = setup_set_w && !setup_no_data_w;
+            end
+            endcase
+        end
+        default:
+        begin
+            ctrl_stall_r = 1'b1;
+        end
+        endcase
+    end
+    else if (data_status_zlp_w)
+        set_with_data_r = 1'b0;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    device_addr_q   <= 7'b0;
+    addressed_q     <= 1'b0;
+    configured_q    <= 1'b0;
+    set_with_data_q <= 1'b0;
+end
+else if (usb_reset_w)
+begin
+    device_addr_q   <= 7'b0;
+    addressed_q     <= 1'b0;
+    configured_q    <= 1'b0;
+    set_with_data_q <= 1'b0;
+end
+else
+begin
+    device_addr_q   <= device_addr_r;
+    addressed_q     <= addressed_r;
+    configured_q    <= configured_r;
+    set_with_data_q <= set_with_data_r;
+end
+
+//-----------------------------------------------------------------
+// SETUP response
+//-----------------------------------------------------------------
+reg        ctrl_sending_q;
+reg [15:0] ctrl_send_idx_q;
+reg [15:0] ctrl_send_len_q;
+wire       ctrl_send_zlp_w = ctrl_sending_q && (ctrl_send_len_q != wLength);
+
+reg        ctrl_sending_r;
+reg [15:0] ctrl_send_idx_r;
+reg [15:0] ctrl_send_len_r;
+
+reg        ctrl_txvalid_q;
+reg [7:0]  ctrl_txdata_q;
+reg        ctrl_txstrb_q;
+reg        ctrl_txlast_q;
+reg        ctrl_txstall_q;
+
+reg        ctrl_txvalid_r;
+reg [7:0]  ctrl_txdata_r;
+reg        ctrl_txstrb_r;
+reg        ctrl_txlast_r;
+reg        ctrl_txstall_r;
+
+wire       ctrl_send_accept_w = ep0_tx_data_accept_w || !ep0_tx_data_valid_w;
+
+reg [7:0]  desc_addr_q;
+wire[7:0]  desc_data_w;
+
+always @ *
+begin
+    ctrl_sending_r  = ctrl_sending_q;
+    ctrl_send_idx_r = ctrl_send_idx_q;
+    ctrl_send_len_r = ctrl_send_len_q;
+
+    ctrl_txvalid_r  = ctrl_txvalid_q;
+    ctrl_txdata_r   = ctrl_txdata_q;
+    ctrl_txstrb_r   = ctrl_txstrb_q;
+    ctrl_txlast_r   = ctrl_txlast_q;
+    ctrl_txstall_r  = ctrl_txstall_q;
+
+    // New SETUP request
+    if (setup_valid_q)
+    begin
+        // Send STALL
+        if (ctrl_stall_r)
+        begin
+            ctrl_txvalid_r  = 1'b1;
+            ctrl_txstrb_r   = 1'b0;
+            ctrl_txlast_r   = 1'b1;
+            ctrl_txstall_r  = 1'b1;
+        end
+        // Send STATUS response (ZLP)
+        else if (ctrl_ack_r)
+        begin
+            ctrl_txvalid_r  = 1'b1;
+            ctrl_txstrb_r   = 1'b0;
+            ctrl_txlast_r   = 1'b1;
+            ctrl_txstall_r  = 1'b0;
+        end
+        else
+        begin
+            ctrl_sending_r  = setup_get_w && !ctrl_stall_r;
+            ctrl_send_idx_r = 16'b0;
+            ctrl_send_len_r = ctrl_get_len_r;
+            ctrl_txstall_r  = 1'b0;
+        end
+    end
+    // Abort control send when STATUS received
+    else if (status_ready_q)
+    begin
+        ctrl_sending_r  = 1'b0;
+        ctrl_send_idx_r = 16'b0;
+        ctrl_send_len_r = 16'b0;
+
+        ctrl_txvalid_r  = 1'b0;
+    end
+    // Send STATUS response (ZLP)
+    else if (set_with_data_q && setup_data_q)
+    begin
+        ctrl_txvalid_r  = 1'b1;
+        ctrl_txstrb_r   = 1'b0;
+        ctrl_txlast_r   = 1'b1;
+        ctrl_txstall_r  = 1'b0;
+    end
+    else if (ctrl_sending_r && ctrl_send_accept_w)
+    begin
+        // TODO: Send ZLP on exact multiple lengths...
+        ctrl_txvalid_r  = 1'b1;
+        ctrl_txdata_r   = desc_data_w;
+        ctrl_txstrb_r   = 1'b1;
+        ctrl_txlast_r   = usb_hs_w ? (ctrl_send_idx_r[5:0] == 6'b111111) : (ctrl_send_idx_r[2:0] == 3'b111);
+
+        // Increment send index
+        ctrl_send_idx_r = ctrl_send_idx_r + 16'd1;
+
+        // TODO: Detect need for ZLP
+        if (ctrl_send_idx_r == wLength)
+        begin
+            ctrl_sending_r = 1'b0;
+            ctrl_txlast_r  = 1'b1;
+        end
+    end
+    else if (ctrl_send_accept_w)
+        ctrl_txvalid_r  = 1'b0;
+end
+
+assign data_status_zlp_w = set_with_data_q && setup_data_q && ctrl_send_accept_w;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    ctrl_sending_q  <= 1'b0;
+    ctrl_send_idx_q <= 16'b0;
+    ctrl_send_len_q <= 16'b0;
+    ctrl_txvalid_q  <= 1'b0;
+    ctrl_txdata_q   <= 8'b0;
+    ctrl_txstrb_q   <= 1'b0;
+    ctrl_txlast_q   <= 1'b0;
+    ctrl_txstall_q  <= 1'b0;
+    desc_addr_q     <= 8'b0;
+end
+else if (usb_reset_w)
+begin
+    ctrl_sending_q  <= 1'b0;
+    ctrl_send_idx_q <= 16'b0;
+    ctrl_send_len_q <= 16'b0;
+    ctrl_txvalid_q  <= 1'b0;
+    ctrl_txdata_q   <= 8'b0;
+    ctrl_txstrb_q   <= 1'b0;
+    ctrl_txlast_q   <= 1'b0;
+    ctrl_txstall_q  <= 1'b0;
+    desc_addr_q     <= 8'b0;
+end
+else
+begin
+    ctrl_sending_q  <= ctrl_sending_r;
+    ctrl_send_idx_q <= ctrl_send_idx_r;
+    ctrl_send_len_q <= ctrl_send_len_r;
+    ctrl_txvalid_q  <= ctrl_txvalid_r;
+    ctrl_txdata_q   <= ctrl_txdata_r;
+    ctrl_txstrb_q   <= ctrl_txstrb_r;
+    ctrl_txlast_q   <= ctrl_txlast_r;
+    ctrl_txstall_q  <= ctrl_txstall_r;
+
+    if (setup_valid_q)
+        desc_addr_q     <= desc_addr_r;
+    else if (ctrl_sending_r && ctrl_send_accept_w)
+        desc_addr_q     <= desc_addr_q + 8'd1;
+end
+
+assign ep0_tx_ready_w      = ctrl_txvalid_q;
+assign ep0_tx_data_valid_w = ctrl_txvalid_q;
+assign ep0_tx_data_strb_w  = ctrl_txstrb_q;
+assign ep0_tx_data_w       = ctrl_txdata_q;
+assign ep0_tx_data_last_w  = ctrl_txlast_q;
+assign ep0_tx_stall_w      = ctrl_txstall_q;
+
+//-----------------------------------------------------------------
+// Descriptor ROM
+//-----------------------------------------------------------------
+usb_desc_rom
+u_rom
+(
+    .hs_i(usb_hs_w),
+    .addr_i(desc_addr_q),
+    .data_o(desc_data_w)
+);
+
+//-----------------------------------------------------------------
+// Unused Endpoints
+//-----------------------------------------------------------------
+assign ep1_tx_ready_w      = 1'b0;
+assign ep1_tx_data_valid_w = 1'b0;
+assign ep1_tx_data_strb_w  = 1'b0;
+assign ep1_tx_data_w       = 8'b0;
+assign ep1_tx_data_last_w  = 1'b0;
+assign ep1_tx_stall_w      = 1'b0;
+assign ep3_tx_ready_w      = 1'b0;
+assign ep3_tx_data_valid_w = 1'b0;
+assign ep3_tx_data_strb_w  = 1'b0;
+assign ep3_tx_data_w       = 8'b0;
+assign ep3_tx_data_last_w  = 1'b0;
+assign ep3_tx_stall_w      = 1'b0;
+
+assign ep2_rx_space_w      = 1'b0;
+assign ep3_rx_space_w      = 1'b0;
+
+//-----------------------------------------------------------------
+// Stream I/O
+//-----------------------------------------------------------------
+reg        inport_valid_q;
+reg [7:0]  inport_data_q;
+reg [10:0] inport_cnt_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    inport_valid_q <= 1'b0;
+    inport_data_q  <= 8'b0;
+end
+else if (inport_accept_o)
+begin
+    inport_valid_q <= inport_valid_i;
+    inport_data_q  <= inport_data_i;
+end
+
+wire [10:0] max_packet_w   = usb_hs_w ? 11'd511 : 11'd63;
+wire        inport_last_w  = !inport_valid_i || (inport_cnt_q == max_packet_w);
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    inport_cnt_q  <= 11'b0;
+else if (inport_last_w && ep2_tx_data_accept_w)
+    inport_cnt_q  <= 11'b0;
+else if (inport_valid_q && ep2_tx_data_accept_w)
+    inport_cnt_q  <= inport_cnt_q + 11'd1;
+
+assign ep2_tx_data_valid_w = inport_valid_q;
+assign ep2_tx_data_w       = inport_data_q;
+assign ep2_tx_ready_w      = ep2_tx_data_valid_w;
+assign ep2_tx_data_strb_w  = ep2_tx_data_valid_w;
+assign ep2_tx_data_last_w  = inport_last_w;
+assign inport_accept_o     = !inport_valid_q | ep2_tx_data_accept_w;
+
+assign outport_valid_o  = ep1_rx_valid_w && rx_strb_w;
+assign outport_data_o   = rx_data_w;
+assign ep1_rx_space_w   = outport_accept_i;
+
+
+
+endmodule

fpga/usb/usb_serial/src_v/usb_cdc_top.v

@@ -0,0 +1,535 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module usb_cdc_top
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+     parameter BAUDRATE         = 115200
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+     input 	  clk_i,
+     input 	  rst_i,
+
+     output [7:0] utmi_data_out_o,
+     output 	  utmi_txvalid_o,
+     output [1:0] utmi_op_mode_o,
+     output [1:0] utmi_xcvrselect_o,
+     output 	  utmi_termselect_o,
+     output 	  utmi_dppulldown_o,
+     output 	  utmi_dmpulldown_o,
+
+     input [7:0]  utmi_data_in_i,
+     input 	  utmi_txready_i,
+     input 	  utmi_rxvalid_i,
+     input 	  utmi_rxactive_i,
+     input 	  utmi_rxerror_i,
+     input [1:0]  utmi_linestate_i,
+
+     input 	  tx_i,
+     output 	  rx_o
+);
+
+wire  [  7:0]  usb_rx_data_w;
+wire           usb_tx_accept_w;
+wire           enable_w = 1'h1;
+wire           usb_tx_valid_w;
+wire           usb_rx_accept_w;
+wire  [  7:0]  usb_tx_data_w;
+wire           usb_rx_valid_w;
+
+usb_cdc_core
+u_usb
+(
+    // Inputs
+     .clk_i(clk_i)
+    ,.rst_i(rst_i)
+    ,.enable_i(enable_w)
+    ,.utmi_data_in_i(utmi_data_in_i)
+    ,.utmi_txready_i(utmi_txready_i)
+    ,.utmi_rxvalid_i(utmi_rxvalid_i)
+    ,.utmi_rxactive_i(utmi_rxactive_i)
+    ,.utmi_rxerror_i(utmi_rxerror_i)
+    ,.utmi_linestate_i(utmi_linestate_i)
+    ,.inport_valid_i(usb_tx_valid_w)
+    ,.inport_data_i(usb_tx_data_w)
+    ,.outport_accept_i(usb_rx_accept_w)
+
+    // Outputs
+    ,.utmi_data_out_o(utmi_data_out_o)
+    ,.utmi_txvalid_o(utmi_txvalid_o)
+    ,.utmi_op_mode_o(utmi_op_mode_o)
+    ,.utmi_xcvrselect_o(utmi_xcvrselect_o)
+    ,.utmi_termselect_o(utmi_termselect_o)
+    ,.utmi_dppulldown_o(utmi_dppulldown_o)
+    ,.utmi_dmpulldown_o(utmi_dmpulldown_o)
+    ,.inport_accept_o(usb_tx_accept_w)
+    ,.outport_valid_o(usb_rx_valid_w)
+    ,.outport_data_o(usb_rx_data_w)
+);
+
+//-----------------------------------------------------------------
+// Output FIFO
+//-----------------------------------------------------------------
+wire       tx_valid_w;
+wire [7:0] tx_data_w;
+wire       tx_accept_w;
+
+usb_cdc_fifo
+#(
+    .WIDTH(8),
+    .DEPTH(512),
+    .ADDR_W(9)
+)
+u_fifo_tx
+(
+    .clk_i(clk_i),
+    .rst_i(rst_i),
+
+    // In
+    .push_i(tx_valid_w),
+    .data_in_i(tx_data_w),
+    .accept_o(tx_accept_w),
+
+    // Out
+    .pop_i(usb_tx_accept_w),
+    .data_out_o(usb_tx_data_w),
+    .valid_o(usb_tx_valid_w)
+);
+
+//-----------------------------------------------------------------
+// Input FIFO
+//-----------------------------------------------------------------
+wire       rx_valid_w;
+wire [7:0] rx_data_w;
+wire       rx_accept_w;
+
+usb_cdc_fifo
+#(
+    .WIDTH(8),
+    .DEPTH(512),
+    .ADDR_W(9)
+)
+u_fifo_rx
+(
+    .clk_i(clk_i),
+    .rst_i(rst_i),
+
+    // In
+    .push_i(usb_rx_valid_w),
+    .data_in_i(usb_rx_data_w),
+    .accept_o(usb_rx_accept_w),
+
+    // Out
+    .pop_i(rx_accept_w),
+    .data_out_o(rx_data_w),
+    .valid_o(rx_valid_w)
+);
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+
+// Configuration
+localparam   STOP_BITS = 1'b0; // 0 = 1, 1 = 2
+localparam   CLK_FREQ  = 48000000;
+localparam   BIT_DIV   = (CLK_FREQ / BAUDRATE) - 1;
+
+localparam   START_BIT = 4'd0;
+localparam   STOP_BIT0 = 4'd9;
+localparam   STOP_BIT1 = 4'd10;
+
+// Xilinx placement pragmas:
+//synthesis attribute IOB of txd_q is "TRUE"
+
+// TX Signals
+reg          tx_busy_q;
+reg [3:0]    tx_bits_q;
+reg [31:0]   tx_count_q;
+reg [7:0]    tx_shift_reg_q;
+reg          txd_q;
+
+// RX Signals
+reg          rxd_q;
+reg [7:0]    rx_data_q;
+reg [3:0]    rx_bits_q;
+reg [31:0]   rx_count_q;
+reg [7:0]    rx_shift_reg_q;
+reg          rx_ready_q;
+reg          rx_busy_q;
+
+reg          rx_err_q;
+
+//-----------------------------------------------------------------
+// Re-sync RXD
+//-----------------------------------------------------------------
+reg rxd_ms_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+   rxd_ms_q <= 1'b1;
+   rxd_q    <= 1'b1;
+end
+else
+begin
+   rxd_ms_q <= tx_i;
+   rxd_q    <= rxd_ms_q;
+end
+
+//-----------------------------------------------------------------
+// RX Clock Divider
+//-----------------------------------------------------------------
+wire rx_sample_w = (rx_count_q == 32'b0);
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rx_count_q        <= 32'b0;
+else
+begin
+    // Inactive
+    if (!rx_busy_q)
+        rx_count_q    <= {1'b0, BIT_DIV[31:1]};
+    // Rx bit timer
+    else if (rx_count_q != 0)
+        rx_count_q    <= (rx_count_q - 1);
+    // Active
+    else if (rx_sample_w)
+    begin
+        // Last bit?
+        if ((rx_bits_q == STOP_BIT0 && !STOP_BITS) || (rx_bits_q == STOP_BIT1 && STOP_BITS))
+            rx_count_q    <= 32'b0;
+        else
+            rx_count_q    <= BIT_DIV;
+    end
+end
+
+//-----------------------------------------------------------------
+// RX Shift Register
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    rx_shift_reg_q <= 8'h00;
+    rx_busy_q      <= 1'b0;
+end
+// Rx busy
+else if (rx_busy_q && rx_sample_w)
+begin
+    // Last bit?
+    if (rx_bits_q == STOP_BIT0 && !STOP_BITS)
+        rx_busy_q <= 1'b0;
+    else if (rx_bits_q == STOP_BIT1 && STOP_BITS)
+        rx_busy_q <= 1'b0;
+    else if (rx_bits_q == START_BIT)
+    begin
+        // Start bit should still be low as sampling mid
+        // way through start bit, so if high, error!
+        if (rxd_q)
+            rx_busy_q <= 1'b0;
+    end
+    // Rx shift register
+    else 
+        rx_shift_reg_q <= {rxd_q, rx_shift_reg_q[7:1]};
+end
+// Start bit?
+else if (!rx_busy_q && rxd_q == 1'b0)
+begin
+    rx_shift_reg_q <= 8'h00;
+    rx_busy_q      <= 1'b1;
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rx_bits_q  <= START_BIT;
+else if (rx_sample_w && rx_busy_q)
+begin
+    if ((rx_bits_q == STOP_BIT1 && STOP_BITS) || (rx_bits_q == STOP_BIT0 && !STOP_BITS))
+        rx_bits_q <= START_BIT;
+    else
+        rx_bits_q <= rx_bits_q + 4'd1;
+end
+else if (!rx_busy_q && (BIT_DIV == 32'b0))
+    rx_bits_q  <= START_BIT + 4'd1;
+else if (!rx_busy_q)
+    rx_bits_q  <= START_BIT;
+
+//-----------------------------------------------------------------
+// RX Data
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+   rx_ready_q      <= 1'b0;
+   rx_data_q       <= 8'h00;
+   rx_err_q        <= 1'b0;
+end
+else
+begin
+   // If reading data, reset data state
+   if (tx_accept_w)
+   begin
+       rx_ready_q <= 1'b0;
+       rx_err_q   <= 1'b0;
+   end
+
+   if (rx_busy_q && rx_sample_w)
+   begin
+       // Stop bit
+       if ((rx_bits_q == STOP_BIT1 && STOP_BITS) || (rx_bits_q == STOP_BIT0 && !STOP_BITS))
+       begin
+           // RXD should be still high
+           if (rxd_q)
+           begin
+               rx_data_q      <= rx_shift_reg_q;
+               rx_ready_q     <= 1'b1;
+           end
+           // Bad Stop bit - wait for a full bit period
+           // before allowing start bit detection again
+           else
+           begin
+               rx_ready_q      <= 1'b0;
+               rx_data_q       <= 8'h00;
+               rx_err_q        <= 1'b1;
+           end
+       end
+       // Mid start bit sample - if high then error
+       else if (rx_bits_q == START_BIT && rxd_q)
+           rx_err_q        <= 1'b1;
+   end
+end
+
+assign tx_data_w   = rx_data_q;
+assign tx_valid_w  = rx_ready_q;
+
+//-----------------------------------------------------------------
+// TX Clock Divider
+//-----------------------------------------------------------------
+wire tx_sample_w = (tx_count_q == 32'b0);
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    tx_count_q      <= 32'b0;
+else
+begin
+    // Idle
+    if (!tx_busy_q)
+        tx_count_q  <= BIT_DIV;
+    // Tx bit timer
+    else if (tx_count_q != 0)
+        tx_count_q  <= (tx_count_q - 1);
+    else if (tx_sample_w)
+        tx_count_q  <= BIT_DIV;
+end
+
+//-----------------------------------------------------------------
+// TX Shift Register
+//-----------------------------------------------------------------
+reg tx_complete_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    tx_shift_reg_q <= 8'h00;
+    tx_busy_q      <= 1'b0;
+    tx_complete_q  <= 1'b0;
+end
+// Tx busy
+else if (tx_busy_q)
+begin
+    // Shift tx data
+    if (tx_bits_q != START_BIT && tx_sample_w)
+        tx_shift_reg_q <= {1'b0, tx_shift_reg_q[7:1]};
+
+    // Last bit?
+    if (tx_bits_q == STOP_BIT0 && tx_sample_w && !STOP_BITS)
+    begin
+        tx_busy_q      <= 1'b0;
+        tx_complete_q  <= 1'b1;
+    end
+    else if (tx_bits_q == STOP_BIT1 && tx_sample_w && STOP_BITS)
+    begin
+        tx_busy_q      <= 1'b0;
+        tx_complete_q  <= 1'b1;
+    end
+end
+// Buffer data to transmit
+else if (rx_valid_w)
+begin
+    tx_shift_reg_q <= rx_data_w;
+    tx_busy_q      <= 1'b1;
+    tx_complete_q  <= 1'b0;
+end
+else
+    tx_complete_q  <= 1'b0;
+
+assign rx_accept_w = ~tx_busy_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    tx_bits_q  <= 4'd0;
+else if (tx_sample_w && tx_busy_q)
+begin
+    if ((tx_bits_q == STOP_BIT1 && STOP_BITS) || (tx_bits_q == STOP_BIT0 && !STOP_BITS))
+        tx_bits_q <= START_BIT;
+    else
+        tx_bits_q <= tx_bits_q + 4'd1;
+end
+
+//-----------------------------------------------------------------
+// UART Tx Pin
+//-----------------------------------------------------------------
+reg txd_r;
+
+always @ *
+begin
+    txd_r = 1'b1;
+
+    if (tx_busy_q)
+    begin
+        // Start bit (TXD = L)
+        if (tx_bits_q == START_BIT)
+            txd_r = 1'b0;
+        // Stop bits (TXD = H)
+        else if (tx_bits_q == STOP_BIT0 || tx_bits_q == STOP_BIT1)
+            txd_r = 1'b1;
+        // Data bits
+        else
+            txd_r = tx_shift_reg_q[0];
+    end
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    txd_q <= 1'b1;
+else
+    txd_q <= txd_r;
+
+assign rx_o = txd_q;
+
+
+endmodule
+
+module usb_cdc_fifo
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+    parameter WIDTH   = 8,
+    parameter DEPTH   = 4,
+    parameter ADDR_W  = 2
+)
+//-----------------------------------------------------------------
+// Ports
+//-----------------------------------------------------------------
+(
+    // Inputs
+     input               clk_i
+    ,input               rst_i
+    ,input  [WIDTH-1:0]  data_in_i
+    ,input               push_i
+    ,input               pop_i
+
+    // Outputs
+    ,output [WIDTH-1:0]  data_out_o
+    ,output              accept_o
+    ,output              valid_o
+);
+
+//-----------------------------------------------------------------
+// Local Params
+//-----------------------------------------------------------------
+localparam COUNT_W = ADDR_W + 1;
+
+//-----------------------------------------------------------------
+// Registers
+//-----------------------------------------------------------------
+reg [WIDTH-1:0]   ram_q[DEPTH-1:0];
+reg [ADDR_W-1:0]  rd_ptr_q;
+reg [ADDR_W-1:0]  wr_ptr_q;
+reg [COUNT_W-1:0] count_q;
+
+//-----------------------------------------------------------------
+// Sequential
+//-----------------------------------------------------------------
+always @ (posedge clk_i )
+if (rst_i)
+begin
+    count_q   <= {(COUNT_W) {1'b0}};
+    rd_ptr_q  <= {(ADDR_W) {1'b0}};
+    wr_ptr_q  <= {(ADDR_W) {1'b0}};
+end
+else
+begin
+    // Push
+    if (push_i & accept_o)
+    begin
+        ram_q[wr_ptr_q] <= data_in_i;
+        wr_ptr_q        <= wr_ptr_q + 1;
+    end
+
+    // Pop
+    if (pop_i & valid_o)
+        rd_ptr_q      <= rd_ptr_q + 1;
+
+    // Count up
+    if ((push_i & accept_o) & ~(pop_i & valid_o))
+        count_q <= count_q + 1;
+    // Count down
+    else if (~(push_i & accept_o) & (pop_i & valid_o))
+        count_q <= count_q - 1;
+end
+
+//-------------------------------------------------------------------
+// Combinatorial
+//-------------------------------------------------------------------
+/* verilator lint_off WIDTH */
+assign valid_o       = (count_q != 0);
+assign accept_o      = (count_q != DEPTH);
+/* verilator lint_on WIDTH */
+
+assign data_out_o    = ram_q[rd_ptr_q];
+
+
+
+
+endmodule

fpga/usb/usb_serial/src_v/usb_desc_rom.v

@@ -0,0 +1,226 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+module usb_desc_rom
+(
+    input        hs_i,
+    input  [7:0] addr_i,
+    output [7:0] data_o
+);
+
+reg [7:0] desc_rom_r;
+
+always @ *
+begin
+    case (addr_i)
+    8'd0: desc_rom_r = 8'h12;
+    8'd1: desc_rom_r = 8'h01;
+    8'd2: desc_rom_r = 8'h00;
+    8'd3: desc_rom_r = 8'h02;
+    8'd4: desc_rom_r = 8'h02;
+    8'd5: desc_rom_r = 8'h00;
+    8'd6: desc_rom_r = 8'h00;
+    8'd7: desc_rom_r = hs_i ? 8'h40 : 8'h08;
+    8'd8: desc_rom_r = 8'h50;  // VID_L
+    8'd9: desc_rom_r = 8'h1d;  // VID_H
+    8'd10: desc_rom_r = 8'h49; // PID_L 
+    8'd11: desc_rom_r = 8'h61; // PID_H
+    8'd12: desc_rom_r = 8'h01;
+    8'd13: desc_rom_r = 8'h01;
+    8'd14: desc_rom_r = 8'h00;
+    8'd15: desc_rom_r = 8'h00;
+    8'd16: desc_rom_r = 8'h00;
+    8'd17: desc_rom_r = 8'h01;
+    8'd18: desc_rom_r = 8'h09;
+    8'd19: desc_rom_r = 8'h02;
+    8'd20: desc_rom_r = 8'h43;
+    8'd21: desc_rom_r = 8'h00;
+    8'd22: desc_rom_r = 8'h02;
+    8'd23: desc_rom_r = 8'h01;
+    8'd24: desc_rom_r = 8'h00;
+    8'd25: desc_rom_r = 8'h80;
+    8'd26: desc_rom_r = 8'h32;
+    8'd27: desc_rom_r = 8'h09;
+    8'd28: desc_rom_r = 8'h04;
+    8'd29: desc_rom_r = 8'h00;
+    8'd30: desc_rom_r = 8'h00;
+    8'd31: desc_rom_r = 8'h01;
+    8'd32: desc_rom_r = 8'h02;
+    8'd33: desc_rom_r = 8'h02;
+    8'd34: desc_rom_r = 8'h01;
+    8'd35: desc_rom_r = 8'h00;
+    8'd36: desc_rom_r = 8'h05;
+    8'd37: desc_rom_r = 8'h24;
+    8'd38: desc_rom_r = 8'h00;
+    8'd39: desc_rom_r = 8'h10;
+    8'd40: desc_rom_r = 8'h01;
+    8'd41: desc_rom_r = 8'h05;
+    8'd42: desc_rom_r = 8'h24;
+    8'd43: desc_rom_r = 8'h01;
+    8'd44: desc_rom_r = 8'h03;
+    8'd45: desc_rom_r = 8'h01;
+    8'd46: desc_rom_r = 8'h04;
+    8'd47: desc_rom_r = 8'h24;
+    8'd48: desc_rom_r = 8'h02;
+    8'd49: desc_rom_r = 8'h06;
+    8'd50: desc_rom_r = 8'h05;
+    8'd51: desc_rom_r = 8'h24;
+    8'd52: desc_rom_r = 8'h06;
+    8'd53: desc_rom_r = 8'h00;
+    8'd54: desc_rom_r = 8'h01;
+    8'd55: desc_rom_r = 8'h07;
+    8'd56: desc_rom_r = 8'h05;
+    8'd57: desc_rom_r = 8'h83;
+    8'd58: desc_rom_r = 8'h03;
+    8'd59: desc_rom_r = 8'h40;
+    8'd60: desc_rom_r = 8'h00;
+    8'd61: desc_rom_r = 8'h02;
+    8'd62: desc_rom_r = 8'h09;
+    8'd63: desc_rom_r = 8'h04;
+    8'd64: desc_rom_r = 8'h01;
+    8'd65: desc_rom_r = 8'h00;
+    8'd66: desc_rom_r = 8'h02;
+    8'd67: desc_rom_r = 8'h0a;
+    8'd68: desc_rom_r = 8'h00;
+    8'd69: desc_rom_r = 8'h00;
+    8'd70: desc_rom_r = 8'h00;
+    8'd71: desc_rom_r = 8'h07;
+    8'd72: desc_rom_r = 8'h05;
+    8'd73: desc_rom_r = 8'h01;
+    8'd74: desc_rom_r = 8'h02;
+    8'd75: desc_rom_r = hs_i ? 8'h00 : 8'h40;
+    8'd76: desc_rom_r = hs_i ? 8'h02 : 8'h00;
+    8'd77: desc_rom_r = 8'h00;
+    8'd78: desc_rom_r = 8'h07;
+    8'd79: desc_rom_r = 8'h05;
+    8'd80: desc_rom_r = 8'h82;
+    8'd81: desc_rom_r = 8'h02;
+    8'd82: desc_rom_r = hs_i ? 8'h00 : 8'h40;
+    8'd83: desc_rom_r = hs_i ? 8'h02 : 8'h00;
+    8'd84: desc_rom_r = 8'h00;
+    8'd85: desc_rom_r = 8'h04;
+    8'd86: desc_rom_r = 8'h03;
+    8'd87: desc_rom_r = 8'h09;
+    8'd88: desc_rom_r = 8'h04;
+    8'd89: desc_rom_r = 8'h1e;
+    8'd90: desc_rom_r = 8'h03;
+    8'd91: desc_rom_r = 8'h55;
+    8'd92: desc_rom_r = 8'h00;
+    8'd93: desc_rom_r = 8'h4c;
+    8'd94: desc_rom_r = 8'h00;
+    8'd95: desc_rom_r = 8'h54;
+    8'd96: desc_rom_r = 8'h00;
+    8'd97: desc_rom_r = 8'h52;
+    8'd98: desc_rom_r = 8'h00;
+    8'd99: desc_rom_r = 8'h41;
+    8'd100: desc_rom_r = 8'h00;
+    8'd101: desc_rom_r = 8'h2d;
+    8'd102: desc_rom_r = 8'h00;
+    8'd103: desc_rom_r = 8'h45;
+    8'd104: desc_rom_r = 8'h00;
+    8'd105: desc_rom_r = 8'h4d;
+    8'd106: desc_rom_r = 8'h00;
+    8'd107: desc_rom_r = 8'h42;
+    8'd108: desc_rom_r = 8'h00;
+    8'd109: desc_rom_r = 8'h45;
+    8'd110: desc_rom_r = 8'h00;
+    8'd111: desc_rom_r = 8'h44;
+    8'd112: desc_rom_r = 8'h00;
+    8'd113: desc_rom_r = 8'h44;
+    8'd114: desc_rom_r = 8'h00;
+    8'd115: desc_rom_r = 8'h45;
+    8'd116: desc_rom_r = 8'h00;
+    8'd117: desc_rom_r = 8'h44;
+    8'd118: desc_rom_r = 8'h00;
+    8'd119: desc_rom_r = 8'h1e;
+    8'd120: desc_rom_r = 8'h03;
+    8'd121: desc_rom_r = 8'h55;
+    8'd122: desc_rom_r = 8'h00;
+    8'd123: desc_rom_r = 8'h53;
+    8'd124: desc_rom_r = 8'h00;
+    8'd125: desc_rom_r = 8'h42;
+    8'd126: desc_rom_r = 8'h00;
+    8'd127: desc_rom_r = 8'h20;
+    8'd128: desc_rom_r = 8'h00;
+    8'd129: desc_rom_r = 8'h44;
+    8'd130: desc_rom_r = 8'h00;
+    8'd131: desc_rom_r = 8'h45;
+    8'd132: desc_rom_r = 8'h00;
+    8'd133: desc_rom_r = 8'h4d;
+    8'd134: desc_rom_r = 8'h00;
+    8'd135: desc_rom_r = 8'h4f;
+    8'd136: desc_rom_r = 8'h00;
+    8'd137: desc_rom_r = 8'h20;
+    8'd138: desc_rom_r = 8'h00;
+    8'd139: desc_rom_r = 8'h20;
+    8'd140: desc_rom_r = 8'h00;
+    8'd141: desc_rom_r = 8'h20;
+    8'd142: desc_rom_r = 8'h00;
+    8'd143: desc_rom_r = 8'h20;
+    8'd144: desc_rom_r = 8'h00;
+    8'd145: desc_rom_r = 8'h20;
+    8'd146: desc_rom_r = 8'h00;
+    8'd147: desc_rom_r = 8'h20;
+    8'd148: desc_rom_r = 8'h00;
+    8'd149: desc_rom_r = 8'h0e;
+    8'd150: desc_rom_r = 8'h03;
+    8'd151: desc_rom_r = 8'h30;
+    8'd152: desc_rom_r = 8'h00;
+    8'd153: desc_rom_r = 8'h30;
+    8'd154: desc_rom_r = 8'h00;
+    8'd155: desc_rom_r = 8'h30;
+    8'd156: desc_rom_r = 8'h00;
+    8'd157: desc_rom_r = 8'h30;
+    8'd158: desc_rom_r = 8'h00;
+    8'd159: desc_rom_r = 8'h30;
+    8'd160: desc_rom_r = 8'h00;
+    8'd161: desc_rom_r = 8'h30;
+    8'd162: desc_rom_r = 8'h00;
+    8'd163: desc_rom_r = 8'h00;
+    8'd164: desc_rom_r = 8'hc2;
+    8'd165: desc_rom_r = 8'h01;
+    8'd166: desc_rom_r = 8'h00;
+    8'd167: desc_rom_r = 8'h00;
+    8'd168: desc_rom_r = 8'h00;
+    8'd169: desc_rom_r = 8'h08;
+    default: desc_rom_r = 8'h00;
+    endcase
+end
+
+assign data_o = desc_rom_r;
+
+endmodule

fpga/usb/usb_serial/src_v/usbf_crc16.v

@@ -0,0 +1,83 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module usbf_crc16
+(
+    // Inputs
+     input  [ 15:0]  crc_in_i
+    ,input  [  7:0]  din_i
+
+    // Outputs
+    ,output [ 15:0]  crc_out_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Logic
+//-----------------------------------------------------------------
+assign crc_out_o[15] =    din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^ 
+                        crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
+assign crc_out_o[14] =    din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^
+                        crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
+assign crc_out_o[13] =    din_i[6] ^ din_i[7] ^ 
+                        crc_in_i[7] ^ crc_in_i[6];
+assign crc_out_o[12] =    din_i[5] ^ din_i[6] ^ 
+                        crc_in_i[6] ^ crc_in_i[5];
+assign crc_out_o[11] =    din_i[4] ^ din_i[5] ^ 
+                        crc_in_i[5] ^ crc_in_i[4];
+assign crc_out_o[10] =    din_i[3] ^ din_i[4] ^ 
+                        crc_in_i[4] ^ crc_in_i[3];
+assign crc_out_o[9] =     din_i[2] ^ din_i[3] ^ 
+                        crc_in_i[3] ^ crc_in_i[2];
+assign crc_out_o[8] =     din_i[1] ^ din_i[2] ^ 
+                        crc_in_i[2] ^ crc_in_i[1];
+assign crc_out_o[7] =     din_i[0] ^ din_i[1] ^ 
+                        crc_in_i[15] ^ crc_in_i[1] ^ crc_in_i[0];
+assign crc_out_o[6] =     din_i[0] ^ 
+                        crc_in_i[14] ^ crc_in_i[0];
+assign crc_out_o[5] =     crc_in_i[13];
+assign crc_out_o[4] =     crc_in_i[12];
+assign crc_out_o[3] =     crc_in_i[11];
+assign crc_out_o[2] =     crc_in_i[10];
+assign crc_out_o[1] =     crc_in_i[9];
+assign crc_out_o[0] =     din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
+                        crc_in_i[8] ^ crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
+
+
+endmodule

fpga/usb/usb_serial/src_v/usbf_defs.v

@@ -0,0 +1,64 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+//-----------------------------------------------------------------
+// Definitions
+//-----------------------------------------------------------------
+
+// Tokens
+`define PID_OUT                    8'hE1
+`define PID_IN                     8'h69
+`define PID_SOF                    8'hA5
+`define PID_SETUP                  8'h2D
+
+// Data
+`define PID_DATA0                  8'hC3
+`define PID_DATA1                  8'h4B
+`define PID_DATA2                  8'h87
+`define PID_MDATA                  8'h0F
+
+// Handshake
+`define PID_ACK                    8'hD2
+`define PID_NAK                    8'h5A
+`define PID_STALL                  8'h1E
+`define PID_NYET                   8'h96
+
+// Special
+`define PID_PRE                    8'h3C
+`define PID_ERR                    8'h3C
+`define PID_SPLIT                  8'h78
+`define PID_PING                   8'hB4

fpga/usb/usb_serial/src_v/usbf_device_core.v

@@ -0,0 +1,1054 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module usbf_device_core
+(
+    // Inputs
+     input           clk_i
+    ,input           rst_i
+    ,input  [  7:0]  utmi_data_i
+    ,input           utmi_txready_i
+    ,input           utmi_rxvalid_i
+    ,input           utmi_rxactive_i
+    ,input           utmi_rxerror_i
+    ,input  [  1:0]  utmi_linestate_i
+    ,input           ep0_stall_i
+    ,input           ep0_iso_i
+    ,input           ep0_cfg_int_rx_i
+    ,input           ep0_cfg_int_tx_i
+    ,input           ep0_rx_space_i
+    ,input           ep0_tx_ready_i
+    ,input           ep0_tx_data_valid_i
+    ,input           ep0_tx_data_strb_i
+    ,input  [  7:0]  ep0_tx_data_i
+    ,input           ep0_tx_data_last_i
+    ,input           ep1_stall_i
+    ,input           ep1_iso_i
+    ,input           ep1_cfg_int_rx_i
+    ,input           ep1_cfg_int_tx_i
+    ,input           ep1_rx_space_i
+    ,input           ep1_tx_ready_i
+    ,input           ep1_tx_data_valid_i
+    ,input           ep1_tx_data_strb_i
+    ,input  [  7:0]  ep1_tx_data_i
+    ,input           ep1_tx_data_last_i
+    ,input           ep2_stall_i
+    ,input           ep2_iso_i
+    ,input           ep2_cfg_int_rx_i
+    ,input           ep2_cfg_int_tx_i
+    ,input           ep2_rx_space_i
+    ,input           ep2_tx_ready_i
+    ,input           ep2_tx_data_valid_i
+    ,input           ep2_tx_data_strb_i
+    ,input  [  7:0]  ep2_tx_data_i
+    ,input           ep2_tx_data_last_i
+    ,input           ep3_stall_i
+    ,input           ep3_iso_i
+    ,input           ep3_cfg_int_rx_i
+    ,input           ep3_cfg_int_tx_i
+    ,input           ep3_rx_space_i
+    ,input           ep3_tx_ready_i
+    ,input           ep3_tx_data_valid_i
+    ,input           ep3_tx_data_strb_i
+    ,input  [  7:0]  ep3_tx_data_i
+    ,input           ep3_tx_data_last_i
+    ,input           reg_chirp_en_i
+    ,input           reg_int_en_sof_i
+    ,input           reg_sts_rst_clr_i
+    ,input  [  6:0]  reg_dev_addr_i
+
+    // Outputs
+    ,output          intr_o
+    ,output [  7:0]  utmi_data_o
+    ,output          utmi_txvalid_o
+    ,output          rx_strb_o
+    ,output [  7:0]  rx_data_o
+    ,output          rx_last_o
+    ,output          rx_crc_err_o
+    ,output          ep0_rx_setup_o
+    ,output          ep0_rx_valid_o
+    ,output          ep0_tx_data_accept_o
+    ,output          ep1_rx_setup_o
+    ,output          ep1_rx_valid_o
+    ,output          ep1_tx_data_accept_o
+    ,output          ep2_rx_setup_o
+    ,output          ep2_rx_valid_o
+    ,output          ep2_tx_data_accept_o
+    ,output          ep3_rx_setup_o
+    ,output          ep3_rx_valid_o
+    ,output          ep3_tx_data_accept_o
+    ,output          reg_sts_rst_o
+    ,output [ 10:0]  reg_sts_frame_num_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+`include "usbf_defs.v"
+
+`define USB_RESET_CNT_W     15
+
+localparam STATE_W                       = 3;
+localparam STATE_RX_IDLE                 = 3'd0;
+localparam STATE_RX_DATA                 = 3'd1;
+localparam STATE_RX_DATA_READY           = 3'd2;
+localparam STATE_RX_DATA_IGNORE          = 3'd3;
+localparam STATE_TX_DATA                 = 3'd4;
+localparam STATE_TX_DATA_COMPLETE        = 3'd5;
+localparam STATE_TX_HANDSHAKE            = 3'd6;
+localparam STATE_TX_CHIRP                = 3'd7;
+reg [STATE_W-1:0] state_q;
+
+//-----------------------------------------------------------------
+// Reset detection
+//-----------------------------------------------------------------
+reg [`USB_RESET_CNT_W-1:0] se0_cnt_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    se0_cnt_q <= `USB_RESET_CNT_W'b0;
+else if (utmi_linestate_i == 2'b0)
+begin
+    if (!se0_cnt_q[`USB_RESET_CNT_W-1])
+        se0_cnt_q <= se0_cnt_q + `USB_RESET_CNT_W'd1;
+end    
+else
+    se0_cnt_q <= `USB_RESET_CNT_W'b0;
+
+wire usb_rst_w = se0_cnt_q[`USB_RESET_CNT_W-1];
+
+//-----------------------------------------------------------------
+// Wire / Regs
+//-----------------------------------------------------------------
+`define USB_FRAME_W    11
+wire [`USB_FRAME_W-1:0] frame_num_w;
+
+wire                    frame_valid_w;
+
+`define USB_DEV_W      7
+wire [`USB_DEV_W-1:0]   token_dev_w;
+
+`define USB_EP_W       4
+wire [`USB_EP_W-1:0]    token_ep_w;
+
+`define USB_PID_W      8
+wire [`USB_PID_W-1:0]   token_pid_w;
+
+wire                    token_valid_w;
+
+wire                    rx_data_valid_w;
+wire                    rx_data_complete_w;
+
+wire                    rx_handshake_w;
+
+reg                     tx_data_valid_r;
+reg                     tx_data_strb_r;
+reg  [7:0]              tx_data_r;
+reg                     tx_data_last_r;
+wire                    tx_data_accept_w;
+
+reg                     tx_valid_q;
+reg [7:0]               tx_pid_q;
+wire                    tx_accept_w;
+
+reg                     rx_space_q;
+reg                     rx_space_r;
+reg                     tx_ready_r;
+reg                     out_data_bit_r;
+reg                     in_data_bit_r;
+
+reg                     ep_stall_r;
+reg                     ep_iso_r;
+
+reg                     rx_enable_q;
+reg                     rx_setup_q;
+
+reg                     ep0_out_data_bit_q;
+reg                     ep0_in_data_bit_q;
+reg                     ep1_out_data_bit_q;
+reg                     ep1_in_data_bit_q;
+reg                     ep2_out_data_bit_q;
+reg                     ep2_in_data_bit_q;
+reg                     ep3_out_data_bit_q;
+reg                     ep3_in_data_bit_q;
+
+reg [`USB_DEV_W-1:0]    current_addr_q;
+
+//-----------------------------------------------------------------
+// SIE - TX
+//-----------------------------------------------------------------
+usbf_sie_tx
+u_sie_tx
+(
+    .clk_i(clk_i),
+    .rst_i(rst_i),
+    
+    .enable_i(~usb_rst_w),
+    .chirp_i(reg_chirp_en_i),
+
+    // UTMI Interface
+    .utmi_data_o(utmi_data_o),
+    .utmi_txvalid_o(utmi_txvalid_o),
+    .utmi_txready_i(utmi_txready_i),
+
+    // Request
+    .tx_valid_i(tx_valid_q),
+    .tx_pid_i(tx_pid_q),
+    .tx_accept_o(tx_accept_w),
+
+    // Data
+    .data_valid_i(tx_data_valid_r),
+    .data_strb_i(tx_data_strb_r),
+    .data_i(tx_data_r),
+    .data_last_i(tx_data_last_r),
+    .data_accept_o(tx_data_accept_w)
+);
+
+always @ *
+begin
+    tx_data_valid_r = 1'b0;
+    tx_data_strb_r  = 1'b0;
+    tx_data_r       = 8'b0;
+    tx_data_last_r  = 1'b0;
+
+    case (token_ep_w)
+    4'd0:
+    begin
+        tx_data_valid_r = ep0_tx_data_valid_i;
+        tx_data_strb_r  = ep0_tx_data_strb_i;
+        tx_data_r       = ep0_tx_data_i;
+        tx_data_last_r  = ep0_tx_data_last_i;
+    end
+    4'd1:
+    begin
+        tx_data_valid_r = ep1_tx_data_valid_i;
+        tx_data_strb_r  = ep1_tx_data_strb_i;
+        tx_data_r       = ep1_tx_data_i;
+        tx_data_last_r  = ep1_tx_data_last_i;
+    end
+    4'd2:
+    begin
+        tx_data_valid_r = ep2_tx_data_valid_i;
+        tx_data_strb_r  = ep2_tx_data_strb_i;
+        tx_data_r       = ep2_tx_data_i;
+        tx_data_last_r  = ep2_tx_data_last_i;
+    end
+    4'd3:
+    begin
+        tx_data_valid_r = ep3_tx_data_valid_i;
+        tx_data_strb_r  = ep3_tx_data_strb_i;
+        tx_data_r       = ep3_tx_data_i;
+        tx_data_last_r  = ep3_tx_data_last_i;
+    end
+    default:
+        ;
+    endcase    
+end
+
+assign ep0_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd0);
+assign ep1_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd1);
+assign ep2_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd2);
+assign ep3_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd3);
+
+always @ *
+begin
+    rx_space_r     = 1'b0;
+    tx_ready_r     = 1'b0;
+    out_data_bit_r = 1'b0;
+    in_data_bit_r  = 1'b0;
+
+    ep_stall_r = 1'b0;
+    ep_iso_r   = 1'b0;
+
+    case (token_ep_w)
+    4'd0:
+    begin
+        rx_space_r    = ep0_rx_space_i;
+        tx_ready_r    = ep0_tx_ready_i;
+        out_data_bit_r= ep0_out_data_bit_q;
+        in_data_bit_r = ep0_in_data_bit_q;
+        ep_stall_r    = ep0_stall_i;
+        ep_iso_r      = ep0_iso_i;
+    end
+    4'd1:
+    begin
+        rx_space_r    = ep1_rx_space_i;
+        tx_ready_r    = ep1_tx_ready_i;
+        out_data_bit_r= ep1_out_data_bit_q;
+        in_data_bit_r = ep1_in_data_bit_q;
+        ep_stall_r    = ep1_stall_i;
+        ep_iso_r      = ep1_iso_i;
+    end
+    4'd2:
+    begin
+        rx_space_r    = ep2_rx_space_i;
+        tx_ready_r    = ep2_tx_ready_i;
+        out_data_bit_r= ep2_out_data_bit_q;
+        in_data_bit_r = ep2_in_data_bit_q;
+        ep_stall_r    = ep2_stall_i;
+        ep_iso_r      = ep2_iso_i;
+    end
+    4'd3:
+    begin
+        rx_space_r    = ep3_rx_space_i;
+        tx_ready_r    = ep3_tx_ready_i;
+        out_data_bit_r= ep3_out_data_bit_q;
+        in_data_bit_r = ep3_in_data_bit_q;
+        ep_stall_r    = ep3_stall_i;
+        ep_iso_r      = ep3_iso_i;
+    end
+    default:
+        ;
+    endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rx_space_q <= 1'b0;
+else if (state_q == STATE_RX_IDLE)
+    rx_space_q <= rx_space_r;
+
+//-----------------------------------------------------------------
+// SIE - RX
+//-----------------------------------------------------------------
+usbf_sie_rx
+u_sie_rx
+(
+    .clk_i(clk_i),
+    .rst_i(rst_i),
+    
+    .enable_i(~usb_rst_w && ~reg_chirp_en_i),
+
+    // UTMI Interface
+    .utmi_data_i(utmi_data_i),
+    .utmi_rxvalid_i(utmi_rxvalid_i),
+    .utmi_rxactive_i(utmi_rxactive_i),
+
+    .current_addr_i(current_addr_q),
+
+    .pid_o(token_pid_w),
+
+    .frame_valid_o(frame_valid_w),
+    .frame_number_o(reg_sts_frame_num_o),
+
+    .token_valid_o(token_valid_w),
+    .token_addr_o(token_dev_w),
+    .token_ep_o(token_ep_w),
+    .token_crc_err_o(),
+
+    .handshake_valid_o(rx_handshake_w),
+
+    .data_valid_o(rx_data_valid_w),
+    .data_strb_o(rx_strb_o),
+    .data_o(rx_data_o),
+    .data_last_o(rx_last_o),
+
+    .data_complete_o(rx_data_complete_w),
+    .data_crc_err_o(rx_crc_err_o)
+);
+
+assign ep0_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd0);
+assign ep0_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
+assign ep1_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd1);
+assign ep1_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
+assign ep2_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd2);
+assign ep2_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
+assign ep3_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd3);
+assign ep3_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
+
+//-----------------------------------------------------------------
+// Next state
+//-----------------------------------------------------------------
+reg [STATE_W-1:0] next_state_r;
+
+always @ *
+begin
+    next_state_r = state_q;
+
+    //-----------------------------------------
+    // State Machine
+    //-----------------------------------------
+    case (state_q)
+
+    //-----------------------------------------
+    // IDLE
+    //-----------------------------------------
+    STATE_RX_IDLE :
+    begin
+        // Token received (OUT, IN, SETUP, PING)
+        if (token_valid_w)
+        begin
+            //-------------------------------
+            // IN transfer (device -> host)
+            //-------------------------------
+            if (token_pid_w == `PID_IN)
+            begin
+                // Stalled endpoint?
+                if (ep_stall_r)
+                    next_state_r  = STATE_TX_HANDSHAKE;
+                // Some data to TX?
+                else if (tx_ready_r)
+                    next_state_r  = STATE_TX_DATA;
+                // No data to TX
+                else
+                    next_state_r  = STATE_TX_HANDSHAKE;
+            end
+            //-------------------------------
+            // PING transfer (device -> host)
+            //-------------------------------
+            else if (token_pid_w == `PID_PING)
+            begin
+                next_state_r  = STATE_TX_HANDSHAKE;
+            end
+            //-------------------------------
+            // OUT transfer (host -> device)
+            //-------------------------------
+            else if (token_pid_w == `PID_OUT)
+            begin
+                // Stalled endpoint?
+                if (ep_stall_r)
+                    next_state_r  = STATE_RX_DATA_IGNORE;
+                // Some space to rx
+                else if (rx_space_r)
+                    next_state_r  = STATE_RX_DATA;
+                // No rx space, ignore receive
+                else
+                    next_state_r  = STATE_RX_DATA_IGNORE;
+            end
+            //-------------------------------
+            // SETUP transfer (host -> device)
+            //-------------------------------
+            else if (token_pid_w == `PID_SETUP)
+            begin
+                // Some space to rx
+                if (rx_space_r)
+                    next_state_r  = STATE_RX_DATA;
+                // No rx space, ignore receive
+                else
+                    next_state_r  = STATE_RX_DATA_IGNORE;
+            end
+        end
+        else if (reg_chirp_en_i)
+            next_state_r  = STATE_TX_CHIRP;
+    end
+
+    //-----------------------------------------
+    // RX_DATA
+    //-----------------------------------------
+    STATE_RX_DATA :
+    begin
+        // TODO: Exit data state handling?
+
+        // TODO: Sort out ISO data bit handling
+        // Check for expected DATAx PID
+        if ((token_pid_w == `PID_DATA0 &&  out_data_bit_r && !ep_iso_r) ||
+            (token_pid_w == `PID_DATA1 && !out_data_bit_r && !ep_iso_r))
+            next_state_r  = STATE_RX_DATA_IGNORE;
+        // Receive complete
+        else if (rx_data_valid_w && rx_last_o)
+            next_state_r  = STATE_RX_DATA_READY;
+    end
+    //-----------------------------------------
+    // RX_DATA_IGNORE
+    //-----------------------------------------
+    STATE_RX_DATA_IGNORE :
+    begin
+        // Receive complete
+        if (rx_data_valid_w && rx_last_o)
+            next_state_r  = STATE_RX_DATA_READY;
+    end
+    //-----------------------------------------
+    // RX_DATA_READY
+    //-----------------------------------------
+    STATE_RX_DATA_READY :
+    begin
+        if (rx_data_complete_w)
+        begin
+            // No response on CRC16 error
+            if (rx_crc_err_o)
+                next_state_r  = STATE_RX_IDLE;
+            // ISO endpoint, no response?
+            else if (ep_iso_r)
+                next_state_r  = STATE_RX_IDLE;
+            else
+                next_state_r  = STATE_TX_HANDSHAKE;
+        end
+    end
+    //-----------------------------------------
+    // TX_DATA
+    //-----------------------------------------
+    STATE_TX_DATA :
+    begin
+        if (!tx_valid_q || tx_accept_w)
+            if (tx_data_valid_r && tx_data_last_r && tx_data_accept_w)
+                next_state_r  = STATE_TX_DATA_COMPLETE;
+    end
+    //-----------------------------------------
+    // TX_HANDSHAKE
+    //-----------------------------------------
+    STATE_TX_DATA_COMPLETE :
+    begin
+        next_state_r  = STATE_RX_IDLE;
+    end
+    //-----------------------------------------
+    // TX_HANDSHAKE
+    //-----------------------------------------
+    STATE_TX_HANDSHAKE :
+    begin
+        if (tx_accept_w)
+            next_state_r  = STATE_RX_IDLE;
+    end
+    //-----------------------------------------
+    // TX_CHIRP
+    //-----------------------------------------
+    STATE_TX_CHIRP :
+    begin
+        if (!reg_chirp_en_i)
+            next_state_r  = STATE_RX_IDLE;
+    end
+
+    default :
+       ;
+
+    endcase
+
+    //-----------------------------------------
+    // USB Bus Reset (HOST->DEVICE)
+    //----------------------------------------- 
+    if (usb_rst_w && !reg_chirp_en_i)
+        next_state_r  = STATE_RX_IDLE;
+end
+
+// Update state
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    state_q   <= STATE_RX_IDLE;
+else
+    state_q   <= next_state_r;
+
+//-----------------------------------------------------------------
+// Response
+//-----------------------------------------------------------------
+reg         tx_valid_r;
+reg [7:0]   tx_pid_r;
+
+always @ *
+begin
+    tx_valid_r = 1'b0;
+    tx_pid_r   = 8'b0;
+
+    case (state_q)
+    //-----------------------------------------
+    // IDLE
+    //-----------------------------------------
+    STATE_RX_IDLE :
+    begin
+        // Token received (OUT, IN, SETUP, PING)
+        if (token_valid_w)
+        begin
+            //-------------------------------
+            // IN transfer (device -> host)
+            //-------------------------------
+            if (token_pid_w == `PID_IN)
+            begin
+                // Stalled endpoint?
+                if (ep_stall_r)
+                begin
+                    tx_valid_r = 1'b1;
+                    tx_pid_r   = `PID_STALL;
+                end
+                // Some data to TX?
+                else if (tx_ready_r)
+                begin
+                    tx_valid_r = 1'b1;
+                    // TODO: Handle MDATA for ISOs
+                    tx_pid_r   = in_data_bit_r ? `PID_DATA1 : `PID_DATA0;
+                end
+                // No data to TX
+                else
+                begin
+                    tx_valid_r = 1'b1;
+                    tx_pid_r   = `PID_NAK;
+                end
+            end
+            //-------------------------------
+            // PING transfer (device -> host)
+            //-------------------------------
+            else if (token_pid_w == `PID_PING)
+            begin
+                // Stalled endpoint?
+                if (ep_stall_r)
+                begin
+                    tx_valid_r = 1'b1;
+                    tx_pid_r   = `PID_STALL;
+                end
+                // Data ready to RX
+                else if (rx_space_r)
+                begin
+                    tx_valid_r = 1'b1;
+                    tx_pid_r   = `PID_ACK;
+                end
+                // No data to TX
+                else
+                begin
+                    tx_valid_r = 1'b1;
+                    tx_pid_r   = `PID_NAK;
+                end
+            end
+        end
+    end
+
+    //-----------------------------------------
+    // RX_DATA_READY
+    //-----------------------------------------
+    STATE_RX_DATA_READY :
+    begin
+       // Receive complete
+       if (rx_data_complete_w)
+       begin
+            // No response on CRC16 error
+            if (rx_crc_err_o)
+                ;
+            // ISO endpoint, no response?
+            else if (ep_iso_r)
+                ;
+            // Send STALL?
+            else if (ep_stall_r)
+            begin
+                tx_valid_r = 1'b1;
+                tx_pid_r   = `PID_STALL;
+            end
+            // DATAx bit mismatch
+            else if ( (token_pid_w == `PID_DATA0 && out_data_bit_r) ||
+                      (token_pid_w == `PID_DATA1 && !out_data_bit_r) )
+            begin
+                // Ack transfer to resync
+                tx_valid_r = 1'b1;
+                tx_pid_r   = `PID_ACK;
+            end
+            // Send NAK
+            else if (!rx_space_q)
+            begin
+                tx_valid_r = 1'b1;
+                tx_pid_r   = `PID_NAK;
+            end
+            // TODO: USB 2.0, no more buffer space, return NYET
+            else
+            begin
+                tx_valid_r = 1'b1;
+                tx_pid_r   = `PID_ACK;
+            end
+       end
+    end
+
+    //-----------------------------------------
+    // TX_CHIRP
+    //-----------------------------------------
+    STATE_TX_CHIRP :
+    begin
+        tx_valid_r = 1'b1;
+        tx_pid_r   = 8'b0;
+    end
+
+    default :
+       ;
+
+    endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    tx_valid_q <= 1'b0;
+else if (!tx_valid_q || tx_accept_w)
+    tx_valid_q <= tx_valid_r;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    tx_pid_q <= 8'b0;
+else if (!tx_valid_q || tx_accept_w)
+    tx_pid_q <= tx_pid_r;
+
+//-----------------------------------------------------------------
+// Receive enable
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rx_enable_q <= 1'b0;
+else if (usb_rst_w ||reg_chirp_en_i)
+    rx_enable_q <= 1'b0;
+else
+    rx_enable_q <= (state_q == STATE_RX_DATA);
+
+//-----------------------------------------------------------------
+// Receive SETUP: Pulse on SETUP packet receive
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rx_setup_q <= 1'b0;
+else if (usb_rst_w ||reg_chirp_en_i)
+    rx_setup_q <= 1'b0;
+else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
+    rx_setup_q <= 1'b1;
+else
+    rx_setup_q <= 1'b0;
+
+//-----------------------------------------------------------------
+// Set Address
+//-----------------------------------------------------------------
+reg addr_update_pending_q;
+
+wire ep0_tx_zlp_w = ep0_tx_data_valid_i && (ep0_tx_data_strb_i == 1'b0) && 
+                    ep0_tx_data_last_i && ep0_tx_data_accept_o;
+
+reg sent_status_zlp_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    sent_status_zlp_q   <= 1'b0;
+else if (usb_rst_w)
+    sent_status_zlp_q   <= 1'b0;
+else if (ep0_tx_zlp_w)
+    sent_status_zlp_q   <= 1'b1;
+else if (rx_handshake_w)
+    sent_status_zlp_q   <= 1'b0;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    addr_update_pending_q   <= 1'b0;
+else if ((sent_status_zlp_q && addr_update_pending_q && rx_handshake_w && token_pid_w == `PID_ACK) || usb_rst_w)
+    addr_update_pending_q   <= 1'b0;
+// TODO: Use write strobe
+else if (reg_dev_addr_i != current_addr_q)
+    addr_update_pending_q   <= 1'b1;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    current_addr_q  <= `USB_DEV_W'b0;
+else if (usb_rst_w)
+    current_addr_q  <= `USB_DEV_W'b0;
+else if (sent_status_zlp_q && addr_update_pending_q && rx_handshake_w && token_pid_w == `PID_ACK)
+    current_addr_q  <= reg_dev_addr_i;
+
+//-----------------------------------------------------------------
+// Endpoint data bit toggle
+//-----------------------------------------------------------------
+reg new_out_bit_r;
+reg new_in_bit_r;
+
+always @ *
+begin
+    new_out_bit_r = out_data_bit_r;
+    new_in_bit_r  = in_data_bit_r;
+
+    case (state_q)
+    //-----------------------------------------
+    // RX_DATA_READY
+    //-----------------------------------------
+    STATE_RX_DATA_READY :
+    begin
+       // Receive complete
+       if (rx_data_complete_w)
+       begin
+            // No toggle on CRC16 error
+            if (rx_crc_err_o)
+                ;
+            // ISO endpoint, no response?
+            else if (ep_iso_r)
+                ; // TODO: HS handling
+            // STALL?
+            else if (ep_stall_r)
+                ;
+            // DATAx bit mismatch
+            else if ( (token_pid_w == `PID_DATA0 && out_data_bit_r) ||
+                      (token_pid_w == `PID_DATA1 && !out_data_bit_r) )
+                ;
+            // NAKd
+            else if (!rx_space_q)
+                ;
+            // Data accepted - toggle data bit
+            else
+                new_out_bit_r = !out_data_bit_r;
+       end
+    end
+    //-----------------------------------------
+    // RX_IDLE
+    //-----------------------------------------
+    STATE_RX_IDLE :
+    begin
+        // Token received (OUT, IN, SETUP, PING)
+        if (token_valid_w)
+        begin
+            // SETUP packets always start with DATA0
+            if (token_pid_w == `PID_SETUP)
+            begin
+                new_out_bit_r = 1'b0;
+                new_in_bit_r  = 1'b1;
+            end
+        end
+        // ACK received
+        else if (rx_handshake_w && token_pid_w == `PID_ACK)
+        begin
+            new_in_bit_r = !in_data_bit_r;
+        end
+    end
+    default:
+        ;
+    endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    ep0_out_data_bit_q <= 1'b0;
+    ep0_in_data_bit_q  <= 1'b0;
+end
+else if (usb_rst_w)
+begin
+    ep0_out_data_bit_q <= 1'b0;
+    ep0_in_data_bit_q  <= 1'b0;
+end
+else if (token_ep_w == 4'd0)
+begin
+    ep0_out_data_bit_q <= new_out_bit_r;
+    ep0_in_data_bit_q  <= new_in_bit_r;
+end
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    ep1_out_data_bit_q <= 1'b0;
+    ep1_in_data_bit_q  <= 1'b0;
+end
+else if (usb_rst_w)
+begin
+    ep1_out_data_bit_q <= 1'b0;
+    ep1_in_data_bit_q  <= 1'b0;
+end
+else if (token_ep_w == 4'd1)
+begin
+    ep1_out_data_bit_q <= new_out_bit_r;
+    ep1_in_data_bit_q  <= new_in_bit_r;
+end
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    ep2_out_data_bit_q <= 1'b0;
+    ep2_in_data_bit_q  <= 1'b0;
+end
+else if (usb_rst_w)
+begin
+    ep2_out_data_bit_q <= 1'b0;
+    ep2_in_data_bit_q  <= 1'b0;
+end
+else if (token_ep_w == 4'd2)
+begin
+    ep2_out_data_bit_q <= new_out_bit_r;
+    ep2_in_data_bit_q  <= new_in_bit_r;
+end
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    ep3_out_data_bit_q <= 1'b0;
+    ep3_in_data_bit_q  <= 1'b0;
+end
+else if (usb_rst_w)
+begin
+    ep3_out_data_bit_q <= 1'b0;
+    ep3_in_data_bit_q  <= 1'b0;
+end
+else if (token_ep_w == 4'd3)
+begin
+    ep3_out_data_bit_q <= new_out_bit_r;
+    ep3_in_data_bit_q  <= new_in_bit_r;
+end
+
+//-----------------------------------------------------------------
+// Reset event
+//-----------------------------------------------------------------
+reg rst_event_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rst_event_q <= 1'b0;
+else if (usb_rst_w)
+    rst_event_q <= 1'b1;
+else if (reg_sts_rst_clr_i)
+    rst_event_q <= 1'b0;
+
+assign reg_sts_rst_o = rst_event_q;
+
+//-----------------------------------------------------------------
+// Interrupts
+//-----------------------------------------------------------------
+reg intr_q;
+
+reg cfg_int_rx_r;
+reg cfg_int_tx_r;
+
+always @ *
+begin
+    cfg_int_rx_r = 1'b0;
+    cfg_int_tx_r = 1'b0;
+
+    case (token_ep_w)
+    4'd0:
+    begin
+        cfg_int_rx_r = ep0_cfg_int_rx_i;
+        cfg_int_tx_r = ep0_cfg_int_tx_i;
+    end
+    4'd1:
+    begin
+        cfg_int_rx_r = ep1_cfg_int_rx_i;
+        cfg_int_tx_r = ep1_cfg_int_tx_i;
+    end
+    4'd2:
+    begin
+        cfg_int_rx_r = ep2_cfg_int_rx_i;
+        cfg_int_tx_r = ep2_cfg_int_tx_i;
+    end
+    4'd3:
+    begin
+        cfg_int_rx_r = ep3_cfg_int_rx_i;
+        cfg_int_tx_r = ep3_cfg_int_tx_i;
+    end
+    default:
+        ;
+    endcase
+end
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    intr_q <= 1'b0;
+// SOF
+else if (frame_valid_w && reg_int_en_sof_i)
+    intr_q <= 1'b1;
+// Reset event
+else if (!rst_event_q && usb_rst_w)
+    intr_q <= 1'b1;
+// Rx ready
+else if (state_q == STATE_RX_DATA_READY && rx_space_q && cfg_int_rx_r)
+    intr_q <= 1'b1;
+// Tx complete
+else if (state_q == STATE_TX_DATA_COMPLETE && cfg_int_tx_r)
+    intr_q <= 1'b1;    
+else
+    intr_q <= 1'b0;
+
+assign intr_o = intr_q;
+
+//-------------------------------------------------------------------
+// Debug
+//-------------------------------------------------------------------
+`ifdef verilator
+/* verilator lint_off WIDTH */
+reg [79:0] dbg_state;
+
+always @ *
+begin
+    dbg_state = "-";
+
+    case (state_q)
+    STATE_RX_IDLE: dbg_state = "IDLE";
+    STATE_RX_DATA: dbg_state = "RX_DATA";
+    STATE_RX_DATA_READY: dbg_state = "RX_DATA_READY";
+    STATE_RX_DATA_IGNORE: dbg_state = "RX_IGNORE";
+    STATE_TX_DATA: dbg_state = "TX_DATA";
+    STATE_TX_DATA_COMPLETE: dbg_state = "TX_DATA_COMPLETE";
+    STATE_TX_HANDSHAKE: dbg_state = "TX_HANDSHAKE";
+    STATE_TX_CHIRP: dbg_state = "CHIRP";
+    endcase
+end
+
+reg [79:0] dbg_pid;
+reg [7:0]  dbg_pid_r;
+always @ *
+begin
+    dbg_pid = "-";
+
+    if (tx_valid_q && tx_accept_w)
+        dbg_pid_r = tx_pid_q;
+    else if (token_valid_w || rx_handshake_w || rx_data_valid_w)
+        dbg_pid_r = token_pid_w;
+    else
+        dbg_pid_r = 8'b0;
+
+    case (dbg_pid_r)
+    // Token
+    `PID_OUT:
+        dbg_pid = "OUT";
+    `PID_IN:
+        dbg_pid = "IN";
+    `PID_SOF:
+        dbg_pid = "SOF";
+    `PID_SETUP:
+        dbg_pid = "SETUP";
+    `PID_PING:
+        dbg_pid = "PING";
+    // Data
+    `PID_DATA0:
+        dbg_pid = "DATA0";
+    `PID_DATA1:
+        dbg_pid = "DATA1";
+    `PID_DATA2:
+        dbg_pid = "DATA2";
+    `PID_MDATA:
+        dbg_pid = "MDATA";
+    // Handshake
+    `PID_ACK:
+        dbg_pid = "ACK";
+    `PID_NAK:
+        dbg_pid = "NAK";
+    `PID_STALL:
+        dbg_pid = "STALL";
+    `PID_NYET:
+        dbg_pid = "NYET";
+    // Special
+    `PID_PRE:
+        dbg_pid = "PRE/ERR";
+    `PID_SPLIT:
+        dbg_pid = "SPLIT";
+    default:
+        ;
+    endcase
+end
+/* verilator lint_on WIDTH */
+`endif
+
+
+endmodule

fpga/usb/usb_serial/src_v/usbf_sie_rx.v

@@ -0,0 +1,467 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module usbf_sie_rx
+(
+    // Inputs
+     input           clk_i
+    ,input           rst_i
+    ,input           enable_i
+    ,input  [  7:0]  utmi_data_i
+    ,input           utmi_rxvalid_i
+    ,input           utmi_rxactive_i
+    ,input  [  6:0]  current_addr_i
+
+    // Outputs
+    ,output [  7:0]  pid_o
+    ,output          frame_valid_o
+    ,output [ 10:0]  frame_number_o
+    ,output          token_valid_o
+    ,output [  6:0]  token_addr_o
+    ,output [  3:0]  token_ep_o
+    ,output          token_crc_err_o
+    ,output          handshake_valid_o
+    ,output          data_valid_o
+    ,output          data_strb_o
+    ,output [  7:0]  data_o
+    ,output          data_last_o
+    ,output          data_crc_err_o
+    ,output          data_complete_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+`include "usbf_defs.v"
+
+localparam STATE_W                       = 4;
+localparam STATE_RX_IDLE                 = 4'd0;
+localparam STATE_RX_TOKEN2               = 4'd1;
+localparam STATE_RX_TOKEN3               = 4'd2;
+localparam STATE_RX_TOKEN_COMPLETE       = 4'd3;
+localparam STATE_RX_SOF2                 = 4'd4;
+localparam STATE_RX_SOF3                 = 4'd5;
+localparam STATE_RX_DATA                 = 4'd6;
+localparam STATE_RX_DATA_COMPLETE        = 4'd7;
+localparam STATE_RX_IGNORED              = 4'd8;
+reg [STATE_W-1:0] state_q;
+
+//-----------------------------------------------------------------
+// Wire / Regs
+//-----------------------------------------------------------------
+`define USB_FRAME_W    11
+reg [`USB_FRAME_W-1:0]      frame_num_q;
+
+`define USB_DEV_W      7
+reg [`USB_DEV_W-1:0]        token_dev_q;
+
+`define USB_EP_W       4
+reg [`USB_EP_W-1:0]         token_ep_q;
+
+`define USB_PID_W      8
+reg [`USB_PID_W-1:0]        token_pid_q;
+
+//-----------------------------------------------------------------
+// Data delay (to strip the CRC16 trailing bytes)
+//-----------------------------------------------------------------
+reg [31:0] data_buffer_q;
+reg [3:0]  data_valid_q;
+reg [3:0]  rx_active_q;
+
+wire shift_en_w = (utmi_rxvalid_i & utmi_rxactive_i) || !utmi_rxactive_i;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    data_buffer_q <= 32'b0;
+else if (shift_en_w)
+    data_buffer_q <= {utmi_data_i, data_buffer_q[31:8]};
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    data_valid_q <= 4'b0;
+else if (shift_en_w)
+    data_valid_q <= {(utmi_rxvalid_i & utmi_rxactive_i), data_valid_q[3:1]};
+else
+    data_valid_q <= {data_valid_q[3:1], 1'b0};
+
+reg [1:0] data_crc_q;
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    data_crc_q <= 2'b0;
+else if (shift_en_w)
+    data_crc_q <= {!utmi_rxactive_i, data_crc_q[1]};
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    rx_active_q <= 4'b0;
+else
+    rx_active_q <= {utmi_rxactive_i, rx_active_q[3:1]};
+
+wire [7:0] data_w       = data_buffer_q[7:0];
+wire       data_ready_w = data_valid_q[0];
+wire       crc_byte_w   = data_crc_q[0];
+wire       rx_active_w  = rx_active_q[0];
+
+wire       address_match_w = (token_dev_q == current_addr_i);
+
+//-----------------------------------------------------------------
+// Next state
+//-----------------------------------------------------------------
+reg [STATE_W-1:0] next_state_r;
+
+always @ *
+begin
+    next_state_r = state_q;
+
+    case (state_q)
+
+    //-----------------------------------------
+    // IDLE
+    //-----------------------------------------
+    STATE_RX_IDLE :
+    begin
+       if (data_ready_w)
+       begin
+           // Decode PID
+           case (data_w)
+
+              `PID_OUT, `PID_IN, `PID_SETUP, `PID_PING:
+                    next_state_r  = STATE_RX_TOKEN2;
+
+              `PID_SOF:
+                    next_state_r  = STATE_RX_SOF2;
+
+              `PID_DATA0, `PID_DATA1, `PID_DATA2, `PID_MDATA:
+              begin
+                    next_state_r  = STATE_RX_DATA;
+              end
+
+              `PID_ACK, `PID_NAK, `PID_STALL, `PID_NYET:
+                    next_state_r  = STATE_RX_IDLE;
+
+              default : // SPLIT / ERR
+                    next_state_r  = STATE_RX_IGNORED;
+           endcase
+       end
+    end
+
+    //-----------------------------------------
+    // RX_IGNORED: Unknown / unsupported
+    //-----------------------------------------
+    STATE_RX_IGNORED :
+    begin
+        // Wait until the end of the packet
+        if (!rx_active_w)
+           next_state_r = STATE_RX_IDLE;
+    end
+
+    //-----------------------------------------
+    // SOF (BYTE 2)
+    //-----------------------------------------
+    STATE_RX_SOF2 :
+    begin
+       if (data_ready_w)
+           next_state_r = STATE_RX_SOF3;
+       else if (!rx_active_w)
+           next_state_r = STATE_RX_IDLE;
+    end
+
+    //-----------------------------------------
+    // SOF (BYTE 3)
+    //-----------------------------------------
+    STATE_RX_SOF3 :
+    begin
+       if (data_ready_w || !rx_active_w)
+           next_state_r = STATE_RX_IDLE;
+    end
+
+    //-----------------------------------------
+    // TOKEN (IN/OUT/SETUP) (Address/Endpoint)
+    //-----------------------------------------
+    STATE_RX_TOKEN2 :
+    begin
+       if (data_ready_w)
+           next_state_r = STATE_RX_TOKEN3;
+       else if (!rx_active_w)
+           next_state_r = STATE_RX_IDLE;
+    end
+
+    //-----------------------------------------
+    // TOKEN (IN/OUT/SETUP) (Endpoint/CRC)
+    //-----------------------------------------
+    STATE_RX_TOKEN3 :
+    begin
+       if (data_ready_w)
+           next_state_r = STATE_RX_TOKEN_COMPLETE;
+       else if (!rx_active_w)
+           next_state_r = STATE_RX_IDLE;
+    end
+
+    //-----------------------------------------
+    // RX_TOKEN_COMPLETE
+    //-----------------------------------------
+    STATE_RX_TOKEN_COMPLETE :
+    begin
+        next_state_r  = STATE_RX_IDLE;
+    end
+
+    //-----------------------------------------
+    // RX_DATA
+    //-----------------------------------------
+    STATE_RX_DATA :
+    begin
+       // Receive complete
+       if (crc_byte_w)
+            next_state_r = STATE_RX_DATA_COMPLETE;
+    end
+
+    //-----------------------------------------
+    // RX_DATA_COMPLETE
+    //-----------------------------------------
+    STATE_RX_DATA_COMPLETE :
+    begin
+        if (!rx_active_w)
+            next_state_r = STATE_RX_IDLE;
+    end
+
+    default :
+       ;
+
+    endcase
+end
+
+// Update state
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    state_q   <= STATE_RX_IDLE;
+else if (!enable_i)
+    state_q   <= STATE_RX_IDLE;
+else
+    state_q   <= next_state_r;
+
+//-----------------------------------------------------------------
+// Handshake:
+//-----------------------------------------------------------------
+reg handshake_valid_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    handshake_valid_q <= 1'b0;
+else if (state_q == STATE_RX_IDLE && data_ready_w)
+begin
+    case (data_w)
+    `PID_ACK, `PID_NAK, `PID_STALL, `PID_NYET:
+        handshake_valid_q <= address_match_w;
+    default :
+        handshake_valid_q <= 1'b0;
+    endcase
+end
+else
+    handshake_valid_q <= 1'b0;
+
+assign handshake_valid_o = handshake_valid_q;
+
+//-----------------------------------------------------------------
+// SOF: Frame number
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    frame_num_q         <= `USB_FRAME_W'b0;
+else if (state_q == STATE_RX_SOF2 && data_ready_w)
+    frame_num_q         <= {3'b0, data_w};
+else if (state_q == STATE_RX_SOF3 && data_ready_w)
+    frame_num_q         <= {data_w[2:0], frame_num_q[7:0]};
+else if (!enable_i)
+    frame_num_q         <= `USB_FRAME_W'b0;
+
+assign frame_number_o = frame_num_q;
+
+reg frame_valid_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    frame_valid_q <= 1'b0;
+else
+    frame_valid_q <= (state_q == STATE_RX_SOF3 && data_ready_w);
+
+assign frame_valid_o = frame_valid_q;
+
+//-----------------------------------------------------------------
+// Token: PID
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    token_pid_q <= `USB_PID_W'b0;
+else if (state_q == STATE_RX_IDLE && data_ready_w)
+    token_pid_q <= data_w;
+else if (!enable_i)
+    token_pid_q <= `USB_PID_W'b0;
+
+assign pid_o = token_pid_q;
+
+reg token_valid_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    token_valid_q <= 1'b0;
+else
+    token_valid_q <= (state_q == STATE_RX_TOKEN_COMPLETE) && address_match_w;
+
+assign token_valid_o = token_valid_q;
+
+//-----------------------------------------------------------------
+// Token: Device Address
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    token_dev_q <= `USB_DEV_W'b0;
+else if (state_q == STATE_RX_TOKEN2 && data_ready_w)
+    token_dev_q <= data_w[6:0];
+else if (!enable_i)
+    token_dev_q <= `USB_DEV_W'b0;
+
+assign token_addr_o = token_dev_q;
+
+//-----------------------------------------------------------------
+// Token: Endpoint
+//-----------------------------------------------------------------
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    token_ep_q      <= `USB_EP_W'b0;
+else if (state_q == STATE_RX_TOKEN2 && data_ready_w)
+    token_ep_q[0]   <= data_w[7];
+else if (state_q == STATE_RX_TOKEN3 && data_ready_w)
+    token_ep_q[3:1] <= data_w[2:0];
+else if (!enable_i)
+    token_ep_q      <= `USB_EP_W'b0;
+
+assign token_ep_o = token_ep_q;
+assign token_crc_err_o = 1'b0;
+
+wire [7:0] input_data_w  = data_w;
+wire       input_ready_w = state_q == STATE_RX_DATA && data_ready_w && !crc_byte_w;
+
+//-----------------------------------------------------------------
+// CRC16: Generate CRC16 on incoming data bytes
+//-----------------------------------------------------------------
+reg [15:0]  crc_sum_q;
+wire [15:0] crc_out_w;
+reg         crc_err_q;
+
+usbf_crc16
+u_crc16
+(
+    .crc_in_i(crc_sum_q),
+    .din_i(data_w),
+    .crc_out_o(crc_out_w)
+);
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    crc_sum_q   <= 16'hFFFF;
+else if (state_q == STATE_RX_IDLE)
+    crc_sum_q   <= 16'hFFFF;
+else if (data_ready_w)
+    crc_sum_q   <= crc_out_w;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    crc_err_q   <= 1'b0;
+else if (state_q == STATE_RX_IDLE)
+    crc_err_q   <= 1'b0;
+else if (state_q == STATE_RX_DATA_COMPLETE && next_state_r == STATE_RX_IDLE)
+    crc_err_q   <= (crc_sum_q != 16'hB001);
+
+assign data_crc_err_o = crc_err_q;
+
+reg data_complete_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    data_complete_q   <= 1'b0;
+else if (state_q == STATE_RX_DATA_COMPLETE && next_state_r == STATE_RX_IDLE)
+    data_complete_q   <= 1'b1;
+else
+    data_complete_q   <= 1'b0;
+
+assign data_complete_o = data_complete_q;
+
+reg data_zlp_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    data_zlp_q   <= 1'b0;
+else if (state_q == STATE_RX_IDLE && next_state_r == STATE_RX_DATA)
+    data_zlp_q   <= 1'b1;
+else if (input_ready_w)
+    data_zlp_q   <= 1'b0;
+
+//-----------------------------------------------------------------
+// Data Output
+//-----------------------------------------------------------------
+reg        valid_q;
+reg        last_q;
+reg [7:0]  data_q;
+reg        mask_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    valid_q  <= 1'b0;
+    data_q   <= 8'b0;
+    mask_q   <= 1'b0;
+    last_q   <= 1'b0;
+end
+else
+begin
+    valid_q  <= input_ready_w || ((state_q == STATE_RX_DATA) && crc_byte_w && data_zlp_q);
+    data_q   <= input_data_w;
+    mask_q   <= input_ready_w;
+    last_q   <= (state_q == STATE_RX_DATA) && crc_byte_w;
+end
+
+// Data
+assign data_valid_o = valid_q;
+assign data_strb_o  = mask_q;
+assign data_o       = data_q;
+assign data_last_o  = last_q | crc_byte_w;
+
+
+endmodule

fpga/usb/usb_serial/src_v/usbf_sie_tx.v

@@ -0,0 +1,345 @@
+//-----------------------------------------------------------------
+//                       USB Serial Port
+//                            V0.1
+//                     Ultra-Embedded.com
+//                       Copyright 2020
+//
+//                 Email: admin@ultra-embedded.com
+//
+//                         License: LGPL
+//-----------------------------------------------------------------
+//
+// This source file may be used and distributed without         
+// restriction provided that this copyright statement is not    
+// removed from the file and that any derivative work contains  
+// the original copyright notice and the associated disclaimer. 
+//
+// This source file is free software; you can redistribute it   
+// and/or modify it under the terms of the GNU Lesser General   
+// Public License as published by the Free Software Foundation; 
+// either version 2.1 of the License, or (at your option) any   
+// later version.
+//
+// This source is distributed in the hope that it will be       
+// useful, but WITHOUT ANY WARRANTY; without even the implied   
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+// PURPOSE.  See the GNU Lesser General Public License for more 
+// details.
+//
+// You should have received a copy of the GNU Lesser General    
+// Public License along with this source; if not, write to the 
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// Boston, MA  02111-1307  USA
+//-----------------------------------------------------------------
+
+//-----------------------------------------------------------------
+//                          Generated File
+//-----------------------------------------------------------------
+
+module usbf_sie_tx
+(
+    // Inputs
+     input           clk_i
+    ,input           rst_i
+    ,input           enable_i
+    ,input           chirp_i
+    ,input           utmi_txready_i
+    ,input           tx_valid_i
+    ,input  [  7:0]  tx_pid_i
+    ,input           data_valid_i
+    ,input           data_strb_i
+    ,input  [  7:0]  data_i
+    ,input           data_last_i
+
+    // Outputs
+    ,output [  7:0]  utmi_data_o
+    ,output          utmi_txvalid_o
+    ,output          tx_accept_o
+    ,output          data_accept_o
+);
+
+
+
+//-----------------------------------------------------------------
+// Defines:
+//-----------------------------------------------------------------
+`include "usbf_defs.v"
+
+localparam STATE_W                       = 3;
+localparam STATE_TX_IDLE                 = 3'd0;
+localparam STATE_TX_PID                  = 3'd1;
+localparam STATE_TX_DATA                 = 3'd2;
+localparam STATE_TX_CRC1                 = 3'd3;
+localparam STATE_TX_CRC2                 = 3'd4;
+localparam STATE_TX_DONE                 = 3'd5;
+localparam STATE_TX_CHIRP                = 3'd6;
+
+reg [STATE_W-1:0] state_q;
+reg [STATE_W-1:0] next_state_r;
+
+//-----------------------------------------------------------------
+// Request Type
+//-----------------------------------------------------------------
+reg data_pid_q;
+reg data_zlp_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    data_pid_q <= 1'b0;
+    data_zlp_q <= 1'b0;
+end
+else if (!enable_i)
+begin
+    data_pid_q <= 1'b0;
+    data_zlp_q <= 1'b0;
+end
+else if (tx_valid_i && tx_accept_o)
+begin
+    case (tx_pid_i)
+
+    `PID_MDATA, `PID_DATA2, `PID_DATA0, `PID_DATA1:
+    begin
+        data_pid_q <= 1'b1;
+        data_zlp_q <= data_valid_i && (data_strb_i == 1'b0) && data_last_i;
+    end
+
+    default :
+    begin
+        data_pid_q <= 1'b0;
+        data_zlp_q <= 1'b0;
+    end
+    endcase
+end
+else if (next_state_r == STATE_TX_CRC1)
+begin
+    data_pid_q <= 1'b0;
+    data_zlp_q <= 1'b0;
+end
+
+assign tx_accept_o = (state_q == STATE_TX_IDLE);
+
+//-----------------------------------------------------------------
+// Next state
+//-----------------------------------------------------------------
+always @ *
+begin
+    next_state_r = state_q;
+
+    //-----------------------------------------
+    // State Machine
+    //-----------------------------------------
+    case (state_q)
+
+    //-----------------------------------------
+    // IDLE
+    //-----------------------------------------
+    STATE_TX_IDLE :
+    begin
+        if (chirp_i)
+            next_state_r  = STATE_TX_CHIRP;
+        else if (tx_valid_i)
+            next_state_r  = STATE_TX_PID;
+    end
+
+    //-----------------------------------------
+    // TX_PID
+    //-----------------------------------------
+    STATE_TX_PID :
+    begin
+        // Data accepted
+        if (utmi_txready_i)
+        begin
+            if (data_zlp_q)
+                next_state_r = STATE_TX_CRC1;
+            else if (data_pid_q)
+                next_state_r = STATE_TX_DATA;
+            else
+                next_state_r = STATE_TX_DONE;
+        end
+    end
+
+    //-----------------------------------------
+    // TX_DATA
+    //-----------------------------------------
+    STATE_TX_DATA :
+    begin
+        // Data accepted
+        if (utmi_txready_i)
+        begin
+            // Generate CRC16 at end of packet
+            if (data_last_i)
+                next_state_r  = STATE_TX_CRC1;
+        end
+    end
+
+    //-----------------------------------------
+    // TX_CRC1 (first byte)
+    //-----------------------------------------
+    STATE_TX_CRC1 :
+    begin
+        // Data sent?
+        if (utmi_txready_i)
+            next_state_r  = STATE_TX_CRC2;
+    end
+
+    //-----------------------------------------
+    // TX_CRC (second byte)
+    //-----------------------------------------
+    STATE_TX_CRC2 :
+    begin
+        // Data sent?
+        if (utmi_txready_i)
+            next_state_r  = STATE_TX_DONE;
+    end
+
+    //-----------------------------------------
+    // TX_DONE
+    //-----------------------------------------
+    STATE_TX_DONE :
+    begin
+        // Data sent?
+        if (!utmi_txvalid_o || utmi_txready_i)
+            next_state_r  = STATE_TX_IDLE;
+    end
+
+    //-----------------------------------------
+    // TX_CHIRP
+    //-----------------------------------------
+    STATE_TX_CHIRP :
+    begin
+        if (!chirp_i)
+            next_state_r  = STATE_TX_IDLE;
+    end
+
+    default :
+       ;
+
+    endcase
+
+    // USB reset but not chirping...
+    if (!enable_i && !chirp_i)
+        next_state_r  = STATE_TX_IDLE;
+end
+
+// Update state
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    state_q   <= STATE_TX_IDLE;
+else
+    state_q   <= next_state_r;
+
+//-----------------------------------------------------------------
+// Data Input
+//-----------------------------------------------------------------
+reg       input_valid_r;
+reg [7:0] input_byte_r;
+reg       input_last_r;
+always @ *
+begin
+    input_valid_r = data_strb_i & data_pid_q;
+    input_byte_r  = data_i;
+    input_last_r  = data_last_i;
+end
+
+reg data_accept_r;
+always @ *
+begin
+    if (state_q == STATE_TX_DATA)
+        data_accept_r = utmi_txready_i;
+    else if (state_q == STATE_TX_PID && data_zlp_q)
+        data_accept_r = utmi_txready_i;
+    else
+        data_accept_r = 1'b0;
+end
+
+assign data_accept_o = data_accept_r;
+
+//-----------------------------------------------------------------
+// CRC16: Generate CRC16 on outgoing data
+//-----------------------------------------------------------------
+reg [15:0]  crc_sum_q;
+wire [15:0] crc_out_w;
+reg         crc_err_q;
+
+usbf_crc16
+u_crc16
+(
+    .crc_in_i(crc_sum_q),
+    .din_i(utmi_data_o),
+    .crc_out_o(crc_out_w)
+);
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+    crc_sum_q   <= 16'hFFFF;
+else if (state_q == STATE_TX_IDLE)
+    crc_sum_q   <= 16'hFFFF;
+else if (state_q == STATE_TX_DATA && utmi_txvalid_o && utmi_txready_i)
+    crc_sum_q   <= crc_out_w;
+
+//-----------------------------------------------------------------
+// Output
+//-----------------------------------------------------------------
+reg       valid_q;
+reg [7:0] data_q;
+
+always @ (posedge clk_i or posedge rst_i)
+if (rst_i)
+begin
+    valid_q <= 1'b0;
+    data_q  <= 8'b0;
+end
+else if (!enable_i)
+begin
+    valid_q <= 1'b0;
+    data_q  <= 8'b0;
+end
+else if (tx_valid_i && tx_accept_o)
+begin
+    valid_q <= 1'b1;
+    data_q  <= tx_pid_i;
+end
+else if (utmi_txready_i)
+begin
+    valid_q <= 1'b0;
+    data_q  <= 8'b0;
+end
+
+reg       utmi_txvalid_r;
+reg [7:0] utmi_data_r;
+
+always @ *
+begin
+    if (state_q == STATE_TX_CHIRP)
+    begin
+        utmi_txvalid_r = 1'b1;
+        utmi_data_r    = 8'b0;
+    end
+    else if (state_q == STATE_TX_CRC1)
+    begin
+        utmi_txvalid_r = 1'b1;
+        utmi_data_r    = crc_sum_q[7:0] ^ 8'hFF;
+    end
+    else if (state_q == STATE_TX_CRC2)
+    begin
+        utmi_txvalid_r = 1'b1;
+        utmi_data_r    = crc_sum_q[15:8] ^ 8'hFF;
+    end
+    else if (state_q == STATE_TX_DATA)
+    begin
+        utmi_txvalid_r = data_valid_i;
+        utmi_data_r    = data_i;
+    end
+    else
+    begin
+        utmi_txvalid_r = valid_q;
+        utmi_data_r    = data_q;
+    end
+end
+
+assign utmi_txvalid_o = utmi_txvalid_r;
+assign utmi_data_o    = utmi_data_r;
+
+
+endmodule

fw/boot.mif

@@ -15,7 +15,7 @@ CONTENT BEGIN
 0008 : 0001210B;
 0009 : 200DF413;
 000A : 00040863;
-000B : 05B010EF;
+000B : 1E7010EF;
 000C : 408D8DB3;
 000D : 060D8263;
 000E : 00000493;
@@ -44,21 +44,21 @@ CONTENT BEGIN
 0025 : FA0D94E3;
 0026 : 30200073;
 0027 : 00000000;
-0028 : 000005B8;
-0029 : 000005B8;
-002A : 000005B8;
-002B : 0000051C;
-002C : 000005B8;
-002D : 00000A1E;
-002E : 000005B8;
-002F : 000005B8;
-0030 : 000005B8;
-0031 : 00001886;
-0032 : 41016700;
+0028 : 000006E6;
+0029 : 00000588;
+002A : 0000057C;
+002B : 0000055A;
+002C : 000006E6;
+002D : 00000B4C;
+002E : 000006E6;
+002F : 000006E6;
+0030 : 000006E6;
+0031 : 00001A12;
+0032 : 41016720;
 0033 : 00000040;
 0034 : FFFFFFFF;
 0035 : FFFFFFFF;
-0036 : 00007240;
+0036 : 0000741C;
 0037 : 00000000;
 0038 : 00000000;
 0039 : 00000000;
@@ -320,7 +320,7 @@ CONTENT BEGIN
 0139 : 0040006F;
 013A : C6061141;
 013B : C226C422;
-013C : 4283283D;
+013C : 42832055;
 013D : 86630E40;
 013E : 10970002;
 013F : 80E74000;
@@ -329,7016 +329,7135 @@ CONTENT BEGIN
 0142 : 0810878B;
 0143 : 0F004303;
 0144 : 00030363;
-0145 : 10EF2925;
-0146 : B7ED0E70;
-0147 : 0E800293;
-0148 : 0002A703;
-0149 : 00170313;
-014A : 0062A023;
-014B : 11418082;
-014C : 57FDC606;
-014D : 80F02423;
-014E : FD900093;
-014F : 0610078B;
-0150 : C0102773;
-0151 : 0EE02623;
-0152 : 078B535D;
-0153 : 10EF0660;
-0154 : 65712D40;
-0155 : 20050513;
-0156 : 639D2055;
-0157 : B2438513;
-0158 : 258328E9;
-0159 : 46378000;
-015A : 06933858;
-015B : 846314D6;
-015C : 6F1D02D5;
-015D : AE8F0513;
-015E : 22D120C9;
-015F : 1BC020EF;
-0160 : 735010EF;
-0161 : 6FE010EF;
-0162 : 80002423;
-0163 : B8002623;
-0164 : 014140B2;
-0165 : 28038082;
-0166 : 6E9D8040;
-0167 : B00E8513;
-0168 : 01085893;
-0169 : 01081E13;
-016A : 010E5693;
-016B : 0FF8F613;
-016C : 01885593;
-016D : B7D1287D;
-016E : 95334785;
-016F : 429300A7;
-0170 : 050BFFF5;
-0171 : 80820655;
-0172 : 0C800293;
-0173 : A503872A;
-0174 : 66B70002;
-0175 : 83934141;
-0176 : 03337006;
-0177 : FC6300E5;
-0178 : 11410063;
-0179 : 50EFC606;
-017A : 45B11890;
-017B : 40B2C10C;
-017C : 0141557D;
-017D : A0238082;
-017E : 80820062;
-017F : 3216D737;
-0180 : 0313478D;
-0181 : 82B39487;
-0182 : 353302A7;
-0183 : 83B30265;
-0184 : 859300A2;
-0185 : 2223FFF3;
-0186 : 808290B0;
-0187 : 90802783;
-0188 : 0107F293;
-0189 : FE029CE3;
-018A : 15634329;
-018B : 43B50065;
-018C : 90700023;
-018D : 90A00023;
-018E : 11418082;
-018F : C606C422;
-0190 : 4503842A;
-0191 : E5090004;
-0192 : 442240B2;
-0193 : 80820141;
-0194 : 37E90405;
-0195 : 7175B7FD;
-0196 : 86AE862A;
-0197 : 0593850A;
-0198 : C7060800;
-0199 : 227050EF;
-019A : 3FC1850A;
-019B : 614940BA;
-019C : 71398082;
-019D : 104CD22E;
-019E : D432CE06;
-019F : D83AD636;
-01A0 : DC42DA3E;
-01A1 : C62EDE46;
-01A2 : 40F237F9;
-01A3 : 80826121;
-01A4 : 06400793;
-01A5 : 02F57533;
-01A6 : 52B34729;
-01A7 : 73B302E5;
-01A8 : 931302E5;
-01A9 : 05B30042;
-01AA : F5130073;
-01AB : 80820FF5;
-01AC : C6061141;
-01AD : C226C422;
-01AE : 03400793;
-01AF : 242366C1;
-01B0 : 4F45A8F0;
-01B1 : 08000E13;
-01B2 : F8668E93;
-01B3 : A8400613;
-01B4 : 00062083;
-01B5 : 0400F293;
-01B6 : 04028263;
-01B7 : 08000413;
-01B8 : 0804078B;
-01B9 : 04936335;
-01BA : 0393A800;
-01BB : A0230803;
-01BC : 078B0074;
-01BD : 42080804;
-01BE : 08057593;
-01BF : C99D4501;
-01C0 : 0593671D;
-01C1 : 05130680;
-01C2 : 37A5B867;
-01C3 : 0804040B;
-01C4 : 08936841;
-01C5 : A023F848;
-01C6 : A8210114;
-01C7 : 080E078B;
-01C8 : A9D02023;
-01C9 : 13E31F7D;
-01CA : 6F9DFA0F;
-01CB : B6EF8513;
-01CC : 557D3789;
-01CD : 442240B2;
-01CE : 01414492;
-01CF : 71798082;
-01D0 : 37BDD606;
-01D1 : 20051163;
-01D2 : 08000793;
-01D3 : 0807870B;
-01D4 : A8000713;
-01D5 : 08200693;
-01D6 : 878BC314;
-01D7 : 60B50807;
-01D8 : 18008293;
-01D9 : 00572023;
-01DA : 08000313;
-01DB : F0000813;
-01DC : 070B4399;
-01DD : 08930803;
-01DE : A023A800;
-01DF : 060B0108;
-01E0 : 45830803;
-01E1 : 0070A850;
-01E2 : 00A60E33;
-01E3 : 00BE0023;
-01E4 : 10E30505;
-01E5 : 068BFE75;
-01E6 : 05130803;
-01E7 : A023F840;
-01E8 : 078B00A8;
-01E9 : 4F830803;
-01EA : 430300C1;
-01EB : 40A900D1;
-01EC : 004FD793;
-01ED : 00435813;
-01EE : 02178733;
-01EF : A8504E83;
-01F0 : 00FFF693;
-01F1 : 00F37893;
-01F2 : 0FFEFF13;
-01F3 : CA026791;
-01F4 : CE02CC02;
-01F5 : 021803B3;
-01F6 : 00D702B3;
-01F7 : 0012D513;
-01F8 : 00F29713;
-01F9 : 00E14283;
-01FA : 01F57E93;
-01FB : 00F766B3;
-01FC : 00D11C23;
-01FD : 0402F313;
-01FE : 0042D813;
-01FF : 011385B3;
-0200 : 03F5F613;
-0201 : 00561E13;
-0202 : 01DE6FB3;
-0203 : 01F11A23;
-0204 : 00F2F393;
-0205 : 12030463;
-0206 : 00187593;
-0207 : 02158633;
-0208 : 08B34E2D;
-0209 : 53630076;
-020A : 18D1011E;
-020B : 0202F513;
-020C : 08B1C111;
-020D : 01014E83;
-020E : 4F8346A9;
-020F : D7130111;
-0210 : 07B3004E;
-0211 : F29302D7;
-0212 : DE9300FE;
-0213 : F713004F;
-0214 : 03B7001E;
-0215 : 65C1001F;
-0216 : FFF58613;
-0217 : FE3308AE;
-0218 : 05B700C8;
-0219 : 83330200;
-021A : 07B30057;
-021B : F29302D7;
-021C : 181300FF;
-021D : 70B30103;
-021E : 03B70078;
-021F : E53301E0;
-0220 : 0EB701C0;
-0221 : 0FE2FE00;
-0222 : 80058613;
-0223 : 7FFE8713;
-0224 : 00578333;
-0225 : 01531813;
-0226 : 004F5313;
-0227 : 02D306B3;
-0228 : 007870B3;
-0229 : 001568B3;
-022A : 7F134552;
-022B : D09300FF;
-022C : FE33418F;
-022D : 77B300C8;
-022E : D89300E5;
-022F : 62B341F0;
-0230 : 883300FE;
-0231 : 739301E6;
-0232 : F6130FF8;
-0233 : 8E130648;
-0234 : 05330143;
-0235 : 15FD01C6;
-0236 : 00B2F733;
-0237 : 01951E93;
-0238 : 01815283;
-0239 : 01D767B3;
-023A : 1223CA3E;
-023B : 20238850;
-023C : 435288F0;
-023D : 6E9D4862;
-023E : 00535093;
-023F : 01F37693;
-0240 : 00F85393;
-0241 : 03F0F793;
-0242 : 9F1350B2;
-0243 : 55130016;
-0244 : FF930193;
-0245 : 58930013;
-0246 : 5E1300B3;
-0247 : 56130103;
-0248 : 05930153;
-0249 : 68337BC5;
-024A : F71301FF;
-024B : 769301F8;
-024C : 8A3D01FE;
-024D : BADE8513;
-024E : BB256145;
-024F : 021800B3;
-0250 : 007088B3;
-0251 : 50B2BDC5;
-0252 : 80826145;
-0253 : 08237179;
-0254 : D6060E00;
-0255 : 2403D422;
-0256 : 20838800;
-0257 : 75138840;
-0258 : D31301F4;
-0259 : 129300F0;
-025A : 73930015;
-025B : E5330013;
-025C : CC060072;
-025D : 3B29CA22;
-025E : 00545593;
-025F : 00A10623;
-0260 : 03F5F513;
-0261 : 56133331;
-0262 : 06A300B4;
-0263 : 751300A1;
-0264 : 39FD01F6;
-0265 : 01045693;
-0266 : 00A10723;
-0267 : 01F6F513;
-0268 : 000107A3;
-0269 : 571331F5;
-026A : 08230154;
-026B : 751300A1;
-026C : 39F900F7;
-026D : 01945813;
-026E : 00A108A3;
-026F : FEC80513;
-0270 : 092339C1;
-0271 : 31ED00A1;
-0272 : 0893E539;
-0273 : 870B0800;
-0274 : 0E130808;
-0275 : 20230800;
-0276 : 4E99A910;
-0277 : 080E078B;
-0278 : 00C10F13;
-0279 : 00AF0FB3;
-027A : 000FC783;
-027B : A8000293;
-027C : 94130505;
-027D : 60930087;
-027E : A0230804;
-027F : 1FE30012;
-0280 : 070BFDD5;
-0281 : 4503080E;
-0282 : 13130121;
-0283 : 63930085;
-0284 : A0230843;
-0285 : 50B20072;
-0286 : 61455422;
-0287 : 02938082;
-0288 : A7030F40;
-0289 : 06930002;
-028A : A0230017;
-028B : C70D00D2;
-028C : 0E134805;
-028D : 01630F80;
-028E : 23F30507;
-028F : 2503C010;
-0290 : 0613000E;
-0291 : 08130200;
-0292 : 85B3FDF0;
-0293 : 222340A3;
-0294 : 078B00BE;
-0295 : 80820706;
-0296 : 40000337;
-0297 : 00C02583;
-0298 : 00030393;
-0299 : 98702023;
-029A : 22236605;
-029B : 031398B0;
-029C : 24230B86;
-029D : 80829860;
-029E : C0102EF3;
-029F : 0E002F83;
-02A0 : 400012B7;
-02A1 : 0B828713;
-02A2 : 41FE87B3;
-02A3 : 00FE2023;
-02A4 : 98E02023;
-02A5 : 222366AD;
-02A6 : 83139800;
-02A7 : BFD16406;
-02A8 : 04000793;
-02A9 : 0807870B;
-02AA : A6A00223;
-02AB : 0807870B;
-02AC : A2B02E23;
-02AD : 0807870B;
-02AE : A1404703;
-02AF : 0FF77293;
-02B0 : 0807878B;
-02B1 : 042345C1;
-02B2 : 0313A250;
-02B3 : 068B0400;
-02B4 : 45030803;
-02B5 : 1393A270;
-02B6 : D5130185;
-02B7 : 54634183;
-02B8 : 15FD0005;
-02B9 : 8082F5ED;
-02BA : 15E9C291;
-02BB : 07934721;
-02BC : 08930400;
-02BD : 03130FE0;
-02BE : 880B0FD0;
-02BF : 48030807;
-02C0 : 7E13A670;
-02C1 : 0A630FF8;
-02C2 : 64630118;
-02C3 : 177D01C3;
-02C4 : 167DC319;
-02C5 : 557DF27D;
-02C6 : 72938082;
-02C7 : 862A0015;
-02C8 : 00028B63;
-02C9 : 00150613;
-02CA : 0807878B;
-02CB : A2704383;
-02CC : 002315FD;
-02CD : 05130075;
-02CE : 078B0400;
-02CF : 47830805;
-02D0 : 7E93A270;
-02D1 : 8A630026;
-02D2 : 070B000E;
-02D3 : 5F830805;
-02D4 : 0609A2A0;
-02D5 : 1F2315F9;
-02D6 : 0793FFF6;
-02D7 : 878B0400;
-02D8 : 57830807;
-02D9 : 8E2EA2A0;
-02DA : 04000293;
-02DB : 00C58833;
-02DC : 888B4715;
-02DD : 23030802;
-02DE : 08B3A2C0;
-02DF : 1E7141C8;
-02E0 : 0068A023;
-02E1 : FFC747E3;
-02E2 : FFA58393;
-02E3 : FFC3F513;
-02E4 : 00C50F33;
-02E5 : 0023DE93;
-02E6 : 006F0813;
-02E7 : 0802850B;
-02E8 : 8E3357F1;
-02E9 : 5F8302FE;
-02EA : 8642A200;
-02EB : 04000293;
-02EC : 01FF1223;
-02ED : 05B39E2E;
-02EE : 156301CF;
-02EF : 05930AB6;
-02F0 : 8633FFAE;
-02F1 : CAAD0105;
-02F2 : 04000293;
-02F3 : 0802870B;
-02F4 : A6D00023;
-02F5 : 0802870B;
-02F6 : A2604683;
-02F7 : 00D60023;
-02F8 : 0802870B;
-02F9 : A2002823;
-02FA : 0802870B;
-02FB : A2604803;
-02FC : 010600A3;
-02FD : 0802870B;
-02FE : A2604703;
-02FF : 00E60123;
-0300 : 0802870B;
-0301 : A2604303;
-0302 : 006601A3;
-0303 : 0802870B;
-0304 : A2604883;
-0305 : 01160223;
-0306 : 0802870B;
-0307 : A1404383;
-0308 : 0FF3FE93;
-0309 : 0802868B;
-030A : A3D00023;
-030B : 0802878B;
-030C : A2604503;
-030D : 00A602A3;
-030E : 04000F13;
-030F : 080F070B;
-0310 : A1205F83;
-0311 : 010F9793;
-0312 : 0107D593;
-0313 : 020F8463;
-0314 : C6061141;
-0315 : 8513609D;
-0316 : 3C21BD60;
-0317 : 557D40B2;
-0318 : 80820141;
-0319 : 0802850B;
-031A : A2604703;
-031B : 0FA30605;
-031C : B7A1FEE6;
-031D : 080F078B;
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-1BA3 : 00008000;
-1BA4 : 00C04000;
-1BA5 : 400010B8;
-1BA6 : FFFFFFFF;
-1BA7 : 00000000;
-1BA8 : 00000000;
-1BA9 : 38434241;
-1BAA : 41003030;
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-1BAC : 6F282000;
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-1BEE : 000071EC;
-1BEF : 00006FA4;
-1BF0 : 00006FAE;
-1BF1 : 00006FAC;
-1BF2 : 00000000;
-1BF3 : 05002D00;
-1BF4 : 00100228;
-1BF5 : 00006F6D;
-1BF6 : 0A002C02;
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-1BF8 : 0000666D;
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-1C54 : 33323130;
-1C55 : 37363534;
-1C56 : 62613938;
-1C57 : 66656463;
-1C58 : 00000000;
-1C59 : 000065C0;
-1C5A : 000065D6;
-1C5B : 00006594;
-1C5C : 00006594;
-1C5D : 00006594;
-1C5E : 00006594;
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-1C61 : 00006594;
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-1C64 : 00006766;
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-1C68 : 00006594;
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-1C6C : 00006594;
-1C6D : 00006594;
-1C6E : 00006704;
-1C6F : 00000001;
-1C70 : 00000000;
-1C71 : 00000000;
-1C72 : 00000000;
-1C73 : 00000000;
-1C74 : 00000000;
-1C75 : 00000000;
-1C76 : 00000000;
-1C77 : 00000000;
-1C78 : 00000000;
-1C79 : 00000000;
-1C7A : 00000000;
-1C7B : 6362612F;
-1C7C : 6B736964;
-1C7D : 3030382E;
-1C7E : 0000002F;
-1C7F : 00000000;
-1C80 : 00000000;
-1C81 : 00000000;
-1C82 : 00000000;
-1C83 : 00000105;
-1C84 : 00007FBF;
-1C85 : 00000000;
-1C86 : D3030300;
-1C87 : 0000257E;
-1C88 : 00000000;
-1C89 : 000025A2;
-1C8A : 00000000;
-1C8B : 00000000;
-1C8C : 00000000;
-1C8D : 00002590;
-1C8E : 00000000;
-1C8F : 00000000;
-1C90 : 00000000;
-1C91 : 00000000;
-1C92 : 00000000;
-1C93 : 00000000;
-1C94 : 00000000;
-1C95 : 00000000;
-1C96 : 00000000;
-1C97 : 00000000;
-1C98 : 00000000;
-1C99 : 00000000;
-1C9A : 00000000;
-1C9B : 00000000;
-1C9C : 00000000;
-1C9D : 00000000;
-1C9E : 00000000;
-1C9F : 00000000;
-1CA0 : 00000000;
-1CA1 : 00000000;
-1CA2 : 00000000;
-1CA3 : 00000000;
-1CA4 : 00000000;
-1CA5 : 00000000;
-1CA6 : 00000000;
-1CA7 : 00000000;
-[1CA8..1FFF] : 00;
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+1D03 : 00000000;
+1D04 : 0000271C;
+1D05 : 00000000;
+1D06 : 00000000;
+1D07 : 00000000;
+1D08 : 00000000;
+1D09 : 00000000;
+1D0A : 00000000;
+1D0B : 00000000;
+1D0C : 00000000;
+1D0D : 00000000;
+1D0E : 00000000;
+1D0F : 00000000;
+1D10 : 00000000;
+1D11 : 00000000;
+1D12 : 00000000;
+1D13 : 00000000;
+1D14 : 00000000;
+1D15 : 00000000;
+1D16 : 00000000;
+1D17 : 00000000;
+1D18 : 00000000;
+1D19 : 00000000;
+1D1A : 00000000;
+1D1B : 00000000;
+1D1C : 00000000;
+1D1D : 00000000;
+1D1E : 00000000;
+[1D1F..1FFF] : 00;
 END;

fw/diskcache.c

@@ -39,7 +39,7 @@ static struct cache_block __dram_noinit disk_cache[CACHE_BLOCKS];
 static struct dll lru_list;
 static struct dll free_list;
 
-static void disk_cache_init(void)
+void disk_cache_init(void)
 {
     struct cache_block *bp, *bep;
     struct dll *hp, *hep;
@@ -188,13 +188,14 @@ static struct cache_block *disk_cache_get(block_t block, bool do_read)
 
 DSTATUS disk_initialize(BYTE drive)
 {
-    DSTATUS status;
+    DSTATUS status, old_status;
 
     if (drive != 0)
 	return STA_NOINIT | STA_NODISK;
 
+    old_status = sdc.status;
     status = sdcard_init();
-    if (!(status & STA_NOINIT))
+    if ((status ^ old_status) & STA_NOINIT)
 	disk_cache_init();
 
     return sdc.fsstatus = status;
@@ -203,7 +204,10 @@ DSTATUS disk_initialize(BYTE drive)
 DRESULT disk_ioctl(BYTE drive, BYTE command, void *buffer)
 {
     if (drive != 0)
-	return STA_NOINIT;
+	return STA_NOINIT | STA_NODISK;
+
+    if (sdc.status & STA_NOINIT)
+	return RES_NOTRDY;
 
     switch (command) {
     case CTRL_SYNC:
@@ -227,6 +231,9 @@ DRESULT disk_read(BYTE drive, BYTE *buffer,
 {
     (void)drive;
 
+    if (sdc.status & STA_NOINIT)
+	return RES_NOTRDY;
+
     if (!sectorcount)
 	return RES_OK;
 
@@ -256,6 +263,9 @@ DRESULT disk_write(BYTE drive, const BYTE *buffer, LBA_t sectornumber,
 {
     (void)drive;
 
+    if (sdc.status & STA_NOINIT)
+	return RES_NOTRDY;
+
     if (!sectorcount)
 	return RES_OK;
 

fw/fw.h

@@ -80,6 +80,7 @@ extern void write_rtc(void);
 extern bool do_write_rtc;
 extern void rtc_abc_init(void);
 extern void rtc_abc_io_poll(void);
+extern void disk_cache_init(void);
 
 extern uint32_t romcopy_time[2];
 

fw/io.h

@@ -6,6 +6,7 @@
 #include <stdbool.h>
 #include "ioregs.h"
 #include "picorv32.h"
+#include "irq.h"
 
 static inline void pause(void)
 {
@@ -74,5 +75,10 @@ static inline void i2c_set_speed(unsigned int khz)
     I2C_DIVISOR = ((CPU_HZ/4000)-1)/khz;
 }
 
+static inline void wait_romcopy_done(void)
+{
+    while (~irqmask() & (1 << ROMCOPY_IRQ))
+	pause();
+}
 
 #endif /* IO_H */

fw/main.c

@@ -4,7 +4,7 @@
 #include "sys.h"
 #include "console.h"
 
-volatile bool dont_gc;		/* Keep things from linker gc */
+volatile bool dont_gc = false;	/* Keep things from linker gc */
 
 void main(void)
 {

fw/sdcard.c

@@ -76,7 +76,8 @@ enum sdcard_acmd {
 };
 
 struct sdcard_info sdc = {
-    .status = STA_NOINIT
+    .status   = STA_NOINIT,
+    .fsstatus = STA_NOINIT
 };
 
 /* < 0 if it should be left on, 0 for off, > 0 for off after timeout */
@@ -627,9 +628,11 @@ static void sdcard_try_high_speed(void)
 static DSTATUS sdcard_present_check(void)
 {
     /* Send CRC enable command; only care about getting any response at all */
-    if (!(sdc.status & STA_NOINIT) &&
-	sdcard_send_cmd(CMD_CRC_ON_OFF, 0x0001) < 0) {
-	sdc.status = STA_NOINIT | STA_NODISK;
+    if (sdc.status & STA_NOINIT)
+	return sdc.status;
+
+    if (sdcard_send_cmd(CMD_CRC_ON_OFF, 0x0001) < 0) {
+	sdc.fsstatus = sdc.status = STA_NOINIT | STA_NODISK;
 	set_led(LED_SDCARD, false);
 	con_puts("sdcard: card removed\n");
     }
@@ -646,6 +649,7 @@ DSTATUS sdcard_present_poll(void)
     if ((now - last_disk_poll) < SDCARD_PRESENT_POLL)
 	return sdc.status;
 
+    last_disk_poll = now;
     return sdcard_present_check();
 }
 
@@ -661,6 +665,9 @@ DSTATUS sdcard_init(void)
     uint32_t now = timer_count();
     DSTATUS old_sdc_status = sdc.status;
 
+    /* So we can wait for the ready condition */
+    SDCARD_CTL_IRQEN = SDCARD_IRQ_READY;
+
     if (!(old_sdc_status & STA_NOINIT)) {
 	return sdcard_present_check();
     }
@@ -671,11 +678,8 @@ DSTATUS sdcard_init(void)
     }
     last_disk_retry = now;
 
-    /* So we can wait for the ready condition */
-    SDCARD_CTL_IRQEN = SDCARD_IRQ_READY;
-
     memset(&sdc, 0, sizeof sdc);
-    sdc.status = STA_NOINIT | STA_NODISK;
+    sdc.fsstatus = sdc.status = STA_NOINIT | STA_NODISK;
 
 #if 0
     status = /* Check card detect if present */

fw/system.c

@@ -11,9 +11,8 @@ IRQHANDLER(sysclock)
 
     count++;
     timer_irq_count = count;
-#ifdef TEST
-    set_leds(count >> 3); /* 4 Hz */
-#endif
+    if (!(count & ((1U << TIMER_SHIFT)-1)))
+	CON_DATA = '.';		/* Console heartbeat */
 }
 
 static no_return killed(const char *how, size_t pc)
@@ -25,16 +24,18 @@ static no_return killed(const char *how, size_t pc)
     reset();
 }
 
-IRQHANDLER(BUSERR)
+IRQHANDLER(buserr)
 {
     killed("misaligned", pc);
 }
 
-IRQHANDLER(EBREAK)
+IRQHANDLER(ebreak)
 {
     killed("invalid instruction", pc);
 }
 
+volatile uint32_t __dram_bss test_dram[8];
+
 uint32_t timer_irq_start;
 void init(void)
 {
@@ -46,21 +47,27 @@ void init(void)
 #endif
 	"firmware compiled on: " __DATE__ " " __TIME__ "\n";
 
-    set_leds(-1U);
+    timer_irq_start = rdtime();
+
+    /* Start ROM copy engine, unmask timer and fatal exceptions */
+    unmask_irqs((1U << ROMCOPY_IRQ)|(1U << EBREAK_IRQ)|
+		(1U << BUSERR_IRQ)|(1U << SYSCLOCK_IRQ));
 
-    /* Start ROM copy engine and unmask fatal exceptions */
-    unmask_irqs((1U << ROMCOPY_IRQ)|(1U << EBREAK_IRQ)|(1U << BUSERR_IRQ));
+    set_leds(7);
+    con_set_baudrate(115200);
+    con_puts(hello);
+    con_flush();
 
     /* Enable internal timer */
-    timer_irq_start = rdtime();
     unmask_irq(SYSCLOCK_IRQ);
 
+    set_leds(6);
+    wait_romcopy_done();
+    set_leds(5);
+
     /* This needs to be done as early as possible!!! */
     abc_init_memmap();
 
-    con_set_baudrate(115200);
-    con_puts(hello);
-
     if (SYS_MAGIC != SYS_MAGIC_MAX80) {
 	con_puts("Not a MAX80 board?!?!\n\n");
     } else {
@@ -71,14 +78,37 @@ void init(void)
 		   (uint16_t)boardcfg);
     }
 
+    con_puts("Quick DRAM test:\n");
+    for (int i = 0; i < 8; i++) {
+	uint32_t v = (i*0x11111111) + 0x44332211;
+	test_dram[i] = v;
+	con_printf("%08x ", v);
+    }
+    con_putc('\n');
+
+    for (int i = 0; i < 8; i++) {
+	con_printf("%08x ", test_dram[i]);
+    }
+    con_puts("\n\n");
+
+    set_leds(4);
+
     read_rtc();
     rtc_abc_init();
 
+    set_leds(3);
+
+    disk_cache_init();
     abcdisk_init();
+
+    set_leds(2);
+
     abc_init();
 
-    set_leds(0);
+    set_leds(1);
 
     /* Release WAIT# if asserted */
     ABC_BUSCTL = 0;
+
+    set_leds(0);
 }