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@@ -38,28 +38,36 @@
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//
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module vjtag_max80
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#(
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+ parameter sram_bits,
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parameter [31:0] sdram_base_addr,
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parameter sdram_bits,
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parameter [31:0] VJTAG_WRITE_PREFIX = 32'hABC80FED
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) (
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- input rst_n,
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- input sys_clk,
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+ input rst_n,
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+ input sys_clk,
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- dram_bus.dstr sdram,
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+ output reset_cmd,
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- input cpu_valid,
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- input [6:2] cpu_addr,
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- input [31:0] cpu_wdata,
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- input [ 3:0] cpu_wstrb,
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- output [31:0] cpu_rdata,
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- output cpu_irq,
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- output cpu_halt,
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+ input cpu_valid,
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+ input [6:2] cpu_addr,
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+ input [31:0] cpu_wdata,
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+ input [ 3:0] cpu_wstrb,
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+ output [31:0] cpu_rdata,
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+ output cpu_irq,
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+ output cpu_halt,
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- output reg reset_cmd
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- );
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+ dram_bus.dstr sdram,
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+
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+ // SRAM interface
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+ output [sram_bits-1:2] sram_addr,
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+ input [31:0] sram_rdata,
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+ output [31:0] sram_wdata,
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+ output sram_read,
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+ output sram_write
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+ );
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wire v_tdi;
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- wire v_tdo;
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+ reg v_tdo;
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wire [4:0] v_ir;
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wire v_tck;
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wire v_st_cdr;
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@@ -104,17 +112,13 @@ module vjtag_max80
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localparam cmd_cpustatus = 4'b1111;
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reg jtag_bypass;
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- reg [31:0] jtag_shr;
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+ wire jtag_out;
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reg tdi_s;
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+ wire tdo_s;
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// Latched information for use in the synchronous state machine
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reg [3:0] ir_cmd; // Command part of IR
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reg ir_ro; // Readonly (update suppress)
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- reg st_cdr_s;
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- reg st_sdr_s;
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- reg st_xdr_s; // Any state between CDR and UDR, exclusively
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- reg st_udr_s;
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- reg st_uir_s;
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always @(posedge v_tck)
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begin
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@@ -122,20 +126,15 @@ module vjtag_max80
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tdi_s <= v_tdi;
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ir_cmd <= v_ir[4:1];
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ir_ro <= v_ir[0];
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- st_cdr_s <= v_st_cdr;
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- st_sdr_s <= v_st_sdr;
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- st_xdr_s <= v_st_sdr|v_st_e1dr|v_st_e2dr|v_st_pdr;
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- st_udr_s <= v_st_udr;
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- st_uir_s <= v_st_uir;
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end
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- assign v_tdo = jtag_bypass ? tdi_s : jtag_shr[0];
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+ assign v_tdo = jtag_bypass ? tdi_s : tdo_s;
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// Sync incoming JTAG signals. Only tck needs an actual
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// synchronizer; the rest just need holding registers (see above)
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// as the delay of tck will guarantee the others are stable.
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wire tck_s;
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- synchronizer #(.width(1)) tck_sync
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+ synchronizer #(.width(1), .stages(3)) tck_sync
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(
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.rst_n ( rst_n ),
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.clk ( sys_clk ),
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@@ -144,13 +143,17 @@ module vjtag_max80
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);
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// Mask of memaddr bits that are not settable: the top bits
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- // and the bottom two bits (byte within dword)
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- localparam [31:0] memaddr_mask = (1'b1 << sdram_bits) - 3'b100;
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+ // and the bottom two bits (byte within dword), and the
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+ // sram/dram select bit
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+ localparam [31:0] memaddr_mask = ((1'b1 << sdram_bits) - 3'b100)
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+ | sdram_base_addr;
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function logic [31:0] maskaddr (input [31:0] addr);
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- maskaddr = (addr & memaddr_mask) | sdram_base_addr;
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+ maskaddr = addr & memaddr_mask;
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endfunction
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+ wire is_dram = |(mem_addr & sdram_base_addr); // Really just one bit
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+
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reg jtag_cpu_irq = 1'b0;
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reg jtag_cpu_halt = 1'b0;
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reg jtag_reset_cmd = 1'b0;
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@@ -168,13 +171,15 @@ module vjtag_max80
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reg mem_write;
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reg [31:0] mem_addr;
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wire [31:0] mem_addr_next = maskaddr(mem_addr + 3'h4);
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- wire [31:0] mem_rdata;
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+ wire [31:0] sdram_rdata;
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reg [31:0] mem_wdata;
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- wire mem_ready;
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+ wire sdram_ready;
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+ reg sram_ready;
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reg mem_done;
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reg mem_error; // Memory underrun
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reg advance_mem_addr;
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reg mem_header_done;
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+ reg mem_do_write;
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reg tck_q;
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reg tck_stb;
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@@ -184,14 +189,18 @@ module vjtag_max80
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tck_stb <= tck_s & ~tck_q;
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end
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+
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// Keep a counter to keep track of SDRAM data bit count; this is to
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// allow streaming of data to/from SDRAM without leaving the
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// SDR state.
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reg [4:0] sdr_ctr;
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- wire [31:0] jtag_shr_in =
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- ir_cmd[3] ? { tdi_s : jtag_shr[31:1] } :
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+ // Main data shift register.
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+ reg [31:0] jtag_shr;
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+ wire [31:0] jtag_shr_in = ir_cmd[3]
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+ ? { tdi_s, jtag_shr[31:1] } :
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{ 30'bx, tdi_s, jtag_shr[1] };
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+ assign tdo_s = jtag_shr[0];
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always @(posedge sys_clk)
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begin
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@@ -202,22 +211,30 @@ module vjtag_max80
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if ( tck_stb )
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begin
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- if ( st_sdr_s )
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+ if ( v_st_sdr )
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jtag_shr <= jtag_shr_in;
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- if ( st_cdr_s )
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+ if ( v_st_cdr )
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case ( ir_cmd )
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- cmd_halt: jtag_shr[0] <= jtag_cpu_halt;
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+ cmd_halt: begin
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+ jtag_shr[0] <= jtag_cpu_halt;
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+ end
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cmd_memerr: begin
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jtag_shr[0] <= mem_error;
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if ( ~ir_ro ) mem_error <= 1'b0;
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end
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- cmd_mem0, cmd_memaddr, cmd_memread, cmd_memwrite:
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- jtag_shr <= jtag_memaddr;
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- cmd_cpucmd, cmd_cpucmd_irq:
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- jtag_shr <= jtag_cpucmd;
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- cmd_cpuinfo: jtag_shr <= jtag_cpuinfo;
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- cmd_cpustatus: jtag_shr <= jtag_cpustatus;
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+ cmd_mem0, cmd_memaddr, cmd_memread, cmd_memwrite: begin
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+ jtag_shr <= jtag_memaddr;
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+ end
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+ cmd_cpucmd, cmd_cpucmd_irq: begin
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+ jtag_shr <= jtag_cpucmd;
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+ end
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+ cmd_cpuinfo: begin
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+ jtag_shr <= jtag_cpuinfo;
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+ end
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+ cmd_cpustatus: begin
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+ jtag_shr <= jtag_cpustatus;
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+ end
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default: ;
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endcase // case ( ir_cmd )
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@@ -233,24 +250,23 @@ module vjtag_max80
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// suppress the update until we know that the user will
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// be reading the fetched data.
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+ mem_do_write <= 1'b0;
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+
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if ( ir_cmd[3:1] == cmd_memwr )
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begin
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- if ( st_cdr_s )
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+ if ( v_st_cdr )
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begin
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mem_done <= 1'b0;
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mem_valid <= 1'b0;
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mem_write <= ir_cmd[0];
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advance_mem_addr <= 1'b0;
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- mem_addr <= jtag_memaddr;
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- end
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-
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- if ( ~st_xdr_s )
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- begin
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mem_header_done <= 1'b0;
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+ mem_addr <= jtag_memaddr;
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sdr_ctr <= 5'b0;
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+ mem_do_write <= 1'b0;
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end
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- if ( st_sdr_s )
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+ if ( v_st_sdr )
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begin
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sdr_ctr <= sdr_ctr + 1'b1;
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@@ -266,74 +282,91 @@ module vjtag_max80
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// Write
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if ( jtag_shr_in == VJTAG_WRITE_PREFIX )
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mem_header_done <= 1'b1;
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- sdr_ctr <= 5'b0;
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+ else
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+ sdr_ctr <= 5'b0;
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end
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end
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// Memory access underrun?
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- if ( &sdr_ctr )
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+ if ( sdr_ctr == 5'd31 )
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mem_error <= mem_error | mem_valid;
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if ( ~mem_write )
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- // Read
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- case ( sdr_ctr )
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- 5'd2: begin
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- // For a read, make sure we are committed
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- // to reading the new word
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- if ( ~ir_ro )
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- jtag_memaddr <= mem_addr;
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-
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- advance_mem_addr <= mem_header_done;
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- end
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- 5'd3:
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- begin
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- // After mem_addr advanced
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- mem_valid <= 1'b1;
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- mem_done <= 1'b0;
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- end
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- 5'd31: begin
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- jtag_shr <= mem_rdata;
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- end
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- default: ;
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- endcase // case ( sdr_ctr )
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+ begin
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+ // Read
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+ case ( sdr_ctr )
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+ 5'd2: begin
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+ // For a read, make sure we are committed
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+ // to reading the new word
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+ if ( ~ir_ro )
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+ jtag_memaddr <= mem_addr;
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+
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+ advance_mem_addr <= mem_header_done;
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+ end
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+ 5'd3:
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+ begin
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+ // After mem_addr advanced
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+ mem_valid <= 1'b1;
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+ mem_done <= 1'b0;
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+ end
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+ 5'd31: begin
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+ jtag_shr <= is_dram ? sdram_rdata : sram_rdata;
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+ end
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+ default: ;
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+ endcase // case ( sdr_ctr )
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+ end // if ( ~mem_write )
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else
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- // Write
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- if ( &sdr_ctr )
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- begin
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- mem_wdata <= jtag_shr_in;
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- mem_valid <= 1'b1;
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- mem_done <= 1'b0;
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- advance_mem_addr <= 1'b1;
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- if ( ~ir_ro )
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- jtag_memaddr <= mem_addr_next;
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- end
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+ begin
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+ // Write
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+ mem_do_write <= &sdr_ctr;
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+ end // else: !if( ~mem_write )
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end // if ( st_sdr_s )
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end // if ( ir_cmd[3:1] == cmd_memwr )
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-
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- if ( st_uir_s )
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+
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+ if ( mem_do_write )
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+ begin
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+ mem_wdata <= jtag_shr_in;
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+ mem_valid <= 1'b1;
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+ mem_done <= 1'b0;
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+ advance_mem_addr <= 1'b1;
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+ if ( ~ir_ro )
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+ jtag_memaddr <= mem_addr_next;
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+ end
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+
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+ if ( v_st_uir )
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jtag_cpu_irq <= ir_cmd == cmd_irq;
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- else if ( st_udr_s )
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+ else if ( v_st_udr )
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jtag_cpu_irq <= ir_cmd == cmd_cpucmd_irq;
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- if ( st_uir_s )
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+ if ( v_st_uir )
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jtag_reset_cmd <= jtag_reset_cmd | (ir_cmd == cmd_reset);
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- if ( st_udr_s & ~ir_ro )
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+ if ( v_st_udr & ~ir_ro )
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case ( ir_cmd )
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- cmd_halt: jtag_cpu_halt <= jtag_shr[0];
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- cmd_memaddr: jtag_memaddr <= maskaddr(jtag_shr);
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- cmd_cpucmd, cmd_cpucmd_irq:
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- jtag_cpucmd <= jtag_shr;
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+ cmd_halt: begin
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+ jtag_cpu_halt <= jtag_shr_in[0];
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+ end
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+ cmd_memaddr: begin
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+ jtag_memaddr <= maskaddr(jtag_shr_in);
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+ end
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+ cmd_cpucmd, cmd_cpucmd_irq: begin
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+ jtag_cpucmd <= jtag_shr_in;
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+ end
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default: /* nothing */ ;
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endcase // case ( ir_cmd )
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end // if ( tck_stb )
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// Increment the temporary address register if applicable,
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// but only after the previous transaction is done...
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- if ( mem_valid & mem_ready )
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+ if ( mem_valid )
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begin
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- mem_valid <= 1'b0;
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- mem_done <= 1'b1;
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+ if (is_dram ? sdram_ready : sram_ready)
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+ begin
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+ mem_valid <= 1'b0;
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+ mem_done <= 1'b1;
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+ end
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+ else
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+ sram_ready <= ~is_dram;
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end
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if ( advance_mem_addr & ~mem_valid )
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begin
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@@ -347,15 +380,20 @@ module vjtag_max80
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.bus ( sdram ),
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.prio ( 2'd2 ),
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.addr ( mem_addr ),
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- .valid ( mem_valid ),
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+ .valid ( mem_valid & is_dram ),
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.wd ( mem_wdata ),
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.wstrb ( {4{mem_write}} ),
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- .ready ( mem_ready ),
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- .rd ( mem_rdata )
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+ .ready ( sdram_ready ),
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+ .rd ( sdram_rdata )
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);
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+ assign sram_addr = mem_addr[sram_bits-1:2];
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+ assign sram_wdata = mem_wdata;
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+ assign sram_read = mem_valid & ~is_dram & ~mem_write;
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+ assign sram_write = mem_valid & ~is_dram & mem_write;
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+
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wire [7:0] cpustatus_new =
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- ( tck_stb & st_cdr_s & ~ir_ro & (ir_cmd == cmd_cpustatus) )
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+ ( tck_stb & v_st_cdr & ~ir_ro & (ir_cmd == cmd_cpustatus) )
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? 'b0 : jtag_cpustatus;
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always @(negedge rst_n or posedge sys_clk)
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H. Peter Anvin