abcbus: drop unused mapram nodes

With going to simpleio, only 128x18 bits are needed in abcmapram,
which reduces the cost to 1 M9K block.

fpga/abcbus.sv

@@ -99,6 +99,7 @@ module abcbus (
 
    assign abc_master = 1'b0;	// Only device mode supported
    assign abc_d_ce_n = 1'b0;	// Do not isolate busses
+   assign abc_a_oe   = 1'b0;	// Only device mode, again...
 
    reg	     abc_clk_active;
 
@@ -253,49 +254,38 @@ module abcbus (
    // 512 byte granularity for memory (registers 0-127),
    // one input and one output queue per select code for I/O (128-255).
    //
-   // bit [24:0]  = SDRAM address.
-   // bit [25]    = write enable ( bit 30 from CPU )
-   // bit [26]    = read enable  ( bit 31 from CPU )
+   // bit [15:0]  = SDRAM address [24:9] ( bits 24:9 from CPU )
+   // bit [16]    = write enable ( bit 30 from CPU )
+   // bit [17]    = read enable  ( bit 31 from CPU )
    //
    // Accesses from the internal CPU supports 32-bit accesses only!
    //
-   wire [7:0] abc_map_addr = { 1'b0, abc_a_s[15:9] };
-   wire [35:0] rdata_abcmemmap;
-   wire [35:0] abc_memmap_rd;
-
-   //
-   // For I/O, don't allow the read/write enables to conflict with
-   // the direction of the I/O.
-   //
-   wire [1:0]  abcmap_masked_rdwr = cpu_wdata[31:30];
+   wire [17:0] rdata_abcmemmap;
+   wire [17:0] abc_memmap_rd;
 
    abcmapram abcmapram (
 			.aclr      ( ~rst_n ),
 
 			.clock     ( sdram_clk ),
 
-			.address_a ( abc_map_addr ),
-			.data_a    ( 36'bx ),
+			.address_a ( abc_a_s[15:9] ),
+			.data_a    ( 18'bx ),
 			.wren_a    ( 1'b0 ),
-			.byteena_a ( 4'bxxxx ),
 			.q_a       ( abc_memmap_rd ),
 
-			.address_b ( cpu_addr[9:2] ),
-			.data_b    ( { 9'bx,
-				       abcmap_masked_rdwr,
-				       cpu_wdata[24:0] } ),
+			.address_b ( cpu_addr[8:2] ),
+			.data_b    ( { cpu_wdata[31:30], cpu_wdata[24:9] } ),
 			.wren_b    ( map_valid & cpu_wstrb[0] ),
-			.byteena_b ( 4'b1111 ),
 
 			.q_b       ( rdata_abcmemmap )
 			);
 
-   assign cpu_rdata_map =  { rdata_abcmemmap[26:25], 5'b0,
-			     rdata_abcmemmap[24:0] };
+   assign cpu_rdata_map =  { rdata_abcmemmap[17:16], 5'b0,
+			     rdata_abcmemmap[15:0], 9'b0 };
 
-   wire        abc_rden    = abc_memmap_rd[26];
-   wire        abc_wren    = abc_memmap_rd[25];
-   wire [24:0] abc_memaddr = abc_memmap_rd[24:0];
+   wire        abc_rden    = abc_memmap_rd[17];
+   wire        abc_wren    = abc_memmap_rd[16];
+   wire [24:0] abc_memaddr = { abc_memmap_rd[15:0], abc_a_s[8:0] };
 
    reg	      abc_memrd_en;
    reg	      abc_memwr_en;
@@ -337,8 +327,8 @@ module abcbus (
 	  sdram_wrq     <= abc_do_memwr & ~abc_wacked;
        end // else: !if(~rst_n)
 
-   assign sdram_addr = { abc_memaddr[24:9], abc_a_s[8:0] };
-   assign sdram_wd = abc_di;
+   assign sdram_addr = abc_memaddr;
+   assign sdram_wd   = abc_di;
 
    // I/O data registers; RST# is considered OUT 7 even through
    // it is an IN from the ABC point of view.

fpga/ip/abcmapram.v

@@ -41,8 +41,6 @@ module abcmapram (
 	aclr,
 	address_a,
 	address_b,
-	byteena_a,
-	byteena_b,
 	clock,
 	data_a,
 	data_b,
@@ -52,23 +50,19 @@ module abcmapram (
 	q_b);
 
 	input	  aclr;
-	input	[7:0]  address_a;
-	input	[7:0]  address_b;
-	input	[3:0]  byteena_a;
-	input	[3:0]  byteena_b;
+	input	[6:0]  address_a;
+	input	[6:0]  address_b;
 	input	  clock;
-	input	[35:0]  data_a;
-	input	[35:0]  data_b;
+	input	[17:0]  data_a;
+	input	[17:0]  data_b;
 	input	  wren_a;
 	input	  wren_b;
-	output	[35:0]  q_a;
-	output	[35:0]  q_b;
+	output	[17:0]  q_a;
+	output	[17:0]  q_b;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_off
 `endif
 	tri0	  aclr;
-	tri1	[3:0]  byteena_a;
-	tri1	[3:0]  byteena_b;
 	tri1	  clock;
 	tri0	  wren_a;
 	tri0	  wren_b;
@@ -76,17 +70,15 @@ module abcmapram (
 // synopsys translate_on
 `endif
 
-	wire [35:0] sub_wire0;
-	wire [35:0] sub_wire1;
-	wire [35:0] q_a = sub_wire0[35:0];
-	wire [35:0] q_b = sub_wire1[35:0];
+	wire [17:0] sub_wire0;
+	wire [17:0] sub_wire1;
+	wire [17:0] q_a = sub_wire0[17:0];
+	wire [17:0] q_b = sub_wire1[17:0];
 
 	altsyncram	altsyncram_component (
 				.aclr0 (aclr),
 				.address_a (address_a),
 				.address_b (address_b),
-				.byteena_a (byteena_a),
-				.byteena_b (byteena_b),
 				.clock0 (clock),
 				.data_a (data_a),
 				.data_b (data_b),
@@ -97,6 +89,8 @@ module abcmapram (
 				.aclr1 (1'b0),
 				.addressstall_a (1'b0),
 				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
 				.clock1 (1'b1),
 				.clocken0 (1'b1),
 				.clocken1 (1'b1),
@@ -107,8 +101,6 @@ module abcmapram (
 				.rden_b (1'b1));
 	defparam
 		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.byteena_reg_b = "CLOCK0",
-		altsyncram_component.byte_size = 9,
 		altsyncram_component.clock_enable_input_a = "BYPASS",
 		altsyncram_component.clock_enable_input_b = "BYPASS",
 		altsyncram_component.clock_enable_output_a = "BYPASS",
@@ -116,8 +108,8 @@ module abcmapram (
 		altsyncram_component.indata_reg_b = "CLOCK0",
 		altsyncram_component.intended_device_family = "Cyclone IV E",
 		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = 256,
-		altsyncram_component.numwords_b = 256,
+		altsyncram_component.numwords_a = 128,
+		altsyncram_component.numwords_b = 128,
 		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
 		altsyncram_component.outdata_aclr_a = "CLEAR0",
 		altsyncram_component.outdata_aclr_b = "CLEAR0",
@@ -125,14 +117,14 @@ module abcmapram (
 		altsyncram_component.outdata_reg_b = "CLOCK0",
 		altsyncram_component.power_up_uninitialized = "FALSE",
 		altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
-		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
-		altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
-		altsyncram_component.widthad_a = 8,
-		altsyncram_component.widthad_b = 8,
-		altsyncram_component.width_a = 36,
-		altsyncram_component.width_b = 36,
-		altsyncram_component.width_byteena_a = 4,
-		altsyncram_component.width_byteena_b = 4,
+		altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
+		altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
+		altsyncram_component.widthad_a = 7,
+		altsyncram_component.widthad_b = 7,
+		altsyncram_component.width_a = 18,
+		altsyncram_component.width_b = 18,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
 		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
 
 
@@ -145,8 +137,8 @@ endmodule
 // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
 // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
 // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "1"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
 // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
@@ -171,7 +163,7 @@ endmodule
 // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2304"
 // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
 // Retrieval info: PRIVATE: MIFfilename STRING ""
 // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
@@ -179,8 +171,8 @@ endmodule
 // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
 // Retrieval info: PRIVATE: REGdata NUMERIC "1"
 // Retrieval info: PRIVATE: REGq NUMERIC "1"
 // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
@@ -191,10 +183,10 @@ endmodule
 // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
 // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
 // Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "36"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "36"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "36"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "36"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
 // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
 // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
 // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
@@ -202,8 +194,6 @@ endmodule
 // Retrieval info: PRIVATE: rden NUMERIC "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: BYTEENA_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "9"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
@@ -211,8 +201,8 @@ endmodule
 // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
 // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
 // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
 // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
@@ -220,39 +210,35 @@ endmodule
 // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
 // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
 // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "36"
-// Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "4"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
 // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
-// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
-// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]"
-// Retrieval info: USED_PORT: byteena_b 0 0 4 0 INPUT VCC "byteena_b[3..0]"
+// Retrieval info: USED_PORT: address_a 0 0 7 0 INPUT NODEFVAL "address_a[6..0]"
+// Retrieval info: USED_PORT: address_b 0 0 7 0 INPUT NODEFVAL "address_b[6..0]"
 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-// Retrieval info: USED_PORT: data_a 0 0 36 0 INPUT NODEFVAL "data_a[35..0]"
-// Retrieval info: USED_PORT: data_b 0 0 36 0 INPUT NODEFVAL "data_b[35..0]"
-// Retrieval info: USED_PORT: q_a 0 0 36 0 OUTPUT NODEFVAL "q_a[35..0]"
-// Retrieval info: USED_PORT: q_b 0 0 36 0 OUTPUT NODEFVAL "q_b[35..0]"
+// Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
+// Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
+// Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
+// Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
 // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
 // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
 // Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
-// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
-// Retrieval info: CONNECT: @byteena_b 0 0 4 0 byteena_b 0 0 4 0
+// Retrieval info: CONNECT: @address_a 0 0 7 0 address_a 0 0 7 0
+// Retrieval info: CONNECT: @address_b 0 0 7 0 address_b 0 0 7 0
 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 36 0 data_a 0 0 36 0
-// Retrieval info: CONNECT: @data_b 0 0 36 0 data_b 0 0 36 0
+// Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
+// Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
 // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-// Retrieval info: CONNECT: q_a 0 0 36 0 @q_a 0 0 36 0
-// Retrieval info: CONNECT: q_b 0 0 36 0 @q_b 0 0 36 0
+// Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
+// Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL abcmapram.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL abcmapram.inc FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL abcmapram.cmp FALSE