Historique des commits

Auteur SHA1 Message Date
  H. Peter Anvin 0a742774ae Getting full synthesis with CPU and fast memory; not tested yet il y a 3 ans
  H. Peter Anvin 29caaeebbe pll: change system clock to 84 MHz il y a 3 ans
  H. Peter Anvin 98999420a7 max80: better testing of the sdram controller il y a 3 ans
  H. Peter Anvin 728e8de139 sdram: allow arbitrary alignments on port 1 il y a 3 ans
  H. Peter Anvin 2c6d4d66d2 sdram: fix some timing calculations, pre-ack, cleanups il y a 3 ans
  H. Peter Anvin 7efe6c8d1c sdram: fix op_cycle counter overflow il y a 3 ans
  H. Peter Anvin 9363f018e1 sdram: rewrite state machine with an operations loop counter il y a 3 ans
  H. Peter Anvin b2d184d021 Fix polarity of output SDRAM clock; move into sdram module il y a 3 ans
  H. Peter Anvin 30d5acc569 Change core clock to 168 MHz and video clock to 48 MHz il y a 3 ans
  H. Peter Anvin afc9429471 Add simple SDRAM controller il y a 3 ans
  H. Peter Anvin 43d9806872 Remove unused assignments; use a DDIO buffer for sr_clk il y a 3 ans
  H. Peter Anvin 8d356f7502 Automate jic file generation il y a 3 ans
  H. Peter Anvin 7522b73a70 Update configuration assigments, JIC generation il y a 3 ans