max80_fw/output_files/max80.cmp.rpt

Compilation report for max80
Fri Aug  6 20:12:57 2021
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log
  8. Analysis & Synthesis Summary
  9. Analysis & Synthesis Settings
 10. Parallel Compilation
 11. Analysis & Synthesis Source Files Read
 12. Analysis & Synthesis Resource Usage Summary
 13. Analysis & Synthesis Resource Utilization by Entity
 14. Registers Removed During Synthesis
 15. Removed Registers Triggering Further Register Optimizations
 16. General Register Statistics
 17. Inverted Register Statistics
 18. Multiplexer Restructuring Statistics (Restructuring Performed)
 19. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated
 20. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2
 21. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4
 22. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5
 23. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated
 24. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out
 25. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio
 26. Parameter Settings for User Entity Instance: Top-level Entity: |max80
 27. Parameter Settings for User Entity Instance: pll:pll|altpll:altpll_component
 28. Parameter Settings for User Entity Instance: transpose:hdmitranspose
 29. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:dreg
 30. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:qreg
 31. Parameter Settings for User Entity Instance: hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component
 32. altpll Parameter Settings by Entity Instance
 33. Port Connectivity Checks: "hdmitx:hdmitx"
 34. Port Connectivity Checks: "transpose:hdmitranspose"
 35. Port Connectivity Checks: "tmdsenc:hdmitmds[2].enc"
 36. Port Connectivity Checks: "tmdsenc:hdmitmds[1].enc"
 37. Port Connectivity Checks: "tmdsenc:hdmitmds[0].enc"
 38. Port Connectivity Checks: "pll:pll"
 39. Post-Synthesis Netlist Statistics for Top Partition
 40. Elapsed Time Per Partition
 41. Analysis & Synthesis Equations
 42. Analysis & Synthesis Messages
 43. Fitter Summary
 44. Fitter Settings
 45. Parallel Compilation
 46. Fitter Netlist Optimizations
 47. Ignored Assignments
 48. Incremental Compilation Preservation Summary
 49. Incremental Compilation Partition Settings
 50. Incremental Compilation Placement Preservation
 51. Fitter Equations
 52. Pin-Out File
 53. Fitter Resource Usage Summary
 54. Fitter Partition Statistics
 55. Input Pins
 56. Output Pins
 57. Bidir Pins
 58. Dual Purpose and Dedicated Pins
 59. I/O Bank Usage
 60. All Package Pins
 61. PLL Summary
 62. PLL Usage
 63. I/O Assignment Warnings
 64. Fitter Resource Utilization by Entity
 65. Delay Chain Summary
 66. Pad To Core Delay Chain Fanout
 67. Control Signals
 68. Global & Other Fast Signals
 69. Routing Usage Summary
 70. LAB Logic Elements
 71. LAB-wide Signals
 72. LAB Signals Sourced
 73. LAB Signals Sourced Out
 74. LAB Distinct Inputs
 75. I/O Rules Summary
 76. I/O Rules Details
 77. I/O Rules Matrix
 78. Fitter Device Options
 79. Operating Settings and Conditions
 80. Estimated Delay Added for Hold Timing Summary
 81. Estimated Delay Added for Hold Timing Details
 82. Fitter Messages
 83. Fitter Suppressed Messages
 84. Assembler Summary
 85. Assembler Settings
 86. Assembler Generated Files
 87. Assembler Device Options: max80.sof
 88. Assembler Device Options: max80.jam
 89. Assembler Device Options: max80.jbc
 90. Assembler Device Options: max80.pof
 91. Assembler Messages
 92. Parallel Compilation
 93. Power Analyzer Summary
 94. Power Analyzer Settings
 95. Indeterminate Toggle Rates
 96. Operating Conditions Used
 97. Thermal Power Dissipation by Block
 98. Thermal Power Dissipation by Block Type
 99. Thermal Power Dissipation by Hierarchy
100. Core Dynamic Thermal Power Dissipation by Clock Domain
101. Current Drawn from Voltage Supplies Summary
102. VCCIO Supply Current Drawn by I/O Bank
103. VCCIO Supply Current Drawn by Voltage
104. Confidence Metric Details
105. Signal Activities
106. Power Analyzer Messages
107. Legal Notice
108. Timing Analyzer Summary
109. Parallel Compilation
110. SDC File List
111. Clocks
112. Slow 1200mV 85C Model Fmax Summary
113. Timing Closure Recommendations
114. Slow 1200mV 85C Model Setup Summary
115. Slow 1200mV 85C Model Hold Summary
116. Slow 1200mV 85C Model Recovery Summary
117. Slow 1200mV 85C Model Removal Summary
118. Slow 1200mV 85C Model Minimum Pulse Width Summary
119. Slow 1200mV 85C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
120. Slow 1200mV 85C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'
121. Slow 1200mV 85C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'
122. Slow 1200mV 85C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
123. Slow 1200mV 85C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'
124. Slow 1200mV 85C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
125. Slow 1200mV 85C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'
126. Slow 1200mV 85C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
127. Slow 1200mV 85C Model Metastability Summary
128. Slow 1200mV 0C Model Fmax Summary
129. Slow 1200mV 0C Model Setup Summary
130. Slow 1200mV 0C Model Hold Summary
131. Slow 1200mV 0C Model Recovery Summary
132. Slow 1200mV 0C Model Removal Summary
133. Slow 1200mV 0C Model Minimum Pulse Width Summary
134. Slow 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
135. Slow 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'
136. Slow 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'
137. Slow 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
138. Slow 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'
139. Slow 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
140. Slow 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'
141. Slow 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
142. Slow 1200mV 0C Model Metastability Summary
143. Fast 1200mV 0C Model Setup Summary
144. Fast 1200mV 0C Model Hold Summary
145. Fast 1200mV 0C Model Recovery Summary
146. Fast 1200mV 0C Model Removal Summary
147. Fast 1200mV 0C Model Minimum Pulse Width Summary
148. Fast 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
149. Fast 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'
150. Fast 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'
151. Fast 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
152. Fast 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'
153. Fast 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'
154. Fast 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'
155. Fast 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'
156. Fast 1200mV 0C Model Metastability Summary
157. Multicorner Timing Analysis Summary
158. Board Trace Model Assignments
159. Input Transition Times
160. Signal Integrity Metrics (Slow 1200mv 0c Model)
161. Signal Integrity Metrics (Slow 1200mv 85c Model)
162. Signal Integrity Metrics (Fast 1200mv 0c Model)
163. Setup Transfers
164. Hold Transfers
165. Recovery Transfers
166. Removal Transfers
167. Report TCCS
168. Report RSKM
169. Unconstrained Paths Summary
170. Clock Status Summary
171. Unconstrained Output Ports
172. Unconstrained Output Ports
173. Timing Analyzer Messages
174. EDA Netlist Writer Summary
175. Simulation Settings
176. Simulation Generated Files
177. EDA Netlist Writer Messages
178. Flow Messages
179. Flow Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2020  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+----------------------------------------------------------------------------------+
; Flow Summary                                                                     ;
+------------------------------------+---------------------------------------------+
; Flow Status                        ; Successful - Fri Aug  6 20:12:57 2021       ;
; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name                      ; max80                                       ;
; Top-level Entity Name              ; max80                                       ;
; Family                             ; Cyclone IV E                                ;
; Device                             ; EP4CE15F17C8                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 327 / 15,408 ( 2 % )                        ;
;     Total combinational functions  ; 278 / 15,408 ( 2 % )                        ;
;     Dedicated logic registers      ; 218 / 15,408 ( 1 % )                        ;
; Total registers                    ; 229                                         ;
; Total pins                         ; 143 / 166 ( 86 % )                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0 / 516,096 ( 0 % )                         ;
; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
; Total PLLs                         ; 2 / 4 ( 50 % )                              ;
+------------------------------------+---------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 08/06/2021 20:12:35 ;
; Main task         ; Compilation         ;
; Revision Name     ; max80               ;
+-------------------+---------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                                                      ;
+--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
+--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID                      ; 275741387998995.162830595557146        ; --            ; --          ; --                                ;
; EDA_ENABLE_GLITCH_FILTERING                ; On                                     ; --            ; --          ; eda_simulation                    ;
; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_symbol           ;
; EDA_MAP_ILLEGAL_CHARACTERS                 ; On                                     ; --            ; --          ; eda_simulation                    ;
; EDA_OUTPUT_DATA_FORMAT                     ; Verilog Hdl                            ; --            ; --          ; eda_simulation                    ;
; EDA_SIMULATION_TOOL                        ; ModelSim-Altera (Verilog)              ; <None>        ; --          ; --                                ;
; EDA_TEST_BENCH_DESIGN_INSTANCE_NAME        ; max80                                  ; --            ; --          ; eda_simulation                    ;
; EDA_TIME_SCALE                             ; 1 ps                                   ; --            ; --          ; eda_simulation                    ;
; EDA_WRITE_NODES_FOR_POWER_ESTIMATION       ; ALL_NODES                              ; --            ; --          ; eda_simulation                    ;
; FLOW_ENABLE_POWER_ANALYZER                 ; On                                     ; Off           ; --          ; --                                ;
; HDL_MESSAGE_LEVEL                          ; Level3                                 ; Level2        ; --          ; --                                ;
; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 1                                 ;
; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 2                                 ;
; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 3                                 ;
; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 4                                 ;
; IOBANK_VCCIO                               ; 2.5V                                   ; --            ; --          ; 5                                 ;
; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 6                                 ;
; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 7                                 ;
; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 8                                 ;
; MAX_CORE_JUNCTION_TEMP                     ; 85                                     ; --            ; --          ; --                                ;
; MIN_CORE_JUNCTION_TEMP                     ; 0                                      ; --            ; --          ; --                                ;
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers                  ; Normal        ; --          ; --                                ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS             ; Half Signal Swing                      ; --            ; --          ; --                                ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS             ; Half Signal Swing                      ; --            ; --          ; --                                ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS            ; Half Vccio                             ; --            ; --          ; --                                ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS            ; Half Vccio                             ; --            ; --          ; --                                ;
; PARTITION_COLOR                            ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
; PARTITION_FITTER_PRESERVATION_LEVEL        ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
; PARTITION_NETLIST_TYPE                     ; -- (Not supported for targeted family) ; --            ; --          ; Top                               ;
; POST_MODULE_SCRIPT_FILE                    ; quartus_sh:postmodule.tcl              ; --            ; --          ; --                                ;
; POWER_BOARD_THERMAL_MODEL                  ; None (CONSERVATIVE)                    ; --            ; --          ; --                                ;
; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE         ; 12.5 %                                 ; 12.5%         ; --          ; --                                ;
; POWER_PRESET_COOLING_SOLUTION              ; No Heat Sink With Still Air            ; --            ; --          ; --                                ;
; PROJECT_OUTPUT_DIRECTORY                   ; output_files                           ; --            ; --          ; --                                ;
; REMOVE_REDUNDANT_LOGIC_CELLS               ; On                                     ; Off           ; --          ; --                                ;
; SAFE_STATE_MACHINE                         ; On                                     ; Off           ; --          ; --                                ;
; SYNTH_MESSAGE_LEVEL                        ; High                                   ; Medium        ; --          ; --                                ;
; SYNTH_PROTECT_SDC_CONSTRAINT               ; On                                     ; Off           ; --          ; --                                ;
; VCCA_USER_VOLTAGE                          ; 2.5V                                   ; --            ; --          ; --                                ;
; VERILOG_INPUT_VERSION                      ; SystemVerilog_2005                     ; Verilog_2001  ; --          ; --                                ;
; VERILOG_SHOW_LMF_MAPPING_MESSAGES          ; Off                                    ; --            ; --          ; --                                ;
; VHDL_INPUT_VERSION                         ; VHDL_2008                              ; VHDL_1993     ; --          ; --                                ;
; VHDL_SHOW_LMF_MAPPING_MESSAGES             ; Off                                    ; --            ; --          ; --                                ;
+--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                        ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 679 MB              ; 00:00:15                           ;
; Fitter               ; 00:00:06     ; 1.0                     ; 1524 MB             ; 00:00:07                           ;
; Assembler            ; 00:00:02     ; 1.0                     ; 569 MB              ; 00:00:02                           ;
; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1021 MB             ; 00:00:01                           ;
; Timing Analyzer      ; 00:00:02     ; 1.1                     ; 728 MB              ; 00:00:01                           ;
; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 813 MB              ; 00:00:00                           ;
; Total                ; 00:00:17     ; --                      ; --                  ; 00:00:26                           ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+


+-------------------------------------------------------------------------------------------+
; Flow OS Summary                                                                           ;
+----------------------+-----------------------+-------------+-------------+----------------+
; Module Name          ; Machine Hostname      ; OS Name     ; OS Version  ; Processor type ;
+----------------------+-----------------------+-------------+-------------+----------------+
; Analysis & Synthesis ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
; Fitter               ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
; Assembler            ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
; Power Analyzer       ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
; Timing Analyzer      ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
; EDA Netlist Writer   ; tazenda.hos.anvin.org ; Fedora Core ; Fedora Core ; x86_64         ;
+----------------------+-----------------------+-------------+-------------+----------------+


------------
; Flow Log ;
------------
quartus_map --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
quartus_fit --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
quartus_pow --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
quartus_sta --lower_priority max80 -c max80
quartus_eda --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri Aug  6 20:12:40 2021       ;
; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name                      ; max80                                       ;
; Top-level Entity Name              ; max80                                       ;
; Family                             ; Cyclone IV E                                ;
; Total logic elements               ; 337                                         ;
;     Total combinational functions  ; 274                                         ;
;     Dedicated logic registers      ; 218                                         ;
; Total registers                    ; 226                                         ;
; Total pins                         ; 139                                         ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0                                           ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 2                                           ;
+------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                              ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option                                                           ; Setting            ; Default Value      ;
+------------------------------------------------------------------+--------------------+--------------------+
; Device                                                           ; EP4CE15F17C8       ;                    ;
; Top-level entity name                                            ; max80              ; max80              ;
; Family name                                                      ; Cyclone IV E       ; Cyclone V          ;
; VHDL Show LMF Mapping Messages                                   ; Off                ;                    ;
; Verilog Show LMF Mapping Messages                                ; Off                ;                    ;
; Verilog Version                                                  ; SystemVerilog_2005 ; Verilog_2001       ;
; VHDL Version                                                     ; VHDL_2008          ; VHDL_1993          ;
; Safe State Machine                                               ; On                 ; Off                ;
; Remove Redundant Logic Cells                                     ; On                 ; Off                ;
; HDL message level                                                ; Level3             ; Level2             ;
; SDC constraint protection                                        ; On                 ; Off                ;
; Analysis & Synthesis Message Level                               ; High               ; Medium             ;
; Use smart compilation                                            ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                      ; Off                ; Off                ;
; Restructure Multiplexers                                         ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
; Preserve fewer node names                                        ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
; State Machine Processing                                         ; Auto               ; Auto               ;
; Extract Verilog State Machines                                   ; On                 ; On                 ;
; Extract VHDL State Machines                                      ; On                 ; On                 ;
; Ignore Verilog initial constructs                                ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
; Parallel Synthesis                                               ; On                 ; On                 ;
; DSP Block Balancing                                              ; Auto               ; Auto               ;
; NOT Gate Push-Back                                               ; On                 ; On                 ;
; Power-Up Don't Care                                              ; On                 ; On                 ;
; Remove Duplicate Registers                                       ; On                 ; On                 ;
; Ignore CARRY Buffers                                             ; Off                ; Off                ;
; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore LCELL Buffers                                             ; Off                ; Off                ;
; Ignore SOFT Buffers                                              ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
; Optimization Technique                                           ; Balanced           ; Balanced           ;
; Carry Chain Length                                               ; 70                 ; 70                 ;
; Auto Carry Chains                                                ; On                 ; On                 ;
; Auto Open-Drain Pins                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
; Auto ROM Replacement                                             ; On                 ; On                 ;
; Auto RAM Replacement                                             ; On                 ; On                 ;
; Auto DSP Block Replacement                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
; Strict RAM Replacement                                           ; Off                ; Off                ;
; Allow Synchronous Control Signals                                ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
; Auto RAM Block Balancing                                         ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                ; Off                ; Off                ;
; Auto Resource Sharing                                            ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                               ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                               ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                    ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
; Timing-Driven Synthesis                                          ; On                 ; On                 ;
; Report Parameter Settings                                        ; On                 ; On                 ;
; Report Source Assignments                                        ; On                 ; On                 ;
; Report Connectivity Checks                                       ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
; Clock MUX Protection                                             ; On                 ; On                 ;
; Auto Gated Clock Conversion                                      ; Off                ; Off                ;
; Block Design Naming                                              ; Auto               ; Auto               ;
; Synthesis Effort                                                 ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                             ; Off                ; Off                ;
; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                           ; On                 ; On                 ;
+------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 16          ;
; Maximum allowed            ; 8           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 8           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-8         ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                        ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                    ; Library ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
; ip/hdmitx.v                      ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/hdmitx.v                                     ;         ;
; ip/pll.v                         ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/pll.v                                        ;         ;
; transpose.sv                     ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/transpose.sv                                    ;         ;
; tmdsenc.sv                       ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/tmdsenc.sv                                      ;         ;
; max80.sv                         ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/max80.sv                                        ;         ;
; altpll.tdf                       ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/altpll.tdf                     ;         ;
; aglobal201.inc                   ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/aglobal201.inc                 ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratix_pll.inc                ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixii_pll.inc              ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/cycloneii_pll.inc              ;         ;
; db/pll_altpll.v                  ; yes             ; Auto-Generated Megafunction  ; /home/hpa/abc80/max80/blinktest/db/pll_altpll.v                                 ;         ;
; altlvds_tx.tdf                   ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/altlvds_tx.tdf                 ;         ;
; stratix_lvds_transmitter.inc     ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratix_lvds_transmitter.inc   ;         ;
; stratixii_lvds_transmitter.inc   ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixii_lvds_transmitter.inc ;         ;
; stratixgx_lvds_transmitter.inc   ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixgx_lvds_transmitter.inc ;         ;
; stratixgx_pll.inc                ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixgx_pll.inc              ;         ;
; stratixii_clkctrl.inc            ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/stratixii_clkctrl.inc          ;         ;
; altddio_out.inc                  ; yes             ; Megafunction                 ; /opt/altera/20.1/quartus/libraries/megafunctions/altddio_out.inc                ;         ;
; db/hdmitx_lvds_tx.v              ; yes             ; Auto-Generated Megafunction  ; /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v                             ;         ;
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                          ;
+---------------------------------------------+----------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                  ;
+---------------------------------------------+----------------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 337                                                                                    ;
;                                             ;                                                                                        ;
; Total combinational functions               ; 274                                                                                    ;
; Logic element usage by number of LUT inputs ;                                                                                        ;
;     -- 4 input functions                    ; 102                                                                                    ;
;     -- 3 input functions                    ; 65                                                                                     ;
;     -- <=2 input functions                  ; 107                                                                                    ;
;                                             ;                                                                                        ;
; Logic elements by mode                      ;                                                                                        ;
;     -- normal mode                          ; 218                                                                                    ;
;     -- arithmetic mode                      ; 56                                                                                     ;
;                                             ;                                                                                        ;
; Total registers                             ; 226                                                                                    ;
;     -- Dedicated logic registers            ; 218                                                                                    ;
;     -- I/O registers                        ; 16                                                                                     ;
;                                             ;                                                                                        ;
; I/O pins                                    ; 139                                                                                    ;
;                                             ;                                                                                        ;
; Embedded Multiplier 9-bit elements          ; 0                                                                                      ;
;                                             ;                                                                                        ;
; Total PLLs                                  ; 2                                                                                      ;
;     -- PLLs                                 ; 2                                                                                      ;
;                                             ;                                                                                        ;
; Maximum fan-out node                        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock ;
; Maximum fan-out                             ; 114                                                                                    ;
; Total fan-out                               ; 1582                                                                                   ;
; Average fan-out                             ; 1.90                                                                                   ;
+---------------------------------------------+----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                     ;
+--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
; Compilation Hierarchy Node                                   ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                ; Entity Name               ; Library Name ;
+--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
; |max80                                                       ; 274 (52)            ; 218 (66)                  ; 0           ; 0            ; 0       ; 0         ; 139  ; 0            ; |max80                                                                                                             ; max80                     ; work         ;
;    |hdmitx:hdmitx|                                           ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx                                                                                               ; hdmitx                    ; work         ;
;       |altlvds_tx:ALTLVDS_TX_component|                      ; 78 (0)              ; 109 (0)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ; altlvds_tx                ; work         ;
;          |hdmitx_lvds_tx:auto_generated|                     ; 78 (20)             ; 109 (60)                  ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
;             |hdmitx_cntr:cntr13|                             ; 8 (8)               ; 3 (3)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ; hdmitx_cntr               ; work         ;
;             |hdmitx_cntr:cntr2|                              ; 8 (8)               ; 3 (3)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ; hdmitx_cntr               ; work         ;
;             |hdmitx_ddio_out1:outclock_ddio|                 ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ; hdmitx_ddio_out1          ; work         ;
;             |hdmitx_ddio_out:ddio_out|                       ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ; hdmitx_ddio_out           ; work         ;
;             |hdmitx_shift_reg1:shift_reg23|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg24|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg25|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg26|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg27|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg28|                  ; 5 (5)               ; 5 (5)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg:outclk_shift_h|                ; 7 (7)               ; 7 (7)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ; hdmitx_shift_reg          ; work         ;
;             |hdmitx_shift_reg:outclk_shift_l|                ; 5 (5)               ; 6 (6)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ; hdmitx_shift_reg          ; work         ;
;    |pll:pll|                                                 ; 3 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll                                                                                                     ; pll                       ; work         ;
;       |altpll:altpll_component|                              ; 3 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component                                                                             ; altpll                    ; work         ;
;          |pll_altpll:auto_generated|                         ; 3 (3)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ; pll_altpll                ; work         ;
;             |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ; pll_altpll_dyn_phase_le12 ; work         ;
;             |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|  ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ; pll_altpll_dyn_phase_le1  ; work         ;
;             |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|   ; 0 (0)               ; 0 (0)                     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ; pll_altpll_dyn_phase_le   ; work         ;
;    |tmdsenc:hdmitmds[0].enc|                                 ; 47 (47)             ; 15 (15)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ; tmdsenc                   ; work         ;
;    |tmdsenc:hdmitmds[1].enc|                                 ; 47 (47)             ; 14 (14)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ; tmdsenc                   ; work         ;
;    |tmdsenc:hdmitmds[2].enc|                                 ; 47 (47)             ; 14 (14)                   ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ; tmdsenc                   ; work         ;
+--------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                            ; Reason for Removal                                                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9] ; Stuck at GND due to stuck port data_in                                                                                               ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9] ; Stuck at GND due to stuck port data_in                                                                                               ;
; tmdsenc:hdmitmds[2].enc|creg[0,1]                                                                                        ; Stuck at GND due to stuck port data_in                                                                                               ;
; tmdsenc:hdmitmds[1].enc|creg[0,1]                                                                                        ; Stuck at GND due to stuck port data_in                                                                                               ;
; tmdsenc:hdmitmds[0].enc|creg[0,1]                                                                                        ; Stuck at GND due to stuck port data_in                                                                                               ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep                                             ; Stuck at GND due to stuck port clock                                                                                                 ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state                                                ; Stuck at GND due to stuck port clock                                                                                                 ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg                                     ; Stuck at GND due to stuck port clock                                                                                                 ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_lock_sync                                                  ; Stuck at VCC due to stuck port data_in                                                                                               ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0..2]         ; Stuck at GND due to stuck port clock                                                                                                 ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0,1]                ; Stuck at GND due to stuck port clock                                                                                                 ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8] ; Stuck at GND due to stuck port data_in                                                                                               ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8] ; Stuck at GND due to stuck port data_in                                                                                               ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7] ; Stuck at GND due to stuck port data_in                                                                                               ;
; tmdsenc:hdmitmds[2].enc|dreg[7]                                                                                          ; Merged with dummydata[0]                                                                                                             ;
; tmdsenc:hdmitmds[0].enc|dreg[0]                                                                                          ; Merged with dummydata[1]                                                                                                             ;
; tmdsenc:hdmitmds[0].enc|dreg[1]                                                                                          ; Merged with dummydata[2]                                                                                                             ;
; tmdsenc:hdmitmds[0].enc|dreg[2]                                                                                          ; Merged with dummydata[3]                                                                                                             ;
; tmdsenc:hdmitmds[0].enc|dreg[3]                                                                                          ; Merged with dummydata[4]                                                                                                             ;
; tmdsenc:hdmitmds[0].enc|dreg[4]                                                                                          ; Merged with dummydata[5]                                                                                                             ;
; tmdsenc:hdmitmds[0].enc|dreg[5]                                                                                          ; Merged with dummydata[6]                                                                                                             ;
; tmdsenc:hdmitmds[0].enc|dreg[6]                                                                                          ; Merged with dummydata[7]                                                                                                             ;
; tmdsenc:hdmitmds[0].enc|dreg[7]                                                                                          ; Merged with dummydata[8]                                                                                                             ;
; tmdsenc:hdmitmds[1].enc|dreg[0]                                                                                          ; Merged with dummydata[9]                                                                                                             ;
; tmdsenc:hdmitmds[1].enc|dreg[1]                                                                                          ; Merged with dummydata[10]                                                                                                            ;
; tmdsenc:hdmitmds[1].enc|dreg[2]                                                                                          ; Merged with dummydata[11]                                                                                                            ;
; tmdsenc:hdmitmds[1].enc|dreg[3]                                                                                          ; Merged with dummydata[12]                                                                                                            ;
; tmdsenc:hdmitmds[1].enc|dreg[4]                                                                                          ; Merged with dummydata[13]                                                                                                            ;
; tmdsenc:hdmitmds[1].enc|dreg[5]                                                                                          ; Merged with dummydata[14]                                                                                                            ;
; tmdsenc:hdmitmds[1].enc|dreg[6]                                                                                          ; Merged with dummydata[15]                                                                                                            ;
; tmdsenc:hdmitmds[1].enc|dreg[7]                                                                                          ; Merged with dummydata[16]                                                                                                            ;
; tmdsenc:hdmitmds[2].enc|dreg[0]                                                                                          ; Merged with dummydata[17]                                                                                                            ;
; tmdsenc:hdmitmds[2].enc|dreg[1]                                                                                          ; Merged with dummydata[18]                                                                                                            ;
; tmdsenc:hdmitmds[2].enc|dreg[2]                                                                                          ; Merged with dummydata[19]                                                                                                            ;
; tmdsenc:hdmitmds[2].enc|dreg[3]                                                                                          ; Merged with dummydata[20]                                                                                                            ;
; tmdsenc:hdmitmds[2].enc|dreg[4]                                                                                          ; Merged with dummydata[21]                                                                                                            ;
; tmdsenc:hdmitmds[2].enc|dreg[5]                                                                                          ; Merged with dummydata[22]                                                                                                            ;
; tmdsenc:hdmitmds[2].enc|dreg[6]                                                                                          ; Merged with dummydata[23]                                                                                                            ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe1a                                  ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[7] ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ;
; tmdsenc:hdmitmds[1].enc|denreg                                                                                           ; Merged with tmdsenc:hdmitmds[0].enc|denreg                                                                                           ;
; tmdsenc:hdmitmds[2].enc|denreg                                                                                           ; Merged with tmdsenc:hdmitmds[0].enc|denreg                                                                                           ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[5] ; Merged with hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ;
; Total Number of Removed Registers = 49                                                                                   ;                                                                                                                                      ;
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                     ;
+--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                            ; Reason for Removal        ; Registers Removed due to This Register                                                                                   ;
+--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep                                             ; Stuck at GND              ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg,                                    ;
;                                                                                                                          ; due to stuck port clock   ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2],           ;
;                                                                                                                          ;                           ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0],           ;
;                                                                                                                          ;                           ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7] ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9] ; Stuck at GND              ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8] ;
;                                                                                                                          ; due to stuck port data_in ;                                                                                                                          ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9] ; Stuck at GND              ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8] ;
;                                                                                                                          ; due to stuck port data_in ;                                                                                                                          ;
+--------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 218   ;
; Number of registers using Synchronous Clear  ; 18    ;
; Number of registers using Synchronous Load   ; 9     ;
; Number of registers using Asynchronous Clear ; 85    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 39    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; tmdsenc:hdmitmds[2].enc|qreg[7]         ; 1       ;
; tmdsenc:hdmitmds[0].enc|qreg[3]         ; 1       ;
; tmdsenc:hdmitmds[1].enc|qreg[3]         ; 1       ;
; dummydata[0]                            ; 5       ;
; dummydata[23]                           ; 5       ;
; dummydata[22]                           ; 6       ;
; dummydata[19]                           ; 7       ;
; tmdsenc:hdmitmds[0].enc|qreg[7]         ; 1       ;
; dummydata[7]                            ; 5       ;
; dummydata[8]                            ; 5       ;
; dummydata[1]                            ; 11      ;
; dummydata[2]                            ; 6       ;
; tmdsenc:hdmitmds[1].enc|qreg[7]         ; 1       ;
; dummydata[11]                           ; 7       ;
; dummydata[12]                           ; 6       ;
; dummydata[9]                            ; 11      ;
; dummydata[15]                           ; 5       ;
; dummydata[13]                           ; 7       ;
; dummydata[14]                           ; 6       ;
; tmdsenc:hdmitmds[2].enc|qreg[5]         ; 1       ;
; tmdsenc:hdmitmds[2].enc|qreg[9]         ; 1       ;
; tmdsenc:hdmitmds[0].enc|qreg[5]         ; 1       ;
; tmdsenc:hdmitmds[1].enc|qreg[5]         ; 1       ;
; tmdsenc:hdmitmds[0].enc|qreg[9]         ; 1       ;
; tmdsenc:hdmitmds[1].enc|qreg[9]         ; 1       ;
; tmdsenc:hdmitmds[2].enc|qreg[3]         ; 1       ;
; Total number of inverted registers = 26 ;         ;
+-----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[4] ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[2] ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[4] ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[2].enc|qreg[5] ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[0].enc|qreg[5] ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |max80|tmdsenc:hdmitmds[1].enc|qreg[7] ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[2].enc|Add8    ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[0].enc|Add8    ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[1].enc|Add8    ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[2].enc|Add8    ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[0].enc|Add8    ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |max80|tmdsenc:hdmitmds[1].enc|Add8    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+


+----------------------------------------------------------------------------------+
; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated ;
+------------------------------+-------------+------+------------------------------+
; Assignment                   ; Value       ; From ; To                           ;
+------------------------------+-------------+------+------------------------------+
; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; remap_decoy_le3a_0           ;
; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; remap_decoy_le3a_1           ;
; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; remap_decoy_le3a_2           ;
; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; remap_decoy_le3a_0           ;
; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; remap_decoy_le3a_1           ;
; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; remap_decoy_le3a_2           ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; remap_decoy_le3a_0           ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; remap_decoy_le3a_1           ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; remap_decoy_le3a_2           ;
+------------------------------+-------------+------+------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ;
+------------------------------+-------------+------+---------------------------------------------------------------------------+
; Assignment                   ; Value       ; From ; To                                                                        ;
+------------------------------+-------------+------+---------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; -                                                                         ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; -                                                                         ;
; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; -                                                                         ;
+------------------------------+-------------+------+---------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ;
+------------------------------+-------------+------+----------------------------------------------------------------------------+
; Assignment                   ; Value       ; From ; To                                                                         ;
+------------------------------+-------------+------+----------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; -                                                                          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; -                                                                          ;
; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; -                                                                          ;
+------------------------------+-------------+------+----------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ;
+------------------------------+-------------+------+-----------------------------------------------------------------------------+
; Assignment                   ; Value       ; From ; To                                                                          ;
+------------------------------+-------------+------+-----------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED      ; NEVER_ALLOW ; -    ; -                                                                           ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF         ; -    ; -                                                                           ;
; IGNORE_LCELL_BUFFERS         ; OFF         ; -    ; -                                                                           ;
+------------------------------+-------------+------+-----------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated ;
+-----------------+-------+------+-------------------------------------------------------------------+
; Assignment      ; Value ; From ; To                                                                ;
+-----------------+-------+------+-------------------------------------------------------------------+
; AUTO_MERGE_PLLS ; OFF   ; -    ; lvds_tx_pll                                                       ;
+-----------------+-------+------+-------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out ;
+-----------------------------+---------+------+------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                           ;
+-----------------------------+---------+------+------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                            ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                            ;
+-----------------------------+---------+------+------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio ;
+-----------------------------+---------+------+------------------------------------------------------------------------------------+
; Assignment                  ; Value   ; From ; To                                                                                 ;
+-----------------------------+---------+------+------------------------------------------------------------------------------------+
; SYNCHRONIZER_IDENTIFICATION ; OFF     ; -    ; -                                                                                  ;
; ADV_NETLIST_OPT_ALLOWED     ; DEFAULT ; -    ; -                                                                                  ;
+-----------------------------+---------+------+------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |max80 ;
+------------------+--------+-------------------------------------------+
; Parameter Name   ; Value  ; Type                                      ;
+------------------+--------+-------------------------------------------+
; mosfet_installed ; 000000 ; Unsigned Binary                           ;
; reset_pow2       ; 12     ; Signed Integer                            ;
+------------------+--------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pll:pll|altpll:altpll_component ;
+-------------------------------+-----------------------+----------------------+
; Parameter Name                ; Value                 ; Type                 ;
+-------------------------------+-----------------------+----------------------+
; OPERATION_MODE                ; NORMAL                ; Untyped              ;
; PLL_TYPE                      ; AUTO                  ; Untyped              ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=pll ; Untyped              ;
; QUALIFY_CONF_DONE             ; OFF                   ; Untyped              ;
; COMPENSATE_CLOCK              ; CLK0                  ; Untyped              ;
; SCAN_CHAIN                    ; LONG                  ; Untyped              ;
; PRIMARY_CLOCK                 ; INCLK0                ; Untyped              ;
; INCLK0_INPUT_FREQUENCY        ; 20833                 ; Signed Integer       ;
; INCLK1_INPUT_FREQUENCY        ; 0                     ; Untyped              ;
; GATE_LOCK_SIGNAL              ; NO                    ; Untyped              ;
; GATE_LOCK_COUNTER             ; 0                     ; Untyped              ;
; LOCK_HIGH                     ; 1                     ; Untyped              ;
; LOCK_LOW                      ; 1                     ; Untyped              ;
; VALID_LOCK_MULTIPLIER         ; 1                     ; Untyped              ;
; INVALID_LOCK_MULTIPLIER       ; 5                     ; Untyped              ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                   ; Untyped              ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                   ; Untyped              ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                   ; Untyped              ;
; SKIP_VCO                      ; OFF                   ; Untyped              ;
; SWITCH_OVER_COUNTER           ; 0                     ; Untyped              ;
; SWITCH_OVER_TYPE              ; AUTO                  ; Untyped              ;
; FEEDBACK_SOURCE               ; EXTCLK0               ; Untyped              ;
; BANDWIDTH                     ; 0                     ; Untyped              ;
; BANDWIDTH_TYPE                ; HIGH                  ; Untyped              ;
; SPREAD_FREQUENCY              ; 0                     ; Untyped              ;
; DOWN_SPREAD                   ; 0                     ; Untyped              ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                   ; Untyped              ;
; SELF_RESET_ON_LOSS_LOCK       ; ON                    ; Untyped              ;
; CLK9_MULTIPLY_BY              ; 0                     ; Untyped              ;
; CLK8_MULTIPLY_BY              ; 0                     ; Untyped              ;
; CLK7_MULTIPLY_BY              ; 0                     ; Untyped              ;
; CLK6_MULTIPLY_BY              ; 0                     ; Untyped              ;
; CLK5_MULTIPLY_BY              ; 1                     ; Untyped              ;
; CLK4_MULTIPLY_BY              ; 1                     ; Untyped              ;
; CLK3_MULTIPLY_BY              ; 1                     ; Untyped              ;
; CLK2_MULTIPLY_BY              ; 3                     ; Signed Integer       ;
; CLK1_MULTIPLY_BY              ; 2                     ; Signed Integer       ;
; CLK0_MULTIPLY_BY              ; 2                     ; Signed Integer       ;
; CLK9_DIVIDE_BY                ; 0                     ; Untyped              ;
; CLK8_DIVIDE_BY                ; 0                     ; Untyped              ;
; CLK7_DIVIDE_BY                ; 0                     ; Untyped              ;
; CLK6_DIVIDE_BY                ; 0                     ; Untyped              ;
; CLK5_DIVIDE_BY                ; 1                     ; Untyped              ;
; CLK4_DIVIDE_BY                ; 1                     ; Untyped              ;
; CLK3_DIVIDE_BY                ; 1                     ; Untyped              ;
; CLK2_DIVIDE_BY                ; 4                     ; Signed Integer       ;
; CLK1_DIVIDE_BY                ; 1                     ; Signed Integer       ;
; CLK0_DIVIDE_BY                ; 1                     ; Signed Integer       ;
; CLK9_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK8_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK7_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK6_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK5_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK4_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK3_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK2_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK1_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK0_PHASE_SHIFT              ; 0                     ; Untyped              ;
; CLK5_TIME_DELAY               ; 0                     ; Untyped              ;
; CLK4_TIME_DELAY               ; 0                     ; Untyped              ;
; CLK3_TIME_DELAY               ; 0                     ; Untyped              ;
; CLK2_TIME_DELAY               ; 0                     ; Untyped              ;
; CLK1_TIME_DELAY               ; 0                     ; Untyped              ;
; CLK0_TIME_DELAY               ; 0                     ; Untyped              ;
; CLK9_DUTY_CYCLE               ; 50                    ; Untyped              ;
; CLK8_DUTY_CYCLE               ; 50                    ; Untyped              ;
; CLK7_DUTY_CYCLE               ; 50                    ; Untyped              ;
; CLK6_DUTY_CYCLE               ; 50                    ; Untyped              ;
; CLK5_DUTY_CYCLE               ; 50                    ; Untyped              ;
; CLK4_DUTY_CYCLE               ; 50                    ; Untyped              ;
; CLK3_DUTY_CYCLE               ; 50                    ; Untyped              ;
; CLK2_DUTY_CYCLE               ; 50                    ; Signed Integer       ;
; CLK1_DUTY_CYCLE               ; 50                    ; Signed Integer       ;
; CLK0_DUTY_CYCLE               ; 50                    ; Signed Integer       ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                   ; Untyped              ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                   ; Untyped              ;
; LOCK_WINDOW_UI                ;  0.05                 ; Untyped              ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                ; Untyped              ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                ; Untyped              ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                ; Untyped              ;
; DPA_MULTIPLY_BY               ; 0                     ; Untyped              ;
; DPA_DIVIDE_BY                 ; 1                     ; Untyped              ;
; DPA_DIVIDER                   ; 0                     ; Untyped              ;
; EXTCLK3_MULTIPLY_BY           ; 1                     ; Untyped              ;
; EXTCLK2_MULTIPLY_BY           ; 1                     ; Untyped              ;
; EXTCLK1_MULTIPLY_BY           ; 1                     ; Untyped              ;
; EXTCLK0_MULTIPLY_BY           ; 1                     ; Untyped              ;
; EXTCLK3_DIVIDE_BY             ; 1                     ; Untyped              ;
; EXTCLK2_DIVIDE_BY             ; 1                     ; Untyped              ;
; EXTCLK1_DIVIDE_BY             ; 1                     ; Untyped              ;
; EXTCLK0_DIVIDE_BY             ; 1                     ; Untyped              ;
; EXTCLK3_PHASE_SHIFT           ; 0                     ; Untyped              ;
; EXTCLK2_PHASE_SHIFT           ; 0                     ; Untyped              ;
; EXTCLK1_PHASE_SHIFT           ; 0                     ; Untyped              ;
; EXTCLK0_PHASE_SHIFT           ; 0                     ; Untyped              ;
; EXTCLK3_TIME_DELAY            ; 0                     ; Untyped              ;
; EXTCLK2_TIME_DELAY            ; 0                     ; Untyped              ;
; EXTCLK1_TIME_DELAY            ; 0                     ; Untyped              ;
; EXTCLK0_TIME_DELAY            ; 0                     ; Untyped              ;
; EXTCLK3_DUTY_CYCLE            ; 50                    ; Untyped              ;
; EXTCLK2_DUTY_CYCLE            ; 50                    ; Untyped              ;
; EXTCLK1_DUTY_CYCLE            ; 50                    ; Untyped              ;
; EXTCLK0_DUTY_CYCLE            ; 50                    ; Untyped              ;
; VCO_MULTIPLY_BY               ; 0                     ; Untyped              ;
; VCO_DIVIDE_BY                 ; 0                     ; Untyped              ;
; SCLKOUT0_PHASE_SHIFT          ; 0                     ; Untyped              ;
; SCLKOUT1_PHASE_SHIFT          ; 0                     ; Untyped              ;
; VCO_MIN                       ; 0                     ; Untyped              ;
; VCO_MAX                       ; 0                     ; Untyped              ;
; VCO_CENTER                    ; 0                     ; Untyped              ;
; PFD_MIN                       ; 0                     ; Untyped              ;
; PFD_MAX                       ; 0                     ; Untyped              ;
; M_INITIAL                     ; 0                     ; Untyped              ;
; M                             ; 0                     ; Untyped              ;
; N                             ; 1                     ; Untyped              ;
; M2                            ; 1                     ; Untyped              ;
; N2                            ; 1                     ; Untyped              ;
; SS                            ; 1                     ; Untyped              ;
; C0_HIGH                       ; 0                     ; Untyped              ;
; C1_HIGH                       ; 0                     ; Untyped              ;
; C2_HIGH                       ; 0                     ; Untyped              ;
; C3_HIGH                       ; 0                     ; Untyped              ;
; C4_HIGH                       ; 0                     ; Untyped              ;
; C5_HIGH                       ; 0                     ; Untyped              ;
; C6_HIGH                       ; 0                     ; Untyped              ;
; C7_HIGH                       ; 0                     ; Untyped              ;
; C8_HIGH                       ; 0                     ; Untyped              ;
; C9_HIGH                       ; 0                     ; Untyped              ;
; C0_LOW                        ; 0                     ; Untyped              ;
; C1_LOW                        ; 0                     ; Untyped              ;
; C2_LOW                        ; 0                     ; Untyped              ;
; C3_LOW                        ; 0                     ; Untyped              ;
; C4_LOW                        ; 0                     ; Untyped              ;
; C5_LOW                        ; 0                     ; Untyped              ;
; C6_LOW                        ; 0                     ; Untyped              ;
; C7_LOW                        ; 0                     ; Untyped              ;
; C8_LOW                        ; 0                     ; Untyped              ;
; C9_LOW                        ; 0                     ; Untyped              ;
; C0_INITIAL                    ; 0                     ; Untyped              ;
; C1_INITIAL                    ; 0                     ; Untyped              ;
; C2_INITIAL                    ; 0                     ; Untyped              ;
; C3_INITIAL                    ; 0                     ; Untyped              ;
; C4_INITIAL                    ; 0                     ; Untyped              ;
; C5_INITIAL                    ; 0                     ; Untyped              ;
; C6_INITIAL                    ; 0                     ; Untyped              ;
; C7_INITIAL                    ; 0                     ; Untyped              ;
; C8_INITIAL                    ; 0                     ; Untyped              ;
; C9_INITIAL                    ; 0                     ; Untyped              ;
; C0_MODE                       ; BYPASS                ; Untyped              ;
; C1_MODE                       ; BYPASS                ; Untyped              ;
; C2_MODE                       ; BYPASS                ; Untyped              ;
; C3_MODE                       ; BYPASS                ; Untyped              ;
; C4_MODE                       ; BYPASS                ; Untyped              ;
; C5_MODE                       ; BYPASS                ; Untyped              ;
; C6_MODE                       ; BYPASS                ; Untyped              ;
; C7_MODE                       ; BYPASS                ; Untyped              ;
; C8_MODE                       ; BYPASS                ; Untyped              ;
; C9_MODE                       ; BYPASS                ; Untyped              ;
; C0_PH                         ; 0                     ; Untyped              ;
; C1_PH                         ; 0                     ; Untyped              ;
; C2_PH                         ; 0                     ; Untyped              ;
; C3_PH                         ; 0                     ; Untyped              ;
; C4_PH                         ; 0                     ; Untyped              ;
; C5_PH                         ; 0                     ; Untyped              ;
; C6_PH                         ; 0                     ; Untyped              ;
; C7_PH                         ; 0                     ; Untyped              ;
; C8_PH                         ; 0                     ; Untyped              ;
; C9_PH                         ; 0                     ; Untyped              ;
; L0_HIGH                       ; 1                     ; Untyped              ;
; L1_HIGH                       ; 1                     ; Untyped              ;
; G0_HIGH                       ; 1                     ; Untyped              ;
; G1_HIGH                       ; 1                     ; Untyped              ;
; G2_HIGH                       ; 1                     ; Untyped              ;
; G3_HIGH                       ; 1                     ; Untyped              ;
; E0_HIGH                       ; 1                     ; Untyped              ;
; E1_HIGH                       ; 1                     ; Untyped              ;
; E2_HIGH                       ; 1                     ; Untyped              ;
; E3_HIGH                       ; 1                     ; Untyped              ;
; L0_LOW                        ; 1                     ; Untyped              ;
; L1_LOW                        ; 1                     ; Untyped              ;
; G0_LOW                        ; 1                     ; Untyped              ;
; G1_LOW                        ; 1                     ; Untyped              ;
; G2_LOW                        ; 1                     ; Untyped              ;
; G3_LOW                        ; 1                     ; Untyped              ;
; E0_LOW                        ; 1                     ; Untyped              ;
; E1_LOW                        ; 1                     ; Untyped              ;
; E2_LOW                        ; 1                     ; Untyped              ;
; E3_LOW                        ; 1                     ; Untyped              ;
; L0_INITIAL                    ; 1                     ; Untyped              ;
; L1_INITIAL                    ; 1                     ; Untyped              ;
; G0_INITIAL                    ; 1                     ; Untyped              ;
; G1_INITIAL                    ; 1                     ; Untyped              ;
; G2_INITIAL                    ; 1                     ; Untyped              ;
; G3_INITIAL                    ; 1                     ; Untyped              ;
; E0_INITIAL                    ; 1                     ; Untyped              ;
; E1_INITIAL                    ; 1                     ; Untyped              ;
; E2_INITIAL                    ; 1                     ; Untyped              ;
; E3_INITIAL                    ; 1                     ; Untyped              ;
; L0_MODE                       ; BYPASS                ; Untyped              ;
; L1_MODE                       ; BYPASS                ; Untyped              ;
; G0_MODE                       ; BYPASS                ; Untyped              ;
; G1_MODE                       ; BYPASS                ; Untyped              ;
; G2_MODE                       ; BYPASS                ; Untyped              ;
; G3_MODE                       ; BYPASS                ; Untyped              ;
; E0_MODE                       ; BYPASS                ; Untyped              ;
; E1_MODE                       ; BYPASS                ; Untyped              ;
; E2_MODE                       ; BYPASS                ; Untyped              ;
; E3_MODE                       ; BYPASS                ; Untyped              ;
; L0_PH                         ; 0                     ; Untyped              ;
; L1_PH                         ; 0                     ; Untyped              ;
; G0_PH                         ; 0                     ; Untyped              ;
; G1_PH                         ; 0                     ; Untyped              ;
; G2_PH                         ; 0                     ; Untyped              ;
; G3_PH                         ; 0                     ; Untyped              ;
; E0_PH                         ; 0                     ; Untyped              ;
; E1_PH                         ; 0                     ; Untyped              ;
; E2_PH                         ; 0                     ; Untyped              ;
; E3_PH                         ; 0                     ; Untyped              ;
; M_PH                          ; 0                     ; Untyped              ;
; C1_USE_CASC_IN                ; OFF                   ; Untyped              ;
; C2_USE_CASC_IN                ; OFF                   ; Untyped              ;
; C3_USE_CASC_IN                ; OFF                   ; Untyped              ;
; C4_USE_CASC_IN                ; OFF                   ; Untyped              ;
; C5_USE_CASC_IN                ; OFF                   ; Untyped              ;
; C6_USE_CASC_IN                ; OFF                   ; Untyped              ;
; C7_USE_CASC_IN                ; OFF                   ; Untyped              ;
; C8_USE_CASC_IN                ; OFF                   ; Untyped              ;
; C9_USE_CASC_IN                ; OFF                   ; Untyped              ;
; CLK0_COUNTER                  ; G0                    ; Untyped              ;
; CLK1_COUNTER                  ; G0                    ; Untyped              ;
; CLK2_COUNTER                  ; G0                    ; Untyped              ;
; CLK3_COUNTER                  ; G0                    ; Untyped              ;
; CLK4_COUNTER                  ; G0                    ; Untyped              ;
; CLK5_COUNTER                  ; G0                    ; Untyped              ;
; CLK6_COUNTER                  ; E0                    ; Untyped              ;
; CLK7_COUNTER                  ; E1                    ; Untyped              ;
; CLK8_COUNTER                  ; E2                    ; Untyped              ;
; CLK9_COUNTER                  ; E3                    ; Untyped              ;
; L0_TIME_DELAY                 ; 0                     ; Untyped              ;
; L1_TIME_DELAY                 ; 0                     ; Untyped              ;
; G0_TIME_DELAY                 ; 0                     ; Untyped              ;
; G1_TIME_DELAY                 ; 0                     ; Untyped              ;
; G2_TIME_DELAY                 ; 0                     ; Untyped              ;
; G3_TIME_DELAY                 ; 0                     ; Untyped              ;
; E0_TIME_DELAY                 ; 0                     ; Untyped              ;
; E1_TIME_DELAY                 ; 0                     ; Untyped              ;
; E2_TIME_DELAY                 ; 0                     ; Untyped              ;
; E3_TIME_DELAY                 ; 0                     ; Untyped              ;
; M_TIME_DELAY                  ; 0                     ; Untyped              ;
; N_TIME_DELAY                  ; 0                     ; Untyped              ;
; EXTCLK3_COUNTER               ; E3                    ; Untyped              ;
; EXTCLK2_COUNTER               ; E2                    ; Untyped              ;
; EXTCLK1_COUNTER               ; E1                    ; Untyped              ;
; EXTCLK0_COUNTER               ; E0                    ; Untyped              ;
; ENABLE0_COUNTER               ; L0                    ; Untyped              ;
; ENABLE1_COUNTER               ; L0                    ; Untyped              ;
; CHARGE_PUMP_CURRENT           ; 2                     ; Untyped              ;
; LOOP_FILTER_R                 ;  1.000000             ; Untyped              ;
; LOOP_FILTER_C                 ; 5                     ; Untyped              ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                  ; Untyped              ;
; LOOP_FILTER_R_BITS            ; 9999                  ; Untyped              ;
; LOOP_FILTER_C_BITS            ; 9999                  ; Untyped              ;
; VCO_POST_SCALE                ; 0                     ; Untyped              ;
; CLK2_OUTPUT_FREQUENCY         ; 0                     ; Untyped              ;
; CLK1_OUTPUT_FREQUENCY         ; 0                     ; Untyped              ;
; CLK0_OUTPUT_FREQUENCY         ; 0                     ; Untyped              ;
; INTENDED_DEVICE_FAMILY        ; Cyclone IV E          ; Untyped              ;
; PORT_CLKENA0                  ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKENA1                  ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKENA2                  ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKENA3                  ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKENA4                  ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKENA5                  ; PORT_UNUSED           ; Untyped              ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_EXTCLK0                  ; PORT_UNUSED           ; Untyped              ;
; PORT_EXTCLK1                  ; PORT_UNUSED           ; Untyped              ;
; PORT_EXTCLK2                  ; PORT_UNUSED           ; Untyped              ;
; PORT_EXTCLK3                  ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKBAD0                  ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKBAD1                  ; PORT_UNUSED           ; Untyped              ;
; PORT_CLK0                     ; PORT_USED             ; Untyped              ;
; PORT_CLK1                     ; PORT_USED             ; Untyped              ;
; PORT_CLK2                     ; PORT_USED             ; Untyped              ;
; PORT_CLK3                     ; PORT_UNUSED           ; Untyped              ;
; PORT_CLK4                     ; PORT_UNUSED           ; Untyped              ;
; PORT_CLK5                     ; PORT_UNUSED           ; Untyped              ;
; PORT_CLK6                     ; PORT_UNUSED           ; Untyped              ;
; PORT_CLK7                     ; PORT_UNUSED           ; Untyped              ;
; PORT_CLK8                     ; PORT_UNUSED           ; Untyped              ;
; PORT_CLK9                     ; PORT_UNUSED           ; Untyped              ;
; PORT_SCANDATA                 ; PORT_UNUSED           ; Untyped              ;
; PORT_SCANDATAOUT              ; PORT_UNUSED           ; Untyped              ;
; PORT_SCANDONE                 ; PORT_UNUSED           ; Untyped              ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKLOSS                  ; PORT_UNUSED           ; Untyped              ;
; PORT_INCLK1                   ; PORT_UNUSED           ; Untyped              ;
; PORT_INCLK0                   ; PORT_USED             ; Untyped              ;
; PORT_FBIN                     ; PORT_UNUSED           ; Untyped              ;
; PORT_PLLENA                   ; PORT_UNUSED           ; Untyped              ;
; PORT_CLKSWITCH                ; PORT_UNUSED           ; Untyped              ;
; PORT_ARESET                   ; PORT_USED             ; Untyped              ;
; PORT_PFDENA                   ; PORT_UNUSED           ; Untyped              ;
; PORT_SCANCLK                  ; PORT_USED             ; Untyped              ;
; PORT_SCANACLR                 ; PORT_UNUSED           ; Untyped              ;
; PORT_SCANREAD                 ; PORT_UNUSED           ; Untyped              ;
; PORT_SCANWRITE                ; PORT_UNUSED           ; Untyped              ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_LOCKED                   ; PORT_USED             ; Untyped              ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED           ; Untyped              ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_PHASEDONE                ; PORT_USED             ; Untyped              ;
; PORT_PHASESTEP                ; PORT_USED             ; Untyped              ;
; PORT_PHASEUPDOWN              ; PORT_USED             ; Untyped              ;
; PORT_SCANCLKENA               ; PORT_UNUSED           ; Untyped              ;
; PORT_PHASECOUNTERSELECT       ; PORT_USED             ; Untyped              ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY     ; Untyped              ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY     ; Untyped              ;
; M_TEST_SOURCE                 ; 5                     ; Untyped              ;
; C0_TEST_SOURCE                ; 5                     ; Untyped              ;
; C1_TEST_SOURCE                ; 5                     ; Untyped              ;
; C2_TEST_SOURCE                ; 5                     ; Untyped              ;
; C3_TEST_SOURCE                ; 5                     ; Untyped              ;
; C4_TEST_SOURCE                ; 5                     ; Untyped              ;
; C5_TEST_SOURCE                ; 5                     ; Untyped              ;
; C6_TEST_SOURCE                ; 5                     ; Untyped              ;
; C7_TEST_SOURCE                ; 5                     ; Untyped              ;
; C8_TEST_SOURCE                ; 5                     ; Untyped              ;
; C9_TEST_SOURCE                ; 5                     ; Untyped              ;
; CBXI_PARAMETER                ; pll_altpll            ; Untyped              ;
; VCO_FREQUENCY_CONTROL         ; AUTO                  ; Untyped              ;
; VCO_PHASE_SHIFT_STEP          ; 0                     ; Untyped              ;
; WIDTH_CLOCK                   ; 5                     ; Signed Integer       ;
; WIDTH_PHASECOUNTERSELECT      ; 3                     ; Signed Integer       ;
; USING_FBMIMICBIDIR_PORT       ; OFF                   ; Untyped              ;
; DEVICE_FAMILY                 ; Cyclone IV E          ; Untyped              ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                ; Untyped              ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                   ; Untyped              ;
; AUTO_CARRY_CHAINS             ; ON                    ; AUTO_CARRY           ;
; IGNORE_CARRY_BUFFERS          ; OFF                   ; IGNORE_CARRY         ;
; AUTO_CASCADE_CHAINS           ; ON                    ; AUTO_CASCADE         ;
; IGNORE_CASCADE_BUFFERS        ; OFF                   ; IGNORE_CASCADE       ;
+-------------------------------+-----------------------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: transpose:hdmitranspose ;
+----------------+-------+---------------------------------------------+
; Parameter Name ; Value ; Type                                        ;
+----------------+-------+---------------------------------------------+
; words          ; 3     ; Signed Integer                              ;
; bits           ; 10    ; Signed Integer                              ;
; reverse_w      ; 0     ; Signed Integer                              ;
; reverse_b      ; 1     ; Signed Integer                              ;
; reg_d          ; 0     ; Signed Integer                              ;
; reg_q          ; 0     ; Signed Integer                              ;
; transpose      ; 1     ; Signed Integer                              ;
+----------------+-------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:dreg ;
+----------------+-------+----------------------------------------------------------+
; Parameter Name ; Value ; Type                                                     ;
+----------------+-------+----------------------------------------------------------+
; bits           ; 30    ; Signed Integer                                           ;
; register       ; 0     ; Signed Integer                                           ;
+----------------+-------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:qreg ;
+----------------+-------+----------------------------------------------------------+
; Parameter Name ; Value ; Type                                                     ;
+----------------+-------+----------------------------------------------------------+
; bits           ; 30    ; Signed Integer                                           ;
; register       ; 0     ; Signed Integer                                           ;
+----------------+-------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component ;
+-----------------------------+----------------+---------------------------------------------+
; Parameter Name              ; Value          ; Type                                        ;
+-----------------------------+----------------+---------------------------------------------+
; AUTO_CARRY_CHAINS           ; ON             ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS        ; OFF            ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS         ; ON             ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS      ; OFF            ; IGNORE_CASCADE                              ;
; NUMBER_OF_CHANNELS          ; 3              ; Signed Integer                              ;
; DESERIALIZATION_FACTOR      ; 10             ; Signed Integer                              ;
; REGISTERED_INPUT            ; TX_CORECLK     ; Untyped                                     ;
; MULTI_CLOCK                 ; OFF            ; Untyped                                     ;
; INCLOCK_PERIOD              ; 27778          ; Signed Integer                              ;
; OUTCLOCK_DIVIDE_BY          ; 10             ; Signed Integer                              ;
; INCLOCK_BOOST               ; 0              ; Signed Integer                              ;
; CENTER_ALIGN_MSB            ; UNUSED         ; Untyped                                     ;
; INTENDED_DEVICE_FAMILY      ; Cyclone IV E   ; Untyped                                     ;
; DEVICE_FAMILY               ; Cyclone IV E   ; Untyped                                     ;
; OUTPUT_DATA_RATE            ; 360            ; Signed Integer                              ;
; INCLOCK_DATA_ALIGNMENT      ; EDGE_ALIGNED   ; Untyped                                     ;
; OUTCLOCK_ALIGNMENT          ; EDGE_ALIGNED   ; Untyped                                     ;
; INCLOCK_PHASE_SHIFT         ; 0              ; Signed Integer                              ;
; OUTCLOCK_PHASE_SHIFT        ; 0              ; Signed Integer                              ;
; COMMON_RX_TX_PLL            ; OFF            ; Untyped                                     ;
; OUTCLOCK_RESOURCE           ; AUTO           ; Untyped                                     ;
; USE_EXTERNAL_PLL            ; OFF            ; Untyped                                     ;
; PREEMPHASIS_SETTING         ; 0              ; Signed Integer                              ;
; VOD_SETTING                 ; 0              ; Signed Integer                              ;
; DIFFERENTIAL_DRIVE          ; 0              ; Signed Integer                              ;
; CORECLOCK_DIVIDE_BY         ; 2              ; Signed Integer                              ;
; ENABLE_CLK_LATENCY          ; OFF            ; Untyped                                     ;
; OUTCLOCK_DUTY_CYCLE         ; 50             ; Signed Integer                              ;
; PLL_BANDWIDTH_TYPE          ; AUTO           ; Untyped                                     ;
; IMPLEMENT_IN_LES            ; ON             ; Untyped                                     ;
; PLL_SELF_RESET_ON_LOSS_LOCK ; ON             ; Untyped                                     ;
; CBXI_PARAMETER              ; hdmitx_lvds_tx ; Untyped                                     ;
+-----------------------------+----------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                    ;
+-------------------------------+---------------------------------+
; Name                          ; Value                           ;
+-------------------------------+---------------------------------+
; Number of entity instances    ; 1                               ;
; Entity Instance               ; pll:pll|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                          ;
;     -- PLL_TYPE               ; AUTO                            ;
;     -- PRIMARY_CLOCK          ; INCLK0                          ;
;     -- INCLK0_INPUT_FREQUENCY ; 20833                           ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                               ;
;     -- VCO_MULTIPLY_BY        ; 0                               ;
;     -- VCO_DIVIDE_BY          ; 0                               ;
+-------------------------------+---------------------------------+


+---------------------------------------------------------+
; Port Connectivity Checks: "hdmitx:hdmitx"               ;
+------------+--------+----------+------------------------+
; Port       ; Type   ; Severity ; Details                ;
+------------+--------+----------+------------------------+
; pll_areset ; Input  ; Info     ; Stuck at GND           ;
; tx_locked  ; Output ; Info     ; Explicitly unconnected ;
+------------+--------+----------+------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "transpose:hdmitranspose"                                                                                                                    ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Port ; Type  ; Severity ; Details                                                                                                                                      ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
; clk  ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
+------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Port Connectivity Checks: "tmdsenc:hdmitmds[2].enc" ;
+------+-------+----------+---------------------------+
; Port ; Type  ; Severity ; Details                   ;
+------+-------+----------+---------------------------+
; den  ; Input ; Info     ; Stuck at VCC              ;
; c    ; Input ; Info     ; Stuck at GND              ;
+------+-------+----------+---------------------------+


+-----------------------------------------------------+
; Port Connectivity Checks: "tmdsenc:hdmitmds[1].enc" ;
+------+-------+----------+---------------------------+
; Port ; Type  ; Severity ; Details                   ;
+------+-------+----------+---------------------------+
; den  ; Input ; Info     ; Stuck at VCC              ;
; c    ; Input ; Info     ; Stuck at GND              ;
+------+-------+----------+---------------------------+


+-----------------------------------------------------+
; Port Connectivity Checks: "tmdsenc:hdmitmds[0].enc" ;
+------+-------+----------+---------------------------+
; Port ; Type  ; Severity ; Details                   ;
+------+-------+----------+---------------------------+
; den  ; Input ; Info     ; Stuck at VCC              ;
; c    ; Input ; Info     ; Stuck at GND              ;
+------+-------+----------+---------------------------+


+-----------------------------------------------------------------+
; Port Connectivity Checks: "pll:pll"                             ;
+--------------------+--------+----------+------------------------+
; Port               ; Type   ; Severity ; Details                ;
+--------------------+--------+----------+------------------------+
; areset             ; Input  ; Info     ; Stuck at GND           ;
; phasestep          ; Input  ; Info     ; Stuck at GND           ;
; phasecounterselect ; Input  ; Info     ; Stuck at GND           ;
; phaseupdown        ; Input  ; Info     ; Stuck at VCC           ;
; scanclk            ; Input  ; Info     ; Stuck at GND           ;
; phasedone          ; Output ; Info     ; Explicitly unconnected ;
+--------------------+--------+----------+------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 139                         ;
; cycloneiii_ddio_out   ; 4                           ;
; cycloneiii_ff         ; 218                         ;
;     CLR               ; 46                          ;
;     CLR SCLR          ; 18                          ;
;     CLR SLD           ; 9                           ;
;     ENA               ; 27                          ;
;     ENA CLR           ; 12                          ;
;     plain             ; 106                         ;
; cycloneiii_io_obuf    ; 58                          ;
; cycloneiii_lcell_comb ; 278                         ;
;     arith             ; 56                          ;
;         2 data inputs ; 39                          ;
;         3 data inputs ; 17                          ;
;     normal            ; 222                         ;
;         0 data inputs ; 8                           ;
;         1 data inputs ; 24                          ;
;         2 data inputs ; 37                          ;
;         3 data inputs ; 48                          ;
;         4 data inputs ; 105                         ;
; cycloneiii_pll        ; 2                           ;
;                       ;                             ;
; Max LUT depth         ; 7.20                        ;
; Average LUT depth     ; 2.81                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:00     ;
+----------------+--------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
    Info: Processing started: Fri Aug  6 20:12:35 2021
Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file ip/hdmitx.v
    Info (12023): Found entity 1: hdmitx File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 40
Info (12021): Found 1 design units, including 1 entities, in source file ip/pll.v
    Info (12023): Found entity 1: pll File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 40
Info (12021): Found 3 design units, including 3 entities, in source file transpose.sv
    Info (12023): Found entity 1: condreg File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 4
    Info (12023): Found entity 2: transpose File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 35
    Info (12023): Found entity 3: reverse File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 79
Warning (12019): Can't analyze file -- file syncho.sv is missing
Warning (10229): Verilog HDL Expression warning at tmdsenc.sv(84): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 84
Warning (10259): Verilog HDL error at tmdsenc.sv(93): constant value overflow File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 93
Warning (10229): Verilog HDL Expression warning at tmdsenc.sv(117): truncated literal to match 10 bits File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 117
Info (12021): Found 1 design units, including 1 entities, in source file tmdsenc.sv
    Info (12023): Found entity 1: tmdsenc File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 73
Info (12021): Found 1 design units, including 1 entities, in source file max80.sv
    Info (12023): Found entity 1: max80 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 11
Warning (10236): Verilog HDL Implicit Net warning at max80.sv(185): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 185
Info (12127): Elaborating entity "max80" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at max80.sv(185): object "hdmi_sck" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 185
Warning (10036): Verilog HDL or VHDL warning at max80.sv(217): object "abc_xmemrd" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 217
Warning (10036): Verilog HDL or VHDL warning at max80.sv(218): object "abc_xmemwr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 218
Warning (10036): Verilog HDL or VHDL warning at max80.sv(221): object "abc_iord" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 221
Warning (10036): Verilog HDL or VHDL warning at max80.sv(222): object "abc_iowr" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 222
Warning (10858): Verilog HDL warning at max80.sv(225): object abc_wait used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 225
Warning (10858): Verilog HDL warning at max80.sv(226): object abc_resin used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 226
Warning (10858): Verilog HDL warning at max80.sv(227): object abc_int used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 227
Warning (10858): Verilog HDL warning at max80.sv(228): object abc_nmi used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 228
Warning (10858): Verilog HDL warning at max80.sv(229): object abc_xm used but never assigned File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 229
Warning (10036): Verilog HDL or VHDL warning at max80.sv(268): object "exth_d" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
Warning (10230): Verilog HDL assignment warning at max80.sv(156): truncated value with size 30 to match size of target (24) File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 156
Warning (10040): Verilog HDL or VHDL arithmetic warning at max80.sv(299): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 299
Warning (10030): Net "abc_wait" at max80.sv(225) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 225
Warning (10030): Net "abc_resin" at max80.sv(226) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 226
Warning (10030): Net "abc_int" at max80.sv(227) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 227
Warning (10030): Net "abc_nmi" at max80.sv(228) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 228
Warning (10030): Net "abc_xm" at max80.sv(229) has no driver or initial value, using a default initial value '0' File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 229
Warning (10034): Output port "abc_d_oe" at max80.sv(19) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
Warning (10034): Output port "abc_master" at max80.sv(38) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
Warning (10034): Output port "abc_a_oe" at max80.sv(39) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
Warning (10034): Output port "abc_d_ce_n" at max80.sv(41) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 41
Warning (10034): Output port "flash_cs_n" at max80.sv(80) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
Warning (10034): Output port "flash_clk" at max80.sv(81) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
Warning (10034): Output port "flash_mosi" at max80.sv(82) has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 82
Warning (10862): input port "abc_a" at max80.sv(17) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
Warning (10863): bidir port "abc_d" at max80.sv(18) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
Warning (10862): bidir port "abc_d" at max80.sv(18) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
Warning (10862): input port "abc_out_n" at max80.sv(22) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
Warning (10862): input port "abc_inp_n" at max80.sv(23) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
Warning (10862): bidir port "sr_dq" at max80.sv(60) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
Warning (10862): bidir port "sd_dat" at max80.sv(70) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
Warning (10862): bidir port "gpio" at max80.sv(106) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
Warning (10862): input port "abc_clk" at max80.sv(16) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
Warning (10862): input port "abc_rst_n" at max80.sv(20) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
Warning (10862): input port "abc_cs_n" at max80.sv(21) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
Warning (10862): input port "abc_xmemfl_n" at max80.sv(24) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
Warning (10862): input port "abc_xmemw800_n" at max80.sv(25) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
Warning (10862): input port "abc_xmemw80_n" at max80.sv(26) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
Warning (10862): bidir port "exth_ha" at max80.sv(46) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
Warning (10862): bidir port "exth_hb" at max80.sv(47) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
Warning (10862): input port "exth_hc" at max80.sv(48) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
Warning (10862): bidir port "exth_hd" at max80.sv(49) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
Warning (10862): bidir port "exth_he" at max80.sv(50) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
Warning (10862): bidir port "exth_hf" at max80.sv(51) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
Warning (10862): bidir port "exth_hg" at max80.sv(52) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
Warning (10862): input port "exth_hh" at max80.sv(53) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
Warning (10862): input port "tty_txd" at max80.sv(73) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 73
Warning (10862): input port "tty_rts" at max80.sv(75) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
Warning (10862): input port "tty_dtr" at max80.sv(77) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
Warning (10862): input port "flash_miso" at max80.sv(83) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
Warning (10862): bidir port "spi_clk" at max80.sv(86) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
Warning (10862): bidir port "spi_miso" at max80.sv(87) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
Warning (10862): bidir port "spi_mosi" at max80.sv(88) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 88
Warning (10862): bidir port "spi_cs_esp_n" at max80.sv(89) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 89
Warning (10862): bidir port "spi_cs_flash_n" at max80.sv(90) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 90
Warning (10862): bidir port "esp_io0" at max80.sv(93) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
Warning (10862): bidir port "esp_int" at max80.sv(94) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 94
Warning (10862): bidir port "i2c_scl" at max80.sv(97) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
Warning (10862): bidir port "i2c_sda" at max80.sv(98) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
Warning (10862): input port "rtc_32khz" at max80.sv(99) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
Warning (10862): input port "rtc_int_n" at max80.sv(100) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 100
Warning (10862): bidir port "hdmi_scl" at max80.sv(111) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
Warning (10863): bidir port "hdmi_sda" at max80.sv(112) has no fan-in File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
Warning (10862): bidir port "hdmi_sda" at max80.sv(112) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
Warning (10862): bidir port "hdmi_hpd" at max80.sv(114) has no fan-out File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 114
Info (12128): Elaborating entity "pll" for hierarchy "pll:pll" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 140
Info (12128): Elaborating entity "altpll" for hierarchy "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
Info (12130): Elaborated megafunction instantiation "pll:pll|altpll:altpll_component" File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
Info (12133): Instantiated megafunction "pll:pll|altpll:altpll_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 127
    Info (12134): Parameter "bandwidth_type" = "HIGH"
    Info (12134): Parameter "clk0_divide_by" = "1"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "2"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "1"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "2"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "clk2_divide_by" = "4"
    Info (12134): Parameter "clk2_duty_cycle" = "50"
    Info (12134): Parameter "clk2_multiply_by" = "3"
    Info (12134): Parameter "clk2_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20833"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_USED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_USED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_USED"
    Info (12134): Parameter "port_phasedone" = "PORT_USED"
    Info (12134): Parameter "port_phasestep" = "PORT_USED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_USED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_USED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_USED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "self_reset_on_loss_lock" = "ON"
    Info (12134): Parameter "width_clock" = "5"
    Info (12134): Parameter "width_phasecounterselect" = "3"
Info (12021): Found 8 design units, including 8 entities, in source file db/pll_altpll.v
    Info (12023): Found entity 1: pll_altpll_dyn_phase_le File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 35
    Info (12023): Found entity 2: pll_altpll_dyn_phase_le1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 78
    Info (12023): Found entity 3: pll_altpll_dyn_phase_le12 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 121
    Info (12023): Found entity 4: pll_cmpr File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 171
    Info (12023): Found entity 5: pll_cntr File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 205
    Info (12023): Found entity 6: pll_cmpr1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 309
    Info (12023): Found entity 7: pll_cntr1 File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 343
    Info (12023): Found entity 8: pll_altpll File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 446
Info (12128): Elaborating entity "pll_altpll" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated" File: /opt/altera/20.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
Info (12128): Elaborating entity "pll_altpll_dyn_phase_le" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 509
Warning (10862): input port "datad" at pll_altpll.v(46) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 46
Info (12128): Elaborating entity "pll_altpll_dyn_phase_le1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 516
Warning (10862): input port "datad" at pll_altpll.v(89) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 89
Info (12128): Elaborating entity "pll_altpll_dyn_phase_le12" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 523
Warning (10862): input port "datad" at pll_altpll.v(132) has no fan-out File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 132
Info (12128): Elaborating entity "pll_cntr" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 567
Info (12128): Elaborating entity "pll_cmpr" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|pll_cmpr:cmpr12" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 273
Info (12128): Elaborating entity "pll_cntr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 573
Info (12128): Elaborating entity "pll_cmpr1" for hierarchy "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|pll_cmpr1:cmpr14" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 421
Info (12128): Elaborating entity "tmdsenc" for hierarchy "tmdsenc:hdmitmds[0].enc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 180
Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(92): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 92
Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(134): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 134
Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(135): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 135
Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(140): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 140
Warning (10040): Verilog HDL or VHDL arithmetic warning at tmdsenc.sv(145): loss of carry in addition or borrow in subtraction File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 145
Info (12128): Elaborating entity "transpose" for hierarchy "transpose:hdmitranspose" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 197
Warning (10269): Verilog HDL conditional expression warning at transpose.sv(64): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 64
Warning (10269): Verilog HDL conditional expression warning at transpose.sv(65): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 65
Warning (10269): Verilog HDL conditional expression warning at transpose.sv(67): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 67
Info (12128): Elaborating entity "condreg" for hierarchy "transpose:hdmitranspose|condreg:dreg" File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 53
Warning (10269): Verilog HDL conditional expression warning at transpose.sv(14): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 14
Warning (10269): Verilog HDL conditional expression warning at transpose.sv(15): expression is wider than one bit File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 15
Warning (10862): input port "clk" at transpose.sv(8) has no fan-out File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 8
Info (12128): Elaborating entity "hdmitx" for hierarchy "hdmitx:hdmitx" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 206
Info (12128): Elaborating entity "altlvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
Info (12130): Elaborated megafunction instantiation "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
Info (12133): Instantiated megafunction "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component" with the following parameter: File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 74
    Info (12134): Parameter "center_align_msb" = "UNUSED"
    Info (12134): Parameter "common_rx_tx_pll" = "OFF"
    Info (12134): Parameter "coreclock_divide_by" = "2"
    Info (12134): Parameter "data_rate" = "360.0 Mbps"
    Info (12134): Parameter "deserialization_factor" = "10"
    Info (12134): Parameter "differential_drive" = "0"
    Info (12134): Parameter "enable_clock_pin_mode" = "UNUSED"
    Info (12134): Parameter "implement_in_les" = "ON"
    Info (12134): Parameter "inclock_boost" = "0"
    Info (12134): Parameter "inclock_data_alignment" = "EDGE_ALIGNED"
    Info (12134): Parameter "inclock_period" = "27778"
    Info (12134): Parameter "inclock_phase_shift" = "0"
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=hdmitx"
    Info (12134): Parameter "lpm_type" = "altlvds_tx"
    Info (12134): Parameter "multi_clock" = "OFF"
    Info (12134): Parameter "number_of_channels" = "3"
    Info (12134): Parameter "outclock_alignment" = "EDGE_ALIGNED"
    Info (12134): Parameter "outclock_divide_by" = "10"
    Info (12134): Parameter "outclock_duty_cycle" = "50"
    Info (12134): Parameter "outclock_multiply_by" = "2"
    Info (12134): Parameter "outclock_phase_shift" = "0"
    Info (12134): Parameter "outclock_resource" = "AUTO"
    Info (12134): Parameter "output_data_rate" = "360"
    Info (12134): Parameter "pll_compensation_mode" = "AUTO"
    Info (12134): Parameter "pll_self_reset_on_loss_lock" = "ON"
    Info (12134): Parameter "preemphasis_setting" = "0"
    Info (12134): Parameter "refclk_frequency" = "UNUSED"
    Info (12134): Parameter "registered_input" = "TX_CORECLK"
    Info (12134): Parameter "use_external_pll" = "OFF"
    Info (12134): Parameter "use_no_phase_shift" = "ON"
    Info (12134): Parameter "vod_setting" = "0"
    Info (12134): Parameter "clk_src_is_pll" = "off"
Info (12021): Found 8 design units, including 8 entities, in source file db/hdmitx_lvds_tx.v
    Info (12023): Found entity 1: hdmitx_ddio_out File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 35
    Info (12023): Found entity 2: hdmitx_ddio_out1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 174
    Info (12023): Found entity 3: hdmitx_cmpr File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 241
    Info (12023): Found entity 4: hdmitx_cmpr1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 287
    Info (12023): Found entity 5: hdmitx_cntr File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 321
    Info (12023): Found entity 6: hdmitx_shift_reg File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 477
    Info (12023): Found entity 7: hdmitx_shift_reg1 File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 527
    Info (12023): Found entity 8: hdmitx_lvds_tx File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 574
Info (12128): Elaborating entity "hdmitx_lvds_tx" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated" File: /opt/altera/20.1/quartus/libraries/megafunctions/altlvds_tx.tdf Line: 263
Warning (10036): Verilog HDL or VHDL warning at hdmitx_lvds_tx.v(604): object "dffe19a" assigned a value but never read File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 604
Info (12128): Elaborating entity "hdmitx_ddio_out" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 649
Info (12128): Elaborating entity "hdmitx_ddio_out1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 656
Info (12128): Elaborating entity "hdmitx_cmpr" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cmpr:cmpr10" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 773
Info (12128): Elaborating entity "hdmitx_cntr" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 789
Info (12128): Elaborating entity "hdmitx_cmpr1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|hdmitx_cmpr1:cmpr29" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 448
Info (12128): Elaborating entity "hdmitx_shift_reg" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 803
Info (12128): Elaborating entity "hdmitx_shift_reg1" for hierarchy "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 819
Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[9]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[9]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 89
Warning (14130): Reduced register "tmdsenc:hdmitmds[2].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 89
Warning (14130): Reduced register "tmdsenc:hdmitmds[1].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[0]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 89
Warning (14130): Reduced register "tmdsenc:hdmitmds[0].enc|creg[1]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 482
Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|internal_phasestep" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 482
Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 537
Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|phasedone_state" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 537
Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 484
Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_internal_phasestep_reg" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 484
Warning (14131): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_lock_sync" with stuck data_in port to stuck value VCC -- power-up level has changed File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 485
Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 406
Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[2]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 406
Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 392
Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[0]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 392
Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[1]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 399
Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep|counter_reg_bit[1]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 399
Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[1]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 258
Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[1]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 258
Warning (14110): No clock transition on "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0]" register due to stuck clock or clock enable File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 251
Warning (14130): Reduced register "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter|counter_reg_bit[0]" with stuck clock port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 251
Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[8]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[8]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
Warning (14130): Reduced register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[7]" with stuck data_in port to stuck value GND File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
Info (13005): Duplicate registers merged to single register
    Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[7]" merged to single register "dummydata[0]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[0]" merged to single register "dummydata[1]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[1]" merged to single register "dummydata[2]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[2]" merged to single register "dummydata[3]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[3]" merged to single register "dummydata[4]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[4]" merged to single register "dummydata[5]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[5]" merged to single register "dummydata[6]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[6]" merged to single register "dummydata[7]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[0].enc|dreg[7]" merged to single register "dummydata[8]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[0]" merged to single register "dummydata[9]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[1]" merged to single register "dummydata[10]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[2]" merged to single register "dummydata[11]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[3]" merged to single register "dummydata[12]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[4]" merged to single register "dummydata[13]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[5]" merged to single register "dummydata[14]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[6]" merged to single register "dummydata[15]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|dreg[7]" merged to single register "dummydata[16]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[0]" merged to single register "dummydata[17]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[1]" merged to single register "dummydata[18]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[2]" merged to single register "dummydata[19]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[3]" merged to single register "dummydata[20]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[4]" merged to single register "dummydata[21]" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[5]" merged to single register "dummydata[22]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13360): Duplicate register "tmdsenc:hdmitmds[2].enc|dreg[6]" merged to single register "dummydata[23]", power-up level changed File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
    Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe1a" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 615
    Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[7]" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
Info (13005): Duplicate registers merged to single register
    Info (13350): Duplicate register "tmdsenc:hdmitmds[1].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 88
    Info (13350): Duplicate register "tmdsenc:hdmitmds[2].enc|denreg" merged to single register "tmdsenc:hdmitmds[0].enc|denreg" File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 88
    Info (13350): Duplicate register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[5]" merged to single register "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]" File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 512
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning (13039): The following bidirectional pins have no drivers
    Warning (13040): bidirectional pin "abc_d[0]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Warning (13040): bidirectional pin "abc_d[1]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Warning (13040): bidirectional pin "abc_d[2]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Warning (13040): bidirectional pin "abc_d[3]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Warning (13040): bidirectional pin "abc_d[4]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Warning (13040): bidirectional pin "abc_d[5]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Warning (13040): bidirectional pin "abc_d[6]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Warning (13040): bidirectional pin "abc_d[7]" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Warning (13040): bidirectional pin "hdmi_sda" has no driver File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
Warning (13032): The following tri-state nodes are fed by constants
    Warning (13033): The pin "sr_dq[0]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[1]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[2]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[3]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[4]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[5]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[6]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[7]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[8]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[9]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[10]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[11]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[12]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[13]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[14]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Warning (13033): The pin "sr_dq[15]" is fed by GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
Info (13000): Registers with preset signals will power-up high File: /home/hpa/abc80/max80/blinktest/tmdsenc.sv Line: 124
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "abc_d_oe" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 19
    Warning (13410): Pin "abc_master" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 38
    Warning (13410): Pin "abc_a_oe" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 39
    Warning (13410): Pin "abc_d_ce_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 41
    Warning (13410): Pin "sr_cke" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 57
    Warning (13410): Pin "sr_ba[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
    Warning (13410): Pin "sr_ba[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 58
    Warning (13410): Pin "sr_a[0]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[1]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[2]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[3]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[4]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[5]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[6]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[7]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[8]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[9]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[10]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[11]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_a[12]" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 59
    Warning (13410): Pin "sr_dqm[0]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
    Warning (13410): Pin "sr_dqm[1]" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 61
    Warning (13410): Pin "sr_cs_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 62
    Warning (13410): Pin "sr_we_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 63
    Warning (13410): Pin "sr_cas_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 64
    Warning (13410): Pin "sr_ras_n" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 65
    Warning (13410): Pin "sd_clk" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 68
    Warning (13410): Pin "sd_cmd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 69
    Warning (13410): Pin "tty_rxd" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 74
    Warning (13410): Pin "tty_cts" is stuck at VCC File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 76
    Warning (13410): Pin "flash_cs_n" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 80
    Warning (13410): Pin "flash_clk" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 81
    Warning (13410): Pin "flash_mosi" is stuck at GND File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 82
Info (286030): Timing-Driven Synthesis is running
Info (17016): Found the following redundant logic cells in design
    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|wire_le_comb8_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 59
    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|wire_le_comb9_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 102
    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5|wire_le_comb10_combout" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 145
    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_0" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 554
    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_1" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 558
    Info (17048): Logic cell "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2" File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 562
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 20 node(s), including 4 DDIO, 2 PLL, 0 transceiver and 6 LCELL
Warning (21074): Design contains 39 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "abc_clk" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
    Warning (15610): No output dependent on input pin "abc_a[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[2]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[3]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[4]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[5]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[6]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[7]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[8]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[9]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[10]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[11]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[12]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[13]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[14]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_a[15]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Warning (15610): No output dependent on input pin "abc_rst_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
    Warning (15610): No output dependent on input pin "abc_cs_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
    Warning (15610): No output dependent on input pin "abc_out_n[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Warning (15610): No output dependent on input pin "abc_out_n[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Warning (15610): No output dependent on input pin "abc_out_n[2]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Warning (15610): No output dependent on input pin "abc_out_n[3]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Warning (15610): No output dependent on input pin "abc_out_n[4]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Warning (15610): No output dependent on input pin "abc_inp_n[0]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
    Warning (15610): No output dependent on input pin "abc_inp_n[1]" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
    Warning (15610): No output dependent on input pin "abc_xmemfl_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
    Warning (15610): No output dependent on input pin "abc_xmemw800_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
    Warning (15610): No output dependent on input pin "abc_xmemw80_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
    Warning (15610): No output dependent on input pin "abc_xinpstb_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 27
    Warning (15610): No output dependent on input pin "abc_xoutpstb_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 28
    Warning (15610): No output dependent on input pin "exth_hc" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
    Warning (15610): No output dependent on input pin "exth_hh" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
    Warning (15610): No output dependent on input pin "tty_txd" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 73
    Warning (15610): No output dependent on input pin "tty_rts" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
    Warning (15610): No output dependent on input pin "tty_dtr" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
    Warning (15610): No output dependent on input pin "flash_miso" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
    Warning (15610): No output dependent on input pin "rtc_32khz" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
    Warning (15610): No output dependent on input pin "rtc_int_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 100
Info (21057): Implemented 485 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 40 input pins
    Info (21059): Implemented 47 output pins
    Info (21060): Implemented 52 bidirectional pins
    Info (21061): Implemented 340 logic cells
    Info (21065): Implemented 2 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 217 warnings
    Info: Peak virtual memory: 679 megabytes
    Info: Processing ended: Fri Aug  6 20:12:40 2021
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:15


+----------------------------------------------------------------------------------+
; Fitter Summary                                                                   ;
+------------------------------------+---------------------------------------------+
; Fitter Status                      ; Successful - Fri Aug  6 20:12:47 2021       ;
; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name                      ; max80                                       ;
; Top-level Entity Name              ; max80                                       ;
; Family                             ; Cyclone IV E                                ;
; Device                             ; EP4CE15F17C8                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 327 / 15,408 ( 2 % )                        ;
;     Total combinational functions  ; 278 / 15,408 ( 2 % )                        ;
;     Dedicated logic registers      ; 218 / 15,408 ( 1 % )                        ;
; Total registers                    ; 229                                         ;
; Total pins                         ; 143 / 166 ( 86 % )                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 0 / 516,096 ( 0 % )                         ;
; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
; Total PLLs                         ; 2 / 2 ( 100 % )                             ;
+------------------------------------+---------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                    ;
+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                             ; Setting                               ; Default Value                         ;
+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                             ; EP4CE15F17C8                          ;                                       ;
; Minimum Core Junction Temperature                                  ; 0                                     ;                                       ;
; Maximum Core Junction Temperature                                  ; 85                                    ;                                       ;
; Fit Attempts to Skip                                               ; 0                                     ; 0.0                                   ;
; Device Migration List                                              ; EP4CE15F17C8,EP4CE6F17C8,EP4CE10F17C8 ;                                       ;
; Device I/O Standard                                                ; 3.3-V LVTTL                           ;                                       ;
; Optimize IOC Register Placement for Timing                         ; Pack All IO Registers                 ; Normal                                ;
; Reserve all unused pins                                            ; As output driving ground              ; As input tri-stated with weak pull-up ;
; Use smart compilation                                              ; Off                                   ; Off                                   ;
; Enable parallel Assembler and Timing Analyzer during compilation   ; On                                    ; On                                    ;
; Enable compact report table                                        ; Off                                   ; Off                                   ;
; Auto Merge PLLs                                                    ; On                                    ; On                                    ;
; Router Timing Optimization Level                                   ; Normal                                ; Normal                                ;
; Perform Clocking Topology Analysis During Routing                  ; Off                                   ; Off                                   ;
; Placement Effort Multiplier                                        ; 1.0                                   ; 1.0                                   ;
; Router Effort Multiplier                                           ; 1.0                                   ; 1.0                                   ;
; Optimize Hold Timing                                               ; All Paths                             ; All Paths                             ;
; Optimize Multi-Corner Timing                                       ; On                                    ; On                                    ;
; Power Optimization During Fitting                                  ; Normal compilation                    ; Normal compilation                    ;
; SSN Optimization                                                   ; Off                                   ; Off                                   ;
; Optimize Timing                                                    ; Normal compilation                    ; Normal compilation                    ;
; Optimize Timing for ECOs                                           ; Off                                   ; Off                                   ;
; Regenerate Full Fit Report During ECO Compiles                     ; Off                                   ; Off                                   ;
; Limit to One Fitting Attempt                                       ; Off                                   ; Off                                   ;
; Final Placement Optimizations                                      ; Automatically                         ; Automatically                         ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                         ; Automatically                         ;
; Fitter Initial Placement Seed                                      ; 1                                     ; 1                                     ;
; Periphery to Core Placement and Routing Optimization               ; Off                                   ; Off                                   ;
; PCI I/O                                                            ; Off                                   ; Off                                   ;
; Weak Pull-Up Resistor                                              ; Off                                   ; Off                                   ;
; Enable Bus-Hold Circuitry                                          ; Off                                   ; Off                                   ;
; Auto Packed Registers                                              ; Auto                                  ; Auto                                  ;
; Auto Delay Chains                                                  ; On                                    ; On                                    ;
; Auto Delay Chains for High Fanout Input Pins                       ; Off                                   ; Off                                   ;
; Allow Single-ended Buffer for Differential-XSTL Input              ; Off                                   ; Off                                   ;
; Treat Bidirectional Pin as Output Pin                              ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                                   ; Off                                   ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                                   ; Off                                   ;
; Perform Register Duplication for Performance                       ; Off                                   ; Off                                   ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                                   ; Off                                   ;
; Perform Register Retiming for Performance                          ; Off                                   ; Off                                   ;
; Perform Asynchronous Signal Pipelining                             ; Off                                   ; Off                                   ;
; Fitter Effort                                                      ; Auto Fit                              ; Auto Fit                              ;
; Physical Synthesis Effort Level                                    ; Normal                                ; Normal                                ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                                  ; Auto                                  ;
; Auto Register Duplication                                          ; Auto                                  ; Auto                                  ;
; Auto Global Clock                                                  ; On                                    ; On                                    ;
; Auto Global Register Control Signals                               ; On                                    ; On                                    ;
; Synchronizer Identification                                        ; Auto                                  ; Auto                                  ;
; Enable Beneficial Skew Optimization                                ; On                                    ; On                                    ;
; Optimize Design for Metastability                                  ; On                                    ; On                                    ;
; Force Fitter to Avoid Periphery Placement Warnings                 ; Off                                   ; Off                                   ;
; Enable input tri-state on active configuration pins in user mode   ; Off                                   ; Off                                   ;
+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 16          ;
; Maximum allowed            ; 8           ;
;                            ;             ;
; Average used               ; 1.03        ;
; Maximum used               ; 8           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.4%      ;
;     Processors 3-8         ;   0.4%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                              ;
+-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+
; Node        ; Action          ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node         ; Destination Port ; Destination Port Name ;
+-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+
; led_ctr[26] ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; led_ctr[26]~_Duplicate_1 ; Q                ;                       ;
; led_ctr[26] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; led[1]~output            ; I                ;                       ;
; led_ctr[27] ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; led_ctr[27]~_Duplicate_1 ; Q                ;                       ;
; led_ctr[27] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; led[2]~output            ; I                ;                       ;
; led_ctr[28] ; Duplicated      ; Register Packing ; Timing optimization ; Q         ;                ; led_ctr[28]~_Duplicate_1 ; Q                ;                       ;
; led_ctr[28] ; Packed Register ; Register Packing ; Timing optimization ; Q         ;                ; led[3]~output            ; I                ;                       ;
+-------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------+------------------+-----------------------+


+-------------------------------------------------------------------------------------------------------+
; Ignored Assignments                                                                                   ;
+-----------------------+----------------+--------------+--------------+---------------+----------------+
; Name                  ; Ignored Entity ; Ignored From ; Ignored To   ; Ignored Value ; Ignored Source ;
+-----------------------+----------------+--------------+--------------+---------------+----------------+
; I/O Standard          ; max80          ;              ; hdmi_d       ; LVDS          ; QSF Assignment ;
; Weak Pull-Up Resistor ; max80          ;              ; hdmi_clk(n)  ; OFF           ; QSF Assignment ;
; Weak Pull-Up Resistor ; max80          ;              ; hdmi_d       ; OFF           ; QSF Assignment ;
; Weak Pull-Up Resistor ; max80          ;              ; hdmi_d[0](n) ; OFF           ; QSF Assignment ;
; Weak Pull-Up Resistor ; max80          ;              ; hdmi_d[1](n) ; OFF           ; QSF Assignment ;
; Weak Pull-Up Resistor ; max80          ;              ; hdmi_d[2](n) ; OFF           ; QSF Assignment ;
+-----------------------+----------------+--------------+--------------+---------------+----------------+


+--------------------------------------------------------------------------------------------------+
; Incremental Compilation Preservation Summary                                                     ;
+---------------------+--------------------+----------------------------+--------------------------+
; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+--------------------+----------------------------+--------------------------+
; Placement (by node) ;                    ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 842 ) ; 0.00 % ( 0 / 842 )         ; 0.00 % ( 0 / 842 )       ;
;     -- Achieved     ; 0.00 % ( 0 / 842 ) ; 0.00 % ( 0 / 842 )         ; 0.00 % ( 0 / 842 )       ;
;                     ;                    ;                            ;                          ;
; Routing (by net)    ;                    ;                            ;                          ;
;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+---------------------+--------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                                             ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                                                     ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top                            ; 0.00 % ( 0 / 813 )    ; N/A                     ; Source File       ; N/A                 ;       ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 29 )     ; N/A                     ; Source File       ; N/A                 ;       ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 327 / 15,408 ( 2 % ) ;
;     -- Combinational with no register       ; 109                  ;
;     -- Register only                        ; 49                   ;
;     -- Combinational with a register        ; 169                  ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 105                  ;
;     -- 3 input functions                    ; 65                   ;
;     -- <=2 input functions                  ; 108                  ;
;     -- Register only                        ; 49                   ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 222                  ;
;     -- arithmetic mode                      ; 56                   ;
;                                             ;                      ;
; Total registers*                            ; 229 / 16,166 ( 1 % ) ;
;     -- Dedicated logic registers            ; 218 / 15,408 ( 1 % ) ;
;     -- I/O registers                        ; 11 / 758 ( 1 % )     ;
;                                             ;                      ;
; Total LABs:  partially or completely used   ; 29 / 963 ( 3 % )     ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 143 / 166 ( 86 % )   ;
;     -- Clock pins                           ; 4 / 3 ( 133 % )      ;
;     -- Dedicated input pins                 ; 6 / 17 ( 35 % )      ;
;                                             ;                      ;
; M9Ks                                        ; 0 / 56 ( 0 % )       ;
; Total block memory bits                     ; 0 / 516,096 ( 0 % )  ;
; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )  ;
; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ;
; PLLs                                        ; 2 / 2 ( 100 % )      ;
; Global signals                              ; 6                    ;
;     -- Global clocks                        ; 6 / 20 ( 30 % )      ;
; JTAGs                                       ; 0 / 1 ( 0 % )        ;
; CRC blocks                                  ; 0 / 1 ( 0 % )        ;
; ASMI blocks                                 ; 0 / 1 ( 0 % )        ;
; Oscillator blocks                           ; 0 / 1 ( 0 % )        ;
; Impedance control blocks                    ; 0 / 4 ( 0 % )        ;
; Average interconnect usage (total/H/V)      ; 0.3% / 0.3% / 0.4%   ;
; Peak interconnect usage (total/H/V)         ; 2.8% / 3.0% / 2.5%   ;
; Maximum fan-out                             ; 90                   ;
; Highest non-global fan-out                  ; 42                   ;
; Total fan-out                               ; 1657                 ;
; Average fan-out                             ; 1.87                 ;
+---------------------------------------------+----------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------+
; Fitter Partition Statistics                                                                        ;
+---------------------------------------------+---------------------+--------------------------------+
; Statistic                                   ; Top                 ; hard_block:auto_generated_inst ;
+---------------------------------------------+---------------------+--------------------------------+
; Difficulty Clustering Region                ; Low                 ; Low                            ;
;                                             ;                     ;                                ;
; Total logic elements                        ; 321 / 15408 ( 2 % ) ; 6 / 15408 ( < 1 % )            ;
;     -- Combinational with no register       ; 103                 ; 6                              ;
;     -- Register only                        ; 49                  ; 0                              ;
;     -- Combinational with a register        ; 169                 ; 0                              ;
;                                             ;                     ;                                ;
; Logic element usage by number of LUT inputs ;                     ;                                ;
;     -- 4 input functions                    ; 102                 ; 3                              ;
;     -- 3 input functions                    ; 65                  ; 0                              ;
;     -- <=2 input functions                  ; 105                 ; 3                              ;
;     -- Register only                        ; 49                  ; 0                              ;
;                                             ;                     ;                                ;
; Logic elements by mode                      ;                     ;                                ;
;     -- normal mode                          ; 216                 ; 6                              ;
;     -- arithmetic mode                      ; 56                  ; 0                              ;
;                                             ;                     ;                                ;
; Total registers                             ; 221                 ; 8                              ;
;     -- Dedicated logic registers            ; 218 / 15408 ( 1 % ) ; 0 / 15408 ( 0 % )              ;
;     -- I/O registers                        ; 6                   ; 16                             ;
;                                             ;                     ;                                ;
; Total LABs:  partially or completely used   ; 29 / 963 ( 3 % )    ; 1 / 963 ( < 1 % )              ;
;                                             ;                     ;                                ;
; Virtual pins                                ; 0                   ; 0                              ;
; I/O pins                                    ; 135                 ; 8                              ;
; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ; 0 / 112 ( 0 % )                ;
; Total memory bits                           ; 0                   ; 0                              ;
; Total RAM block bits                        ; 0                   ; 0                              ;
; PLL                                         ; 0 / 2 ( 0 % )       ; 2 / 2 ( 100 % )                ;
; Clock control block                         ; 1 / 24 ( 4 % )      ; 5 / 24 ( 20 % )                ;
; Double Data Rate I/O output circuitry       ; 3 / 336 ( < 1 % )   ; 4 / 336 ( 1 % )                ;
;                                             ;                     ;                                ;
; Connections                                 ;                     ;                                ;
;     -- Input Connections                    ; 287                 ; 12                             ;
;     -- Registered Input Connections         ; 234                 ; 0                              ;
;     -- Output Connections                   ; 64                  ; 235                            ;
;     -- Registered Output Connections        ; 8                   ; 0                              ;
;                                             ;                     ;                                ;
; Internal Connections                        ;                     ;                                ;
;     -- Total Connections                    ; 1621                ; 291                            ;
;     -- Registered Connections               ; 779                 ; 0                              ;
;                                             ;                     ;                                ;
; External Connections                        ;                     ;                                ;
;     -- Top                                  ; 104                 ; 247                            ;
;     -- hard_block:auto_generated_inst       ; 247                 ; 0                              ;
;                                             ;                     ;                                ;
; Partition Interface                         ;                     ;                                ;
;     -- Input Ports                          ; 40                  ; 12                             ;
;     -- Output Ports                         ; 47                  ; 10                             ;
;     -- Bidir Ports                          ; 52                  ; 0                              ;
;                                             ;                     ;                                ;
; Registered Ports                            ;                     ;                                ;
;     -- Registered Input Ports               ; 0                   ; 0                              ;
;     -- Registered Output Ports              ; 0                   ; 0                              ;
;                                             ;                     ;                                ;
; Port Connectivity                           ;                     ;                                ;
;     -- Input Ports driven by GND            ; 0                   ; 3                              ;
;     -- Output Ports driven by GND           ; 0                   ; 0                              ;
;     -- Input Ports driven by VCC            ; 0                   ; 0                              ;
;     -- Output Ports driven by VCC           ; 0                   ; 0                              ;
;     -- Input Ports with no Source           ; 0                   ; 0                              ;
;     -- Output Ports with no Source          ; 0                   ; 0                              ;
;     -- Input Ports with no Fanout           ; 0                   ; 2                              ;
;     -- Output Ports with no Fanout          ; 0                   ; 0                              ;
+---------------------------------------------+---------------------+--------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                                                      ;
+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
; Name           ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
; abc_a[0]       ; A8    ; 8        ; 19           ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[10]      ; L4    ; 2        ; 0            ; 4            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[11]      ; K1    ; 2        ; 0            ; 10           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[12]      ; L1    ; 2        ; 0            ; 9            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[13]      ; M1    ; 2        ; 0            ; 14           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[14]      ; N2    ; 2        ; 0            ; 5            ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[15]      ; N1    ; 2        ; 0            ; 5            ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[1]       ; B8    ; 8        ; 19           ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[2]       ; A9    ; 7        ; 19           ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[3]       ; D1    ; 1        ; 0            ; 24           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[4]       ; G5    ; 1        ; 0            ; 22           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[5]       ; F3    ; 1        ; 0            ; 25           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[6]       ; E1    ; 1        ; 0            ; 14           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[7]       ; F1    ; 1        ; 0            ; 22           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[8]       ; G1    ; 1        ; 0            ; 21           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_a[9]       ; J1    ; 2        ; 0            ; 13           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_clk        ; T8    ; 3        ; 21           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_cs_n       ; F2    ; 1        ; 0            ; 22           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_inp_n[0]   ; L2    ; 2        ; 0            ; 10           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_inp_n[1]   ; M2    ; 2        ; 0            ; 14           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_out_n[0]   ; G2    ; 1        ; 0            ; 21           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_out_n[1]   ; J2    ; 2        ; 0            ; 13           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_out_n[2]   ; K5    ; 2        ; 0            ; 5            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_out_n[3]   ; L3    ; 2        ; 0            ; 11           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_out_n[4]   ; K2    ; 2        ; 0            ; 6            ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_rst_n      ; P2    ; 2        ; 0            ; 3            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_xinpstb_n  ; T12   ; 4        ; 28           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_xmemfl_n   ; N3    ; 3        ; 1            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_xmemw800_n ; P1    ; 2        ; 0            ; 3            ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_xmemw80_n  ; R1    ; 2        ; 0            ; 4            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; abc_xoutpstb_n ; L10   ; 4        ; 30           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; clock_48       ; M15   ; 5        ; 41           ; 15           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 2.5 V        ; --                        ; User                 ; no        ;
; exth_hc        ; T9    ; 4        ; 21           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; exth_hh        ; R8    ; 3        ; 21           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; flash_miso     ; H2    ; 1        ; 0            ; 20           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; On           ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; rtc_32khz      ; E15   ; 6        ; 41           ; 15           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; rtc_int_n      ; B16   ; 6        ; 41           ; 19           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; tty_dtr        ; P14   ; 4        ; 37           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; tty_rts        ; D16   ; 6        ; 41           ; 24           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
; tty_txd        ; E16   ; 6        ; 41           ; 15           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ; no        ;
+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
; abc_a_oe     ; C2    ; 1        ; 0            ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_d_ce_n   ; R5    ; 3        ; 14           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_d_oe     ; T5    ; 3        ; 14           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_int800_x ; A2    ; 8        ; 3            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_int80_x  ; B3    ; 8        ; 1            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_master   ; T10   ; 4        ; 26           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_nmi_x    ; A3    ; 8        ; 3            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_rdy_x    ; B4    ; 8        ; 3            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_resin_x  ; R6    ; 3        ; 16           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; abc_xm_x     ; B1    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; flash_clk    ; H1    ; 1        ; 0            ; 20           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; flash_cs_n   ; D2    ; 1        ; 0            ; 24           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; flash_mosi   ; C1    ; 1        ; 0            ; 25           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; On           ; 3.3-V LVTTL  ; Default          ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; hdmi_clk     ; J15   ; 5        ; 41           ; 13           ; 7            ; yes             ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
; hdmi_clk(n)  ; J16   ; 5        ; 41           ; 13           ; 14           ; no              ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; Fitter               ; -                    ; -                   ;
; hdmi_d[0]    ; K15   ; 5        ; 41           ; 13           ; 21           ; yes             ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
; hdmi_d[0](n) ; K16   ; 5        ; 41           ; 12           ; 0            ; no              ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; Fitter               ; -                    ; -                   ;
; hdmi_d[1]    ; N15   ; 5        ; 41           ; 5            ; 0            ; yes             ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
; hdmi_d[1](n) ; N16   ; 5        ; 41           ; 5            ; 7            ; no              ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; Fitter               ; -                    ; -                   ;
; hdmi_d[2]    ; R16   ; 5        ; 41           ; 3            ; 7            ; yes             ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; User                 ; -                    ; -                   ;
; hdmi_d[2](n) ; P16   ; 5        ; 41           ; 3            ; 14           ; no              ; no                     ; no            ; no        ; no              ; no         ; no            ; no       ; Off          ; LVDS         ; Maximum Current  ; Off         ; --                        ; 1                          ; 1                           ; Fitter               ; -                    ; -                   ;
; led[1]       ; T13   ; 4        ; 30           ; 0            ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; led[2]       ; R14   ; 4        ; 37           ; 0            ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; led[3]       ; T14   ; 4        ; 35           ; 0            ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sd_clk       ; G15   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sd_cmd       ; G16   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[0]      ; A14   ; 7        ; 35           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[10]     ; C14   ; 7        ; 39           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[11]     ; C8    ; 8        ; 14           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[12]     ; B6    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[1]      ; B14   ; 7        ; 35           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[2]      ; D14   ; 7        ; 39           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[3]      ; A15   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[4]      ; C9    ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[5]      ; D9    ; 7        ; 23           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[6]      ; E8    ; 8        ; 14           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[7]      ; A7    ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[8]      ; B7    ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_a[9]      ; A6    ; 8        ; 9            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_ba[0]     ; A13   ; 7        ; 28           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_ba[1]     ; B13   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_cas_n     ; E9    ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_cke       ; F8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_clk       ; D3    ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_cs_n      ; D12   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_dqm[0]    ; E10   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_dqm[1]    ; D8    ; 8        ; 14           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_ras_n     ; B12   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; sr_we_n      ; F9    ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; tty_cts      ; D15   ; 6        ; 41           ; 24           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
; tty_rxd      ; F13   ; 6        ; 41           ; 18           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
; Name           ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Location assigned by ; Output Enable Source ; Output Enable Group ;
+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
; abc_d[0]       ; P3    ; 3        ; 3            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; abc_d[1]       ; M6    ; 3        ; 7            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; abc_d[2]       ; N5    ; 3        ; 7            ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; abc_d[3]       ; T2    ; 3        ; 5            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; abc_d[4]       ; R3    ; 3        ; 3            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; abc_d[5]       ; T3    ; 3        ; 3            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; abc_d[6]       ; R4    ; 3        ; 5            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; abc_d[7]       ; T4    ; 3        ; 7            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; esp_int        ; P8    ; 3        ; 21           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; esp_io0        ; L8    ; 3        ; 19           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; exth_ha        ; N12   ; 4        ; 30           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; exth_hb        ; N9    ; 4        ; 23           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; exth_hd        ; R11   ; 4        ; 26           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; exth_he        ; R12   ; 4        ; 26           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; exth_hf        ; T11   ; 4        ; 26           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; exth_hg        ; N11   ; 4        ; 35           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; gpio[0]        ; L7    ; 3        ; 16           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; gpio[1]        ; P9    ; 4        ; 30           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; gpio[2]        ; T6    ; 3        ; 16           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; gpio[3]        ; R10   ; 4        ; 26           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; gpio[4]        ; T7    ; 3        ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; gpio[5]        ; R7    ; 3        ; 16           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; hdmi_hpd       ; T15   ; 4        ; 35           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; hdmi_scl       ; M11   ; 4        ; 39           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; hdmi_sda       ; R13   ; 4        ; 30           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; i2c_scl        ; C16   ; 6        ; 41           ; 27           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; i2c_sda        ; C15   ; 6        ; 41           ; 27           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sd_dat[0]      ; F15   ; 6        ; 41           ; 19           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sd_dat[1]      ; M10   ; 4        ; 35           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sd_dat[2]      ; F14   ; 6        ; 41           ; 23           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sd_dat[3]      ; F16   ; 6        ; 41           ; 19           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; spi_clk        ; P6    ; 3        ; 14           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; spi_cs_esp_n   ; N8    ; 3        ; 19           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; spi_cs_flash_n ; N6    ; 3        ; 7            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; spi_miso       ; M7    ; 3        ; 14           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; spi_mosi       ; M8    ; 3        ; 19           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[0]       ; A12   ; 7        ; 32           ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[10]      ; B5    ; 8        ; 5            ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[11]      ; A4    ; 8        ; 3            ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[12]      ; E6    ; 8        ; 7            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[13]      ; D6    ; 8        ; 5            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[14]      ; C6    ; 8        ; 11           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[15]      ; D5    ; 8        ; 3            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[1]       ; E11   ; 7        ; 32           ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[2]       ; D11   ; 7        ; 39           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[3]       ; C11   ; 7        ; 37           ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[4]       ; B11   ; 7        ; 30           ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[5]       ; A11   ; 7        ; 30           ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[6]       ; B10   ; 7        ; 26           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[7]       ; A10   ; 7        ; 26           ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[8]       ; A5    ; 8        ; 5            ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
; sr_dq[9]       ; E7    ; 8        ; 7            ; 29           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; no                         ; User                 ; 0 pF                 ; -                   ;
+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Dual Purpose and Dedicated Pins                                                                                             ;
+----------+------------------------------------------+------------------------+------------------+---------------------------+
; Location ; Pin Name                                 ; Reserved As            ; User Signal Name ; Pin Type                  ;
+----------+------------------------------------------+------------------------+------------------+---------------------------+
; C1       ; DIFFIO_L4n, DATA1, ASDO                  ; Use as regular IO      ; flash_mosi       ; Dual Purpose Pin          ;
; D2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; Use as regular IO      ; flash_cs_n       ; Dual Purpose Pin          ;
; F4       ; nSTATUS                                  ; -                      ; -                ; Dedicated Programming Pin ;
; H1       ; DCLK                                     ; Use as regular IO      ; flash_clk        ; Dual Purpose Pin          ;
; H2       ; DATA0                                    ; Use as regular IO      ; flash_miso       ; Dual Purpose Pin          ;
; H5       ; nCONFIG                                  ; -                      ; -                ; Dedicated Programming Pin ;
; J3       ; nCE                                      ; -                      ; -                ; Dedicated Programming Pin ;
; J16      ; DIFFIO_R21n, DEV_OE                      ; Use as regular IO      ; hdmi_clk(n)      ; Dual Purpose Pin          ;
; J15      ; DIFFIO_R21p, DEV_CLRn                    ; Use as regular IO      ; hdmi_clk         ; Dual Purpose Pin          ;
; H14      ; CONF_DONE                                ; -                      ; -                ; Dedicated Programming Pin ;
; H13      ; MSEL0                                    ; -                      ; -                ; Dedicated Programming Pin ;
; H12      ; MSEL1                                    ; -                      ; -                ; Dedicated Programming Pin ;
; G12      ; MSEL2                                    ; -                      ; -                ; Dedicated Programming Pin ;
; G12      ; MSEL3                                    ; -                      ; -                ; Dedicated Programming Pin ;
; G16      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO      ; sd_cmd           ; Dual Purpose Pin          ;
; G15      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO      ; sd_clk           ; Dual Purpose Pin          ;
; F16      ; DIFFIO_R16n, nCEO                        ; Use as programming pin ; sd_dat[3]        ; Dual Purpose Pin          ;
; F15      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO      ; sd_dat[0]        ; Dual Purpose Pin          ;
; C16      ; DIFFIO_R2n, PADD20, DQS2R/CQ3R,CDPCLK5   ; Use as regular IO      ; i2c_scl          ; Dual Purpose Pin          ;
; A12      ; DIFFIO_T27p, PADD0                       ; Use as regular IO      ; sr_dq[0]         ; Dual Purpose Pin          ;
; A11      ; DIFFIO_T25n, PADD1                       ; Use as regular IO      ; sr_dq[5]         ; Dual Purpose Pin          ;
; B11      ; DIFFIO_T25p, PADD2                       ; Use as regular IO      ; sr_dq[4]         ; Dual Purpose Pin          ;
; A15      ; DIFFIO_T23n, PADD3                       ; Use as regular IO      ; sr_a[3]          ; Dual Purpose Pin          ;
; F9       ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO      ; sr_we_n          ; Dual Purpose Pin          ;
; A10      ; DIFFIO_T20n, PADD5                       ; Use as regular IO      ; sr_dq[7]         ; Dual Purpose Pin          ;
; B10      ; DIFFIO_T20p, PADD6                       ; Use as regular IO      ; sr_dq[6]         ; Dual Purpose Pin          ;
; C9       ; DIFFIO_T19n, PADD7                       ; Use as regular IO      ; sr_a[4]          ; Dual Purpose Pin          ;
; D9       ; DIFFIO_T19p, PADD8                       ; Use as regular IO      ; sr_a[5]          ; Dual Purpose Pin          ;
; E9       ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO      ; sr_cas_n         ; Dual Purpose Pin          ;
; C8       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO      ; sr_a[11]         ; Dual Purpose Pin          ;
; E8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO      ; sr_a[6]          ; Dual Purpose Pin          ;
; F8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO      ; sr_cke           ; Dual Purpose Pin          ;
; A7       ; DIFFIO_T11n, PADD18                      ; Use as regular IO      ; sr_a[7]          ; Dual Purpose Pin          ;
; B7       ; DIFFIO_T11p, DATA4                       ; Use as regular IO      ; sr_a[8]          ; Dual Purpose Pin          ;
; A6       ; DIFFIO_T9n, DATA14, DQS3T/CQ3T#,DPCLK11  ; Use as regular IO      ; sr_a[9]          ; Dual Purpose Pin          ;
; B6       ; DIFFIO_T9p, DATA13                       ; Use as regular IO      ; sr_a[12]         ; Dual Purpose Pin          ;
; E7       ; DATA5                                    ; Use as regular IO      ; sr_dq[9]         ; Dual Purpose Pin          ;
; E6       ; DIFFIO_T6p, DATA6                        ; Use as regular IO      ; sr_dq[12]        ; Dual Purpose Pin          ;
; A5       ; DATA7                                    ; Use as regular IO      ; sr_dq[8]         ; Dual Purpose Pin          ;
; B5       ; DIFFIO_T5p, DATA8                        ; Use as regular IO      ; sr_dq[10]        ; Dual Purpose Pin          ;
; D6       ; DIFFIO_T4n, DATA9                        ; Use as regular IO      ; sr_dq[13]        ; Dual Purpose Pin          ;
; A4       ; DIFFIO_T3n, DATA10                       ; Use as regular IO      ; sr_dq[11]        ; Dual Purpose Pin          ;
; B4       ; DIFFIO_T3p, DATA11                       ; Use as regular IO      ; abc_rdy_x        ; Dual Purpose Pin          ;
; B3       ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO      ; abc_int80_x      ; Dual Purpose Pin          ;
+----------+------------------------------------------+------------------------+------------------+---------------------------+


+-------------------------------------------------------------+
; I/O Bank Usage                                              ;
+----------+-------------------+---------------+--------------+
; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1        ; 14 / 14 ( 100 % ) ; 3.3V          ; --           ;
; 2        ; 16 / 18 ( 89 % )  ; 3.3V          ; --           ;
; 3        ; 25 / 25 ( 100 % ) ; 3.3V          ; --           ;
; 4        ; 20 / 27 ( 74 % )  ; 3.3V          ; --           ;
; 5        ; 9 / 20 ( 45 % )   ; 2.5V          ; --           ;
; 6        ; 13 / 14 ( 93 % )  ; 3.3V          ; --           ;
; 7        ; 23 / 24 ( 96 % )  ; 3.3V          ; --           ;
; 8        ; 23 / 24 ( 96 % )  ; 3.3V          ; --           ;
+----------+-------------------+---------------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                             ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
; A1       ;            ; 8        ; VCCIO8         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; A2       ; 356        ; 8        ; abc_int800_x   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A3       ; 358        ; 8        ; abc_nmi_x      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A4       ; 354        ; 8        ; sr_dq[11]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A5       ; 349        ; 8        ; sr_dq[8]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A6       ; 339        ; 8        ; sr_a[9]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A7       ; 334        ; 8        ; sr_a[7]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A8       ; 321        ; 8        ; abc_a[0]       ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A9       ; 319        ; 7        ; abc_a[2]       ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A10      ; 307        ; 7        ; sr_dq[7]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A11      ; 296        ; 7        ; sr_dq[5]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A12      ; 292        ; 7        ; sr_dq[0]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A13      ; 300        ; 7        ; sr_ba[0]       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A14      ; 284        ; 7        ; sr_a[0]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A15      ; 301        ; 7        ; sr_a[3]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; A16      ;            ; 7        ; VCCIO7         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; B1       ; 6          ; 1        ; abc_xm_x       ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; B2       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; B3       ; 359        ; 8        ; abc_int80_x    ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B4       ; 355        ; 8        ; abc_rdy_x      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B5       ; 351        ; 8        ; sr_dq[10]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B6       ; 340        ; 8        ; sr_a[12]       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B7       ; 335        ; 8        ; sr_a[8]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B8       ; 322        ; 8        ; abc_a[1]       ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B9       ; 320        ; 7        ; GND+           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; B10      ; 308        ; 7        ; sr_dq[6]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B11      ; 297        ; 7        ; sr_dq[4]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B12      ; 293        ; 7        ; sr_ras_n       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B13      ; 282        ; 7        ; sr_ba[1]       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B14      ; 285        ; 7        ; sr_a[1]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; B15      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; B16      ; 241        ; 6        ; rtc_int_n      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; C1       ; 9          ; 1        ; flash_mosi     ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
; C2       ; 8          ; 1        ; abc_a_oe       ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; C3       ; 362        ; 8        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; C4       ;            ; 8        ; VCCIO8         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; C5       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C6       ; 338        ; 8        ; sr_dq[14]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C7       ;            ; 8        ; VCCIO8         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; C8       ; 329        ; 8        ; sr_a[11]       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C9       ; 309        ; 7        ; sr_a[4]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C10      ;            ; 7        ; VCCIO7         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; C11      ; 281        ; 7        ; sr_dq[3]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C12      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; C13      ;            ; 7        ; VCCIO7         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; C14      ; 274        ; 7        ; sr_a[10]       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; C15      ; 271        ; 6        ; i2c_sda        ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; C16      ; 270        ; 6        ; i2c_scl        ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; D1       ; 14         ; 1        ; abc_a[3]       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; D2       ; 13         ; 1        ; flash_cs_n     ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
; D3       ; 363        ; 8        ; sr_clk         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D4       ;            ;          ; VCCD_PLL3      ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; D5       ; 357        ; 8        ; sr_dq[15]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D6       ; 352        ; 8        ; sr_dq[13]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D7       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D8       ; 330        ; 8        ; sr_dqm[1]      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D9       ; 310        ; 7        ; sr_a[5]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D10      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; D11      ; 278        ; 7        ; sr_dq[2]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D12      ; 279        ; 7        ; sr_cs_n        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D13      ;            ;          ; VCCD_PLL2      ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; D14      ; 275        ; 7        ; sr_a[2]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; D15      ; 261        ; 6        ; tty_cts        ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; D16      ; 260        ; 6        ; tty_rts        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; E1       ; 39         ; 1        ; abc_a[6]       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; E2       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E3       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; E4       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E5       ;            ;          ; GNDA3          ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E6       ; 348        ; 8        ; sr_dq[12]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E7       ; 345        ; 8        ; sr_dq[9]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E8       ; 332        ; 8        ; sr_a[6]        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E9       ; 315        ; 7        ; sr_cas_n       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E10      ; 290        ; 7        ; sr_dqm[0]      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E11      ; 289        ; 7        ; sr_dq[1]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; E12      ;            ;          ; GNDA2          ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E13      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; E14      ;            ; 6        ; VCCIO6         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; E15      ; 226        ; 6        ; rtc_32khz      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; E16      ; 225        ; 6        ; tty_txd        ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F1       ; 23         ; 1        ; abc_a[7]       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F2       ; 22         ; 1        ; abc_cs_n       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F3       ; 10         ; 1        ; abc_a[5]       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F4       ; 19         ; 1        ; ^nSTATUS       ;        ;              ;         ; --         ;                 ; --       ; --           ;
; F5       ;            ; --       ; VCCA3          ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; F6       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; F7       ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; F8       ; 333        ; 8        ; sr_cke         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; F9       ; 306        ; 7        ; sr_we_n        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; F10      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; F11      ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; F12      ;            ; --       ; VCCA2          ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; F13      ; 237        ; 6        ; tty_rxd        ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F14      ; 257        ; 6        ; sd_dat[2]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F15      ; 240        ; 6        ; sd_dat[0]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; F16      ; 239        ; 6        ; sd_dat[3]      ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G1       ; 27         ; 1        ; abc_a[8]       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G2       ; 24         ; 1        ; abc_out_n[0]   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G3       ;            ; 1        ; VCCIO1         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; G4       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; G5       ; 21         ; 1        ; abc_a[4]       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G6       ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G7       ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G8       ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G9       ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G10      ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; G11      ; 269        ; 6        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; G12      ; 230        ; 6        ; ^MSEL2         ;        ;              ;         ; --         ;                 ; --       ; --           ;
; G12      ; 231        ; 6        ; ^MSEL3         ;        ;              ;         ; --         ;                 ; --       ; --           ;
; G13      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; G14      ;            ; 6        ; VCCIO6         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; G15      ; 235        ; 6        ; sd_clk         ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; G16      ; 234        ; 6        ; sd_cmd         ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; H1       ; 30         ; 1        ; flash_clk      ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
; H2       ; 31         ; 1        ; flash_miso     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; On           ;
; H3       ; 34         ; 1        ; #TCK           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; H4       ; 33         ; 1        ; #TDI           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; H5       ; 32         ; 1        ; ^nCONFIG       ;        ;              ;         ; --         ;                 ; --       ; --           ;
; H6       ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; H7       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H8       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H9       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H10      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H11      ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; H12      ; 229        ; 6        ; ^MSEL1         ;        ;              ;         ; --         ;                 ; --       ; --           ;
; H13      ; 228        ; 6        ; ^MSEL0         ;        ;              ;         ; --         ;                 ; --       ; --           ;
; H14      ; 227        ; 6        ; ^CONF_DONE     ;        ;              ;         ; --         ;                 ; --       ; --           ;
; H15      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; H16      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J1       ; 45         ; 2        ; abc_a[9]       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J2       ; 44         ; 2        ; abc_out_n[1]   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J3       ; 37         ; 1        ; ^nCE           ;        ;              ;         ; --         ;                 ; --       ; --           ;
; J4       ; 36         ; 1        ; #TDO           ; output ;              ;         ; --         ;                 ; --       ; --           ;
; J5       ; 35         ; 1        ; #TMS           ; input  ;              ;         ; --         ;                 ; --       ; --           ;
; J6       ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; J7       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J8       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J9       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J10      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J11      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; J12      ; 221        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; J13      ; 222        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; J14      ; 220        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; J15      ; 217        ; 5        ; hdmi_clk       ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
; J16      ; 216        ; 5        ; hdmi_clk(n)    ; output ; LVDS         ;         ; Row I/O    ; N               ; no       ; Off          ;
; K1       ; 55         ; 2        ; abc_a[11]      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; K2       ; 72         ; 2        ; abc_out_n[4]   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; K3       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; K4       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K5       ; 77         ; 2        ; abc_out_n[2]   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; K6       ; 48         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; K7       ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K8       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K9       ; 138        ; 4        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; K10      ; 150        ; 4        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; K11      ;            ;          ; VCCINT         ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; K12      ; 179        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; K13      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; K14      ;            ; 5        ; VCCIO5         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; K15      ; 215        ; 5        ; hdmi_d[0]      ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
; K16      ; 214        ; 5        ; hdmi_d[0](n)   ; output ; LVDS         ;         ; Row I/O    ; N               ; no       ; Off          ;
; L1       ; 58         ; 2        ; abc_a[12]      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L2       ; 57         ; 2        ; abc_inp_n[0]   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L3       ; 51         ; 2        ; abc_out_n[3]   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L4       ; 78         ; 2        ; abc_a[10]      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; L5       ;            ; --       ; VCCA1          ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; L6       ; 49         ; 2        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; L7       ; 125        ; 3        ; gpio[0]        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; L8       ; 128        ; 3        ; esp_io0        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; L9       ; 139        ; 4        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; L10      ; 153        ; 4        ; abc_xoutpstb_n ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; L11      ; 173        ; 4        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; L12      ;            ; --       ; VCCA4          ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; L13      ; 203        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; L14      ; 194        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; L15      ; 208        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; L16      ; 204        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; M1       ; 41         ; 2        ; abc_a[13]      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; M2       ; 40         ; 2        ; abc_inp_n[1]   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; M3       ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; M4       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M5       ;            ;          ; GNDA1          ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M6       ; 106        ; 3        ; abc_d[1]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; M7       ; 120        ; 3        ; spi_miso       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; M8       ; 131        ; 3        ; spi_mosi       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; M9       ; 140        ; 4        ; GND*           ;        ;              ;         ; Column I/O ;                 ; no       ; Off          ;
; M10      ; 164        ; 4        ; sd_dat[1]      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; M11      ; 174        ; 4        ; hdmi_scl       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; M12      ;            ;          ; GNDA4          ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M13      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; M14      ;            ; 5        ; VCCIO5         ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
; M15      ; 224        ; 5        ; clock_48       ; input  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
; M16      ; 223        ; 5        ; GND+           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
; N1       ; 76         ; 2        ; abc_a[15]      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; N2       ; 75         ; 2        ; abc_a[14]      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; N3       ; 92         ; 3        ; abc_xmemfl_n   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N4       ;            ;          ; VCCD_PLL1      ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; N5       ; 104        ; 3        ; abc_d[2]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N6       ; 105        ; 3        ; spi_cs_flash_n ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N7       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N8       ; 132        ; 3        ; spi_cs_esp_n   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N9       ; 141        ; 4        ; exth_hb        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N10      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; N11      ; 165        ; 4        ; exth_hg        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N12      ; 155        ; 4        ; exth_ha        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; N13      ;            ;          ; VCCD_PLL4      ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
; N14      ; 181        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; N15      ; 191        ; 5        ; hdmi_d[1]      ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
; N16      ; 190        ; 5        ; hdmi_d[1](n)   ; output ; LVDS         ;         ; Row I/O    ; N               ; no       ; Off          ;
; P1       ; 83         ; 2        ; abc_xmemw800_n ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; P2       ; 82         ; 2        ; abc_rst_n      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; P3       ; 93         ; 3        ; abc_d[0]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; P4       ;            ; 3        ; VCCIO3         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; P5       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; P6       ; 119        ; 3        ; spi_clk        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; P7       ;            ; 3        ; VCCIO3         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; P8       ; 133        ; 3        ; esp_int        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; P9       ; 154        ; 4        ; gpio[1]        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; P10      ;            ; 4        ; VCCIO4         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; P11      ; 168        ; 4        ; GND*           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; P12      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; P13      ;            ; 4        ; VCCIO4         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; P14      ; 171        ; 4        ; tty_dtr        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; P15      ; 182        ; 5        ; GND*           ;        ;              ;         ; Row I/O    ;                 ; no       ; Off          ;
; P16      ; 183        ; 5        ; hdmi_d[2](n)   ; output ; LVDS         ;         ; Row I/O    ; N               ; no       ; Off          ;
; R1       ; 81         ; 2        ; abc_xmemw80_n  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
; R2       ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; R3       ; 95         ; 3        ; abc_d[4]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R4       ; 102        ; 3        ; abc_d[6]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R5       ; 121        ; 3        ; abc_d_ce_n     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R6       ; 123        ; 3        ; abc_resin_x    ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R7       ; 126        ; 3        ; gpio[5]        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R8       ; 134        ; 3        ; exth_hh        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R9       ; 136        ; 4        ; GND+           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
; R10      ; 143        ; 4        ; gpio[3]        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R11      ; 145        ; 4        ; exth_hd        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R12      ; 147        ; 4        ; exth_he        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R13      ; 156        ; 4        ; hdmi_sda       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R14      ; 172        ; 4        ; led[2]         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; R15      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
; R16      ; 184        ; 5        ; hdmi_d[2]      ; output ; LVDS         ;         ; Row I/O    ; Y               ; no       ; Off          ;
; T1       ;            ; 3        ; VCCIO3         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
; T2       ; 101        ; 3        ; abc_d[3]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T3       ; 96         ; 3        ; abc_d[5]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T4       ; 103        ; 3        ; abc_d[7]       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T5       ; 122        ; 3        ; abc_d_oe       ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T6       ; 124        ; 3        ; gpio[2]        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T7       ; 127        ; 3        ; gpio[4]        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T8       ; 135        ; 3        ; abc_clk        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T9       ; 137        ; 4        ; exth_hc        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T10      ; 144        ; 4        ; abc_master     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T11      ; 146        ; 4        ; exth_hf        ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T12      ; 149        ; 4        ; abc_xinpstb_n  ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T13      ; 157        ; 4        ; led[1]         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T14      ; 166        ; 4        ; led[3]         ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T15      ; 167        ; 4        ; hdmi_hpd       ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
; T16      ;            ; 4        ; VCCIO4         ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Summary                                                                                                                                                                              ;
+-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; Name                          ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll ;
+-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; SDC pin name                  ; pll|altpll_component|auto_generated|pll1                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll                                  ;
; PLL mode                      ; Normal                                                         ; Normal                                                                                  ;
; Compensate clock              ; clock0                                                         ; clock0                                                                                  ;
; Compensated input/output pins ; --                                                             ; --                                                                                      ;
; Switchover type               ; --                                                             ; --                                                                                      ;
; Input frequency 0             ; 48.0 MHz                                                       ; 36.0 MHz                                                                                ;
; Input frequency 1             ; --                                                             ; --                                                                                      ;
; Nominal PFD frequency         ; 48.0 MHz                                                       ; 36.0 MHz                                                                                ;
; Nominal VCO frequency         ; 864.0 MHz                                                      ; 540.0 MHz                                                                               ;
; VCO post scale K counter      ; --                                                             ; 2                                                                                       ;
; VCO frequency control         ; Auto                                                           ; Auto                                                                                    ;
; VCO phase shift step          ; 144 ps                                                         ; 231 ps                                                                                  ;
; VCO multiply                  ; --                                                             ; --                                                                                      ;
; VCO divide                    ; --                                                             ; --                                                                                      ;
; Freq min lock                 ; 33.35 MHz                                                      ; 20.0 MHz                                                                                ;
; Freq max lock                 ; 72.24 MHz                                                      ; 43.35 MHz                                                                               ;
; M VCO Tap                     ; 0                                                              ; 6                                                                                       ;
; M Initial                     ; 1                                                              ; 1                                                                                       ;
; M value                       ; 18                                                             ; 15                                                                                      ;
; N value                       ; 1                                                              ; 1                                                                                       ;
; Charge pump current           ; setting 1                                                      ; setting 1                                                                               ;
; Loop filter resistance        ; setting 27                                                     ; setting 27                                                                              ;
; Loop filter capacitance       ; setting 0                                                      ; setting 0                                                                               ;
; Bandwidth                     ; 1.03 MHz to 1.97 MHz                                           ; 680 kHz to 980 kHz                                                                      ;
; Bandwidth type                ; Medium                                                         ; Medium                                                                                  ;
; Real time reconfigurable      ; Off                                                            ; Off                                                                                     ;
; Scan chain MIF file           ; --                                                             ; --                                                                                      ;
; Preserve PLL counter order    ; Off                                                            ; Off                                                                                     ;
; PLL location                  ; PLL_2                                                          ; PLL_1                                                                                   ;
; Inclk0 signal                 ; clock_48                                                       ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]              ;
; Inclk1 signal                 ; --                                                             ; --                                                                                      ;
; Inclk0 signal type            ; Dedicated Pin                                                  ; Global Clock                                                                            ;
; Inclk1 signal type            ; --                                                             ; --                                                                                      ;
+-------------------------------+----------------------------------------------------------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
; Name                                                                                                ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift    ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                                  ;
+-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; clock0       ; 2    ; 1   ; 96.0 MHz         ; 0 (0 ps)       ; 5.00 (144 ps)    ; 50/50      ; C0      ; 9             ; 5/4 Odd    ; --            ; 1       ; 0       ; pll|altpll_component|auto_generated|pll1|clk[0]               ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; clock1       ; 2    ; 1   ; 96.0 MHz         ; 0 (0 ps)       ; 5.00 (144 ps)    ; 50/50      ; C2      ; 9             ; 5/4 Odd    ; --            ; 1       ; 0       ; pll|altpll_component|auto_generated|pll1|clk[1]               ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; clock2       ; 3    ; 4   ; 36.0 MHz         ; 0 (0 ps)       ; 1.88 (144 ps)    ; 50/50      ; C1      ; 24            ; 12/12 Even ; --            ; 1       ; 0       ; pll|altpll_component|auto_generated|pll1|clk[2]               ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; clock0       ; 5    ; 1   ; 180.0 MHz        ; -90 (-1389 ps) ; 15.00 (231 ps)   ; 50/50      ; C0      ; 3             ; 2/1 Odd    ; --            ; 1       ; 0       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; clock1       ; 1    ; 1   ; 36.0 MHz         ; -18 (-1389 ps) ; 3.00 (231 ps)    ; 50/50      ; C1      ; 15            ; 8/7 Odd    ; --            ; 1       ; 0       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ;
+-----------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+---------------------------------------------------------------+


+-----------------------------------------+
; I/O Assignment Warnings                 ;
+----------------+------------------------+
; Pin Name       ; Reason                 ;
+----------------+------------------------+
; abc_d_oe       ; Missing drive strength ;
; abc_rdy_x      ; Missing drive strength ;
; abc_resin_x    ; Missing drive strength ;
; abc_int80_x    ; Missing drive strength ;
; abc_int800_x   ; Missing drive strength ;
; abc_nmi_x      ; Missing drive strength ;
; abc_xm_x       ; Missing drive strength ;
; abc_master     ; Missing drive strength ;
; abc_a_oe       ; Missing drive strength ;
; abc_d_ce_n     ; Missing drive strength ;
; sr_cke         ; Missing drive strength ;
; sr_ba[0]       ; Missing drive strength ;
; sr_ba[1]       ; Missing drive strength ;
; sr_a[0]        ; Missing drive strength ;
; sr_a[1]        ; Missing drive strength ;
; sr_a[2]        ; Missing drive strength ;
; sr_a[3]        ; Missing drive strength ;
; sr_a[4]        ; Missing drive strength ;
; sr_a[5]        ; Missing drive strength ;
; sr_a[6]        ; Missing drive strength ;
; sr_a[7]        ; Missing drive strength ;
; sr_a[8]        ; Missing drive strength ;
; sr_a[9]        ; Missing drive strength ;
; sr_a[10]       ; Missing drive strength ;
; sr_a[11]       ; Missing drive strength ;
; sr_a[12]       ; Missing drive strength ;
; sr_dqm[0]      ; Missing drive strength ;
; sr_dqm[1]      ; Missing drive strength ;
; sr_cs_n        ; Missing drive strength ;
; sr_we_n        ; Missing drive strength ;
; sr_cas_n       ; Missing drive strength ;
; sr_ras_n       ; Missing drive strength ;
; sd_clk         ; Missing drive strength ;
; sd_cmd         ; Missing drive strength ;
; tty_rxd        ; Missing drive strength ;
; tty_cts        ; Missing drive strength ;
; flash_cs_n     ; Missing drive strength ;
; flash_clk      ; Missing drive strength ;
; flash_mosi     ; Missing drive strength ;
; led[2]         ; Missing drive strength ;
; led[3]         ; Missing drive strength ;
; abc_d[0]       ; Missing drive strength ;
; abc_d[1]       ; Missing drive strength ;
; abc_d[2]       ; Missing drive strength ;
; abc_d[3]       ; Missing drive strength ;
; abc_d[4]       ; Missing drive strength ;
; abc_d[5]       ; Missing drive strength ;
; abc_d[6]       ; Missing drive strength ;
; abc_d[7]       ; Missing drive strength ;
; hdmi_sda       ; Missing drive strength ;
; exth_ha        ; Missing drive strength ;
; exth_hb        ; Missing drive strength ;
; exth_hd        ; Missing drive strength ;
; exth_he        ; Missing drive strength ;
; exth_hf        ; Missing drive strength ;
; exth_hg        ; Missing drive strength ;
; sr_dq[0]       ; Missing drive strength ;
; sr_dq[1]       ; Missing drive strength ;
; sr_dq[2]       ; Missing drive strength ;
; sr_dq[3]       ; Missing drive strength ;
; sr_dq[4]       ; Missing drive strength ;
; sr_dq[5]       ; Missing drive strength ;
; sr_dq[6]       ; Missing drive strength ;
; sr_dq[7]       ; Missing drive strength ;
; sr_dq[8]       ; Missing drive strength ;
; sr_dq[9]       ; Missing drive strength ;
; sr_dq[10]      ; Missing drive strength ;
; sr_dq[11]      ; Missing drive strength ;
; sr_dq[12]      ; Missing drive strength ;
; sr_dq[13]      ; Missing drive strength ;
; sr_dq[14]      ; Missing drive strength ;
; sr_dq[15]      ; Missing drive strength ;
; sd_dat[0]      ; Missing drive strength ;
; sd_dat[1]      ; Missing drive strength ;
; sd_dat[2]      ; Missing drive strength ;
; sd_dat[3]      ; Missing drive strength ;
; spi_clk        ; Missing drive strength ;
; spi_miso       ; Missing drive strength ;
; spi_mosi       ; Missing drive strength ;
; spi_cs_esp_n   ; Missing drive strength ;
; spi_cs_flash_n ; Missing drive strength ;
; esp_io0        ; Missing drive strength ;
; esp_int        ; Missing drive strength ;
; i2c_scl        ; Missing drive strength ;
; i2c_sda        ; Missing drive strength ;
; gpio[0]        ; Missing drive strength ;
; gpio[1]        ; Missing drive strength ;
; gpio[2]        ; Missing drive strength ;
; gpio[3]        ; Missing drive strength ;
; gpio[4]        ; Missing drive strength ;
; gpio[5]        ; Missing drive strength ;
; hdmi_scl       ; Missing drive strength ;
; hdmi_hpd       ; Missing drive strength ;
+----------------+------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                        ;
+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
; Compilation Hierarchy Node                                   ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                ; Entity Name               ; Library Name ;
+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
; |max80                                                       ; 327 (69)    ; 218 (66)                  ; 11 (11)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 143  ; 0            ; 109 (3)      ; 49 (0)            ; 169 (49)         ; |max80                                                                                                             ; max80                     ; work         ;
;    |hdmitx:hdmitx|                                           ; 118 (0)     ; 109 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (0)        ; 40 (0)            ; 69 (0)           ; |max80|hdmitx:hdmitx                                                                                               ; hdmitx                    ; work         ;
;       |altlvds_tx:ALTLVDS_TX_component|                      ; 118 (0)     ; 109 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (0)        ; 40 (0)            ; 69 (0)           ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ; altlvds_tx                ; work         ;
;          |hdmitx_lvds_tx:auto_generated|                     ; 118 (59)    ; 109 (60)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (0)        ; 40 (39)           ; 69 (20)          ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ; hdmitx_lvds_tx            ; work         ;
;             |hdmitx_cntr:cntr13|                             ; 8 (8)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 4 (4)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ; hdmitx_cntr               ; work         ;
;             |hdmitx_cntr:cntr2|                              ; 8 (8)       ; 3 (3)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 3 (3)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ; hdmitx_cntr               ; work         ;
;             |hdmitx_ddio_out1:outclock_ddio|                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ; hdmitx_ddio_out1          ; work         ;
;             |hdmitx_ddio_out:ddio_out|                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ; hdmitx_ddio_out           ; work         ;
;             |hdmitx_shift_reg1:shift_reg23|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg24|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg25|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg26|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg27|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg1:shift_reg28|                  ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ; hdmitx_shift_reg1         ; work         ;
;             |hdmitx_shift_reg:outclk_shift_h|                ; 7 (7)       ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ; hdmitx_shift_reg          ; work         ;
;             |hdmitx_shift_reg:outclk_shift_l|                ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 5 (5)            ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ; hdmitx_shift_reg          ; work         ;
;    |pll:pll|                                                 ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll                                                                                                     ; pll                       ; work         ;
;       |altpll:altpll_component|                              ; 6 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (0)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component                                                                             ; altpll                    ; work         ;
;          |pll_altpll:auto_generated|                         ; 6 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (3)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ; pll_altpll                ; work         ;
;             |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ; pll_altpll_dyn_phase_le12 ; work         ;
;             |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4|  ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ; pll_altpll_dyn_phase_le1  ; work         ;
;             |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2|   ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ; pll_altpll_dyn_phase_le   ; work         ;
;    |tmdsenc:hdmitmds[0].enc|                                 ; 51 (51)     ; 15 (15)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 29 (29)      ; 3 (3)             ; 19 (19)          ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ; tmdsenc                   ; work         ;
;    |tmdsenc:hdmitmds[1].enc|                                 ; 50 (50)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 3 (3)             ; 16 (16)          ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ; tmdsenc                   ; work         ;
;    |tmdsenc:hdmitmds[2].enc|                                 ; 50 (50)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 3 (3)             ; 16 (16)          ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ; tmdsenc                   ; work         ;
+--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                                 ;
+----------------+----------+---------------+---------------+-----------------------+----------+------+
; Name           ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO      ; TCOE ;
+----------------+----------+---------------+---------------+-----------------------+----------+------+
; abc_clk        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[0]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[1]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[2]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[3]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[4]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[5]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[6]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[7]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[8]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[9]       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[10]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[11]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[12]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[13]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[14]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_a[15]      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_d_oe       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_rst_n      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_cs_n       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_out_n[0]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_out_n[1]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_out_n[2]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_out_n[3]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_out_n[4]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_inp_n[0]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_inp_n[1]   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_xmemfl_n   ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_xmemw800_n ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_xmemw80_n  ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_xinpstb_n  ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_xoutpstb_n ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; abc_rdy_x      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_resin_x    ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_int80_x    ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_int800_x   ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_nmi_x      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_xm_x       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_master     ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_a_oe       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; abc_d_ce_n     ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; exth_hc        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; exth_hh        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; sr_clk         ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_cke         ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_ba[0]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_ba[1]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[0]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[1]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[2]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[3]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[4]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[5]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[6]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[7]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[8]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[9]        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[10]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[11]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_a[12]       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_dqm[0]      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_dqm[1]      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_cs_n        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_we_n        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_cas_n       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sr_ras_n       ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sd_clk         ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; sd_cmd         ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; tty_txd        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; tty_rxd        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; tty_rts        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; tty_cts        ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; tty_dtr        ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; flash_cs_n     ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; flash_clk      ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; flash_mosi     ; Output   ; --            ; --            ; --                    ; --       ; --   ;
; flash_miso     ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; rtc_32khz      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; rtc_int_n      ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; led[1]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; led[2]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; led[3]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; hdmi_d[0]      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; hdmi_d[1]      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; hdmi_d[2]      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; hdmi_clk       ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; abc_d[0]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; abc_d[1]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; abc_d[2]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; abc_d[3]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; abc_d[4]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; abc_d[5]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; abc_d[6]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; abc_d[7]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; hdmi_sda       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; exth_ha        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; exth_hb        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; exth_hd        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; exth_he        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; exth_hf        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; exth_hg        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[0]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[1]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[2]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[3]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[4]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[5]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[6]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[7]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[8]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[9]       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[10]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[11]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[12]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[13]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[14]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sr_dq[15]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sd_dat[0]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sd_dat[1]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sd_dat[2]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; sd_dat[3]      ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; spi_clk        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; spi_miso       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; spi_mosi       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; spi_cs_esp_n   ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; spi_cs_flash_n ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; esp_io0        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; esp_int        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; i2c_scl        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; i2c_sda        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; gpio[0]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; gpio[1]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; gpio[2]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; gpio[3]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; gpio[4]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; gpio[5]        ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; hdmi_scl       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; hdmi_hpd       ; Bidir    ; --            ; --            ; --                    ; --       ; --   ;
; clock_48       ; Input    ; --            ; --            ; --                    ; --       ; --   ;
; hdmi_d[0](n)   ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; hdmi_d[1](n)   ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; hdmi_d[2](n)   ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
; hdmi_clk(n)    ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --   ;
+----------------+----------+---------------+---------------+-----------------------+----------+------+


+---------------------------------------------------+
; Pad To Core Delay Chain Fanout                    ;
+---------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+---------------------+-------------------+---------+
; abc_clk             ;                   ;         ;
; abc_a[0]            ;                   ;         ;
; abc_a[1]            ;                   ;         ;
; abc_a[2]            ;                   ;         ;
; abc_a[3]            ;                   ;         ;
; abc_a[4]            ;                   ;         ;
; abc_a[5]            ;                   ;         ;
; abc_a[6]            ;                   ;         ;
; abc_a[7]            ;                   ;         ;
; abc_a[8]            ;                   ;         ;
; abc_a[9]            ;                   ;         ;
; abc_a[10]           ;                   ;         ;
; abc_a[11]           ;                   ;         ;
; abc_a[12]           ;                   ;         ;
; abc_a[13]           ;                   ;         ;
; abc_a[14]           ;                   ;         ;
; abc_a[15]           ;                   ;         ;
; abc_rst_n           ;                   ;         ;
; abc_cs_n            ;                   ;         ;
; abc_out_n[0]        ;                   ;         ;
; abc_out_n[1]        ;                   ;         ;
; abc_out_n[2]        ;                   ;         ;
; abc_out_n[3]        ;                   ;         ;
; abc_out_n[4]        ;                   ;         ;
; abc_inp_n[0]        ;                   ;         ;
; abc_inp_n[1]        ;                   ;         ;
; abc_xmemfl_n        ;                   ;         ;
; abc_xmemw800_n      ;                   ;         ;
; abc_xmemw80_n       ;                   ;         ;
; abc_xinpstb_n       ;                   ;         ;
; abc_xoutpstb_n      ;                   ;         ;
; exth_hc             ;                   ;         ;
; exth_hh             ;                   ;         ;
; tty_txd             ;                   ;         ;
; tty_rts             ;                   ;         ;
; tty_dtr             ;                   ;         ;
; flash_miso          ;                   ;         ;
; rtc_32khz           ;                   ;         ;
; rtc_int_n           ;                   ;         ;
; abc_d[0]            ;                   ;         ;
; abc_d[1]            ;                   ;         ;
; abc_d[2]            ;                   ;         ;
; abc_d[3]            ;                   ;         ;
; abc_d[4]            ;                   ;         ;
; abc_d[5]            ;                   ;         ;
; abc_d[6]            ;                   ;         ;
; abc_d[7]            ;                   ;         ;
; hdmi_sda            ;                   ;         ;
; exth_ha             ;                   ;         ;
; exth_hb             ;                   ;         ;
; exth_hd             ;                   ;         ;
; exth_he             ;                   ;         ;
; exth_hf             ;                   ;         ;
; exth_hg             ;                   ;         ;
; sr_dq[0]            ;                   ;         ;
; sr_dq[1]            ;                   ;         ;
; sr_dq[2]            ;                   ;         ;
; sr_dq[3]            ;                   ;         ;
; sr_dq[4]            ;                   ;         ;
; sr_dq[5]            ;                   ;         ;
; sr_dq[6]            ;                   ;         ;
; sr_dq[7]            ;                   ;         ;
; sr_dq[8]            ;                   ;         ;
; sr_dq[9]            ;                   ;         ;
; sr_dq[10]           ;                   ;         ;
; sr_dq[11]           ;                   ;         ;
; sr_dq[12]           ;                   ;         ;
; sr_dq[13]           ;                   ;         ;
; sr_dq[14]           ;                   ;         ;
; sr_dq[15]           ;                   ;         ;
; sd_dat[0]           ;                   ;         ;
; sd_dat[1]           ;                   ;         ;
; sd_dat[2]           ;                   ;         ;
; sd_dat[3]           ;                   ;         ;
; spi_clk             ;                   ;         ;
; spi_miso            ;                   ;         ;
; spi_mosi            ;                   ;         ;
; spi_cs_esp_n        ;                   ;         ;
; spi_cs_flash_n      ;                   ;         ;
; esp_io0             ;                   ;         ;
; esp_int             ;                   ;         ;
; i2c_scl             ;                   ;         ;
; i2c_sda             ;                   ;         ;
; gpio[0]             ;                   ;         ;
; gpio[1]             ;                   ;         ;
; gpio[2]             ;                   ;         ;
; gpio[3]             ;                   ;         ;
; gpio[4]             ;                   ;         ;
; gpio[5]             ;                   ;         ;
; hdmi_scl            ;                   ;         ;
; hdmi_hpd            ;                   ;         ;
; clock_48            ;                   ;         ;
+---------------------+-------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                                                                         ;
+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
; Name                                                                                                ; Location       ; Fan-Out ; Usage                   ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
; clock_48                                                                                            ; PIN_M15        ; 1       ; Clock                   ; no     ; --                   ; --               ; --                        ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; PLL_1          ; 82      ; Clock                   ; yes    ; Global Clock         ; GCLK3            ; --                        ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a            ; FF_X24_Y24_N19 ; 41      ; Clock enable            ; no     ; --                   ; --               ; --                        ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1          ; 31      ; Clock                   ; yes    ; Global Clock         ; GCLK4            ; --                        ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; PLL_2          ; 45      ; Clock                   ; yes    ; Global Clock         ; GCLK7            ; --                        ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; PLL_2          ; 68      ; Clock                   ; yes    ; Global Clock         ; GCLK9            ; --                        ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked                          ; PLL_2          ; 13      ; Async. clear            ; no     ; --                   ; --               ; --                        ;
; rst_n                                                                                               ; FF_X31_Y28_N1  ; 14      ; Clock enable            ; no     ; --                   ; --               ; --                        ;
; rst_n                                                                                               ; FF_X31_Y28_N1  ; 75      ; Async. clear            ; yes    ; Global Clock         ; GCLK13           ; --                        ;
; tmdsenc:hdmitmds[0].enc|denreg                                                                      ; FF_X27_Y22_N7  ; 42      ; Sync. clear, Sync. load ; no     ; --                   ; --               ; --                        ;
+-----------------------------------------------------------------------------------------------------+----------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                                                                                                                ;
+-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name                                                                                                ; Location      ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; PLL_1         ; 82      ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; PLL_1         ; 31      ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; PLL_2         ; 1       ; 0                                    ; Global Clock         ; GCLK8            ; --                        ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; PLL_2         ; 45      ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; PLL_2         ; 68      ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
; rst_n                                                                                               ; FF_X31_Y28_N1 ; 75      ; 0                                    ; Global Clock         ; GCLK13           ; --                        ;
+-----------------------------------------------------------------------------------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+


+------------------------------------------------+
; Routing Usage Summary                          ;
+-----------------------+------------------------+
; Routing Resource Type ; Usage                  ;
+-----------------------+------------------------+
; Block interconnects   ; 257 / 47,787 ( < 1 % ) ;
; C16 interconnects     ; 7 / 1,804 ( < 1 % )    ;
; C4 interconnects      ; 95 / 31,272 ( < 1 % )  ;
; Direct links          ; 75 / 47,787 ( < 1 % )  ;
; Global clocks         ; 6 / 20 ( 30 % )        ;
; Local interconnects   ; 196 / 15,408 ( 1 % )   ;
; R24 interconnects     ; 5 / 1,775 ( < 1 % )    ;
; R4 interconnects      ; 135 / 41,310 ( < 1 % ) ;
+-----------------------+------------------------+


+----------------------------------------------------------------------------+
; LAB Logic Elements                                                         ;
+---------------------------------------------+------------------------------+
; Number of Logic Elements  (Average = 11.28) ; Number of LABs  (Total = 29) ;
+---------------------------------------------+------------------------------+
; 1                                           ; 1                            ;
; 2                                           ; 5                            ;
; 3                                           ; 0                            ;
; 4                                           ; 0                            ;
; 5                                           ; 1                            ;
; 6                                           ; 0                            ;
; 7                                           ; 1                            ;
; 8                                           ; 1                            ;
; 9                                           ; 1                            ;
; 10                                          ; 0                            ;
; 11                                          ; 0                            ;
; 12                                          ; 1                            ;
; 13                                          ; 1                            ;
; 14                                          ; 3                            ;
; 15                                          ; 4                            ;
; 16                                          ; 10                           ;
+---------------------------------------------+------------------------------+


+-------------------------------------------------------------------+
; LAB-wide Signals                                                  ;
+------------------------------------+------------------------------+
; LAB-wide Signals  (Average = 1.52) ; Number of LABs  (Total = 29) ;
+------------------------------------+------------------------------+
; 1 Async. clear                     ; 10                           ;
; 1 Clock                            ; 22                           ;
; 1 Clock enable                     ; 3                            ;
; 1 Sync. clear                      ; 3                            ;
; 1 Sync. load                       ; 1                            ;
; 2 Clocks                           ; 5                            ;
+------------------------------------+------------------------------+


+-----------------------------------------------------------------------------+
; LAB Signals Sourced                                                         ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced  (Average = 18.45) ; Number of LABs  (Total = 29) ;
+----------------------------------------------+------------------------------+
; 0                                            ; 0                            ;
; 1                                            ; 0                            ;
; 2                                            ; 2                            ;
; 3                                            ; 3                            ;
; 4                                            ; 1                            ;
; 5                                            ; 0                            ;
; 6                                            ; 0                            ;
; 7                                            ; 1                            ;
; 8                                            ; 0                            ;
; 9                                            ; 0                            ;
; 10                                           ; 1                            ;
; 11                                           ; 0                            ;
; 12                                           ; 0                            ;
; 13                                           ; 0                            ;
; 14                                           ; 0                            ;
; 15                                           ; 0                            ;
; 16                                           ; 1                            ;
; 17                                           ; 1                            ;
; 18                                           ; 0                            ;
; 19                                           ; 3                            ;
; 20                                           ; 0                            ;
; 21                                           ; 0                            ;
; 22                                           ; 0                            ;
; 23                                           ; 5                            ;
; 24                                           ; 3                            ;
; 25                                           ; 0                            ;
; 26                                           ; 2                            ;
; 27                                           ; 1                            ;
; 28                                           ; 2                            ;
; 29                                           ; 1                            ;
; 30                                           ; 2                            ;
+----------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 4.93) ; Number of LABs  (Total = 29) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 1                            ;
; 1                                               ; 3                            ;
; 2                                               ; 9                            ;
; 3                                               ; 4                            ;
; 4                                               ; 1                            ;
; 5                                               ; 3                            ;
; 6                                               ; 0                            ;
; 7                                               ; 1                            ;
; 8                                               ; 0                            ;
; 9                                               ; 0                            ;
; 10                                              ; 0                            ;
; 11                                              ; 0                            ;
; 12                                              ; 7                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 6.76) ; Number of LABs  (Total = 29) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 5                            ;
; 3                                           ; 8                            ;
; 4                                           ; 1                            ;
; 5                                           ; 1                            ;
; 6                                           ; 0                            ;
; 7                                           ; 2                            ;
; 8                                           ; 1                            ;
; 9                                           ; 1                            ;
; 10                                          ; 2                            ;
; 11                                          ; 1                            ;
; 12                                          ; 0                            ;
; 13                                          ; 1                            ;
; 14                                          ; 1                            ;
; 15                                          ; 1                            ;
; 16                                          ; 2                            ;
; 17                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+------------------------------------------+
; I/O Rules Summary                        ;
+----------------------------------+-------+
; I/O Rules Statistic              ; Total ;
+----------------------------------+-------+
; Total I/O Rules                  ; 30    ;
; Number of I/O Rules Passed       ; 17    ;
; Number of I/O Rules Failed       ; 0     ;
; Number of I/O Rules Unchecked    ; 0     ;
; Number of I/O Rules Inapplicable ; 13    ;
+----------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details                                                                                                                                                                                                                                                                      ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+
; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                     ; Device ; Area                   ; Extra Information ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+
; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.         ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.             ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.               ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Termination assignments found.               ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                 ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                 ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                 ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.               ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.               ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Pass         ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; 0 such failures found.                          ; ALL    ; I/O                    ;                   ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.         ; ALL    ; I/O                    ;                   ;
; ----         ; ----      ; Disclaimer                        ; LVDS rules are checked but not reported.                                                             ; None     ; ----                                            ; ALL    ; Differential Signaling ;                   ;
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------------------------+-------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Pin/Rules          ; IO_000003    ; IO_000002    ; IO_000001    ; IO_000004 ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000020    ; IO_000011    ; IO_000021    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000009 ; IO_000010 ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000022    ; IO_000019    ; IO_000033 ; IO_000034    ; IO_000042    ;
+--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
; Total Pass         ; 139          ; 7            ; 139          ; 143       ; 0            ; 143       ; 139          ; 0            ; 91           ; 2            ; 4            ; 58           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 143       ; 143       ; 0            ; 0            ; 4            ; 91           ; 2            ; 0            ; 0            ; 143       ; 103          ; 0            ;
; Total Unchecked    ; 0            ; 0            ; 0            ; 0         ; 0            ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; Total Inapplicable ; 4            ; 136          ; 4            ; 0         ; 143          ; 0         ; 4            ; 143          ; 52           ; 141          ; 139          ; 85           ; 143          ; 143          ; 143          ; 143          ; 143          ; 143          ; 0         ; 0         ; 143          ; 143          ; 139          ; 52           ; 141          ; 143          ; 143          ; 0         ; 40           ; 143          ;
; Total Fail         ; 0            ; 0            ; 0            ; 0         ; 0            ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
; abc_clk            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[0]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[1]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[2]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[3]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[4]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[5]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[6]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[7]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[8]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[9]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[10]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[11]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[12]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[13]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[14]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_a[15]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_d_oe           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_rst_n          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_cs_n           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_out_n[0]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_out_n[1]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_out_n[2]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_out_n[3]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_out_n[4]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_inp_n[0]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_inp_n[1]       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_xmemfl_n       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_xmemw800_n     ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_xmemw80_n      ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_xinpstb_n      ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_xoutpstb_n     ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; abc_rdy_x          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_resin_x        ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_int80_x        ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_int800_x       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_nmi_x          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_xm_x           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_master         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_a_oe           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d_ce_n         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; exth_hc            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; exth_hh            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; sr_clk             ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_cke             ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_ba[0]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_ba[1]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[0]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[1]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[2]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[3]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[4]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[5]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[6]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[7]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[8]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[9]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[10]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[11]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_a[12]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dqm[0]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dqm[1]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_cs_n            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_we_n            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_cas_n           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_ras_n           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sd_clk             ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sd_cmd             ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; tty_txd            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; tty_rxd            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; tty_rts            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; tty_cts            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; tty_dtr            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; flash_cs_n         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; flash_clk          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; flash_mosi         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; flash_miso         ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; rtc_32khz          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; rtc_int_n          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; led[1]             ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; led[2]             ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; led[3]             ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_d[0]          ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_d[1]          ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_d[2]          ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_clk           ; Pass         ; Pass         ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d[0]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d[1]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d[2]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d[3]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d[4]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d[5]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d[6]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; abc_d[7]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_sda           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; exth_ha            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; exth_hb            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; exth_hd            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; exth_he            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; exth_hf            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; exth_hg            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[0]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[1]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[2]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[3]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[4]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[5]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[6]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[7]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[8]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[9]           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[10]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[11]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[12]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[13]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[14]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sr_dq[15]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sd_dat[0]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sd_dat[1]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sd_dat[2]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; sd_dat[3]          ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; spi_clk            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; spi_miso           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; spi_mosi           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; spi_cs_esp_n       ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; spi_cs_flash_n     ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; esp_io0            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; esp_int            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; i2c_scl            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; i2c_sda            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; gpio[0]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; gpio[1]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; gpio[2]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; gpio[3]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; gpio[4]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; gpio[5]            ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_scl           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_hpd           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; clock_48           ; Pass         ; Inapplicable ; Pass         ; Pass      ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
; hdmi_d[0](n)       ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_d[1](n)       ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_d[2](n)       ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
; hdmi_clk(n)        ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ;
+--------------------+--------------+--------------+--------------+-----------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+


+----------------------------------------------------------------------------------+
; Fitter Device Options                                                            ;
+------------------------------------------------------------------+---------------+
; Option                                                           ; Setting       ;
+------------------------------------------------------------------+---------------+
; Enable user-supplied start-up clock (CLKUSR)                     ; Off           ;
; Enable device-wide reset (DEV_CLRn)                              ; Off           ;
; Enable device-wide output enable (DEV_OE)                        ; Off           ;
; Enable INIT_DONE output                                          ; Off           ;
; Configuration scheme                                             ; Active Serial ;
; Error detection CRC                                              ; Off           ;
; Enable open drain on CRC_ERROR pin                               ; Off           ;
; Enable input tri-state on active configuration pins in user mode ; Off           ;
; Configuration Voltage Level                                      ; 3.3V          ;
; Force Configuration Voltage Level                                ; On            ;
; nCEO                                                             ; Unreserved    ;
; Data[0]                                                          ; Unreserved    ;
; Data[1]/ASDO                                                     ; Unreserved    ;
; Data[7..2]                                                       ; Unreserved    ;
; FLASH_nCE/nCSO                                                   ; Unreserved    ;
; Other Active Parallel pins                                       ; Unreserved    ;
; DCLK                                                             ; Unreserved    ;
+------------------------------------------------------------------+---------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 °C   ;
; High Junction Temperature ; 85 °C  ;
+---------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Summary                                                                                                     ;
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
; Source Clock(s)                                               ; Destination Clock(s)                                          ; Delay Added in ns ;
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 10.7              ;
+---------------------------------------------------------------+---------------------------------------------------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                           ;
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
; Source Register                                                                                                          ; Destination Register                                                                                                     ; Delay Added in ns ;
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; 0.579             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.430             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; 0.275             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; 0.263             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.182             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.182             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; 0.182             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.182             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.182             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; 0.182             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; 0.043             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; 0.025             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; 0.025             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; 0.025             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; 0.025             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; 0.025             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; 0.025             ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; 0.025             ;
+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+-------------------+
Note: This table only shows the top 33 path(s) that have the largest delay added for hold.


+-----------------+
; Fitter Messages ;
+-----------------+
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
Info (119006): Selected device EP4CE15F17C8 for design "max80"
Info (119018): Selected Migration Device List
    Info (119019): Selected EP4CE10F17C8 for migration
    Info (119019): Selected EP4CE6F17C8 for migration
Info (119021): Selected migration device list is legal with 166 total of migratable pins
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Warning (15536): Implemented PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type, but with warnings File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Warning (15567): Can't achieve requested High bandwidth type; current PLL requires a bandwidth value of greater than 2.000 Mhz -- achieved bandwidth of 1.03 MHz to 1.97 MHz File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Info (15099): Implementing clock multiplication of 3, clock division of 4, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
Info (15535): Implemented PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" as Cyclone IV E PLL type File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
    Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
    Info (15099): Implementing clock multiplication of 5, clock division of 1, and phase shift of -90 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
    Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of -18 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 630
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (165059): Selected device migration path cannot use 8 pins as differential receiver I/Os
    Info (165060): Pin M8
    Info (165060): Pin R12
    Info (165060): Pin T12
    Info (165060): Pin L11
    Info (165060): Pin L16
    Info (165060): Pin A12
    Info (165060): Pin F9
    Info (165060): Pin B5
Info (165059): Selected device migration path cannot use 9 pins as differential transmitter I/Os
    Info (165060): Pin M8
    Info (165060): Pin R12
    Info (165060): Pin T12
    Info (165060): Pin P14
    Info (165060): Pin L11
    Info (165060): Pin L16
    Info (165060): Pin A12
    Info (165060): Pin F9
    Info (165060): Pin B5
Info (169141): DATA[0] dual-purpose pin not reserved
Info (12825): Data[1]/ASDO dual-purpose pin not reserved
Info (12825): nCSO dual-purpose pin not reserved
Info (12825): DCLK dual-purpose pin not reserved
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
Warning (176674): Following 4 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
    Warning (176118): Pin "hdmi_d[0]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[0](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 109
    Warning (176118): Pin "hdmi_d[1]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[1](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 109
    Warning (176118): Pin "hdmi_d[2]" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_d[2](n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 109
    Warning (176118): Pin "hdmi_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "hdmi_clk(n)" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 110
Warning (15536): Implemented PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type, but with warnings File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Warning (15567): Can't achieve requested High bandwidth type; current PLL requires a bandwidth value of greater than 2.000 Mhz -- achieved bandwidth of 1.03 MHz to 1.97 MHz File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
    Info (15099): Implementing clock multiplication of 3, clock division of 4, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] port File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
Info (15535): Implemented PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" as Cyclone IV E PLL type File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
    Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
    Info (15099): Implementing clock multiplication of 5, clock division of 1, and phase shift of -90 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
    Info (15099): Implementing clock multiplication of 1, clock division of 1, and phase shift of -18 degrees (-1389 ps) for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] port File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 630
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity pll_altpll
        Info (332166): set_false_path -from ** -to *phasedone_state* 
        Info (332166): set_false_path -from ** -to *internal_phasestep* 
Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
    Info (332050): run_legacy_fitter_flow File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
    Info (332050): run_legacy_fitter_flow File: /opt/altera/20.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
Info (332104): Reading SDC File: 'max80.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[0]} {pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[1]} {pll|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 4 -multiply_by 3 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[2]} {pll|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -multiply_by 5 -phase -90.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]}
    Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -phase -18.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at max80.sdc(30): *|synchronizer:*|qreg0* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 30
Warning (332049): Ignored set_multicycle_path at max80.sdc(31): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
    Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
    -start -setup 2 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
Warning (332049): Ignored set_multicycle_path at max80.sdc(33): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
    Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
    -start -hold -1 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
Warning (332174): Ignored filter at max80.sdc(37): sld_signaltap:* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
Warning (332049): Ignored set_false_path at max80.sdc(37): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
    Info (332050): set_false_path -to [get_registers sld_signaltap:*] File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 8 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):   20.834     clock_48
    Info (332111):    5.555 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]
    Info (332111):   27.778 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]
    Info (332111):   10.417 pll|altpll_component|auto_generated|pll1|clk[0]
    Info (332111):   10.417 pll|altpll_component|auto_generated|pll1|clk[1]
    Info (332111):   27.778 pll|altpll_component|auto_generated|pll1|clk[2]
    Info (332111):   10.417        rst_n
    Info (332111): 30517.579    rtc_32khz
Info (176353): Automatically promoted node hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock (placed in counter C0 of PLL_1) File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 891
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info (176353): Automatically promoted node hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] (placed in counter C1 of PLL_1) File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 891
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C1 of PLL_2) File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 605
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
Info (176353): Automatically promoted node rst_n  File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 123
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node rst_ctr[11] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[10] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[9] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[8] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[7] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[6] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[5] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[4] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[3] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176357): Destination node rst_ctr[2] File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 148
        Info (176358): Non-global destination nodes limited to 10 nodes
Info (176233): Starting register packing
Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
Info (176235): Finished register packing
    Extra Info (176218): Packed 3 registers into blocks of type I/O Output Buffer
    Extra Info (176220): Created 3 register duplicates
Warning (15058): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
Warning (15064): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "sr_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance File: /home/hpa/abc80/max80/blinktest/db/pll_altpll.v Line: 491
Warning (15055): PLL "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
    Info (15024): Input port INCLK[0] of node "hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|lvds_tx_pll" is driven by pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]~clkctrl which is OUTCLK output port of Clock control block type node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]~clkctrl File: /home/hpa/abc80/max80/blinktest/db/hdmitx_lvds_tx.v Line: 633
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y20 to location X30_Y29
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
    Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
Info (169213): Configuration voltage level of 3.3V is enforced on the I/O bank 1. The VCCIO of the I/O bank 1 is set to 3.3V.
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning (169180): Following 1 pins must use external clamping diodes.
    Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
Warning (169177): 90 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin abc_clk uses I/O standard 3.3-V LVTTL at T8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 16
    Info (169178): Pin abc_a[0] uses I/O standard 3.3-V LVTTL at A8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[1] uses I/O standard 3.3-V LVTTL at B8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[2] uses I/O standard 3.3-V LVTTL at A9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[3] uses I/O standard 3.3-V LVTTL at D1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[4] uses I/O standard 3.3-V LVTTL at G5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[5] uses I/O standard 3.3-V LVTTL at F3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[6] uses I/O standard 3.3-V LVTTL at E1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[7] uses I/O standard 3.3-V LVTTL at F1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[8] uses I/O standard 3.3-V LVTTL at G1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[9] uses I/O standard 3.3-V LVTTL at J1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[10] uses I/O standard 3.3-V LVTTL at L4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[11] uses I/O standard 3.3-V LVTTL at K1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[12] uses I/O standard 3.3-V LVTTL at L1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[13] uses I/O standard 3.3-V LVTTL at M1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[14] uses I/O standard 3.3-V LVTTL at N2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_a[15] uses I/O standard 3.3-V LVTTL at N1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 17
    Info (169178): Pin abc_rst_n uses I/O standard 3.3-V LVTTL at P2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 20
    Info (169178): Pin abc_cs_n uses I/O standard 3.3-V LVTTL at F2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 21
    Info (169178): Pin abc_out_n[0] uses I/O standard 3.3-V LVTTL at G2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Info (169178): Pin abc_out_n[1] uses I/O standard 3.3-V LVTTL at J2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Info (169178): Pin abc_out_n[2] uses I/O standard 3.3-V LVTTL at K5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Info (169178): Pin abc_out_n[3] uses I/O standard 3.3-V LVTTL at L3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Info (169178): Pin abc_out_n[4] uses I/O standard 3.3-V LVTTL at K2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 22
    Info (169178): Pin abc_inp_n[0] uses I/O standard 3.3-V LVTTL at L2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
    Info (169178): Pin abc_inp_n[1] uses I/O standard 3.3-V LVTTL at M2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 23
    Info (169178): Pin abc_xmemfl_n uses I/O standard 3.3-V LVTTL at N3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 24
    Info (169178): Pin abc_xmemw800_n uses I/O standard 3.3-V LVTTL at P1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 25
    Info (169178): Pin abc_xmemw80_n uses I/O standard 3.3-V LVTTL at R1 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 26
    Info (169178): Pin abc_xinpstb_n uses I/O standard 3.3-V LVTTL at T12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 27
    Info (169178): Pin abc_xoutpstb_n uses I/O standard 3.3-V LVTTL at L10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 28
    Info (169178): Pin exth_hc uses I/O standard 3.3-V LVTTL at T9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 48
    Info (169178): Pin exth_hh uses I/O standard 3.3-V LVTTL at R8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 53
    Info (169178): Pin tty_txd uses I/O standard 3.3-V LVTTL at E16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 73
    Info (169178): Pin tty_rts uses I/O standard 3.3-V LVTTL at D16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 75
    Info (169178): Pin tty_dtr uses I/O standard 3.3-V LVTTL at P14 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 77
    Info (169178): Pin rtc_32khz uses I/O standard 3.3-V LVTTL at E15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 99
    Info (169178): Pin rtc_int_n uses I/O standard 3.3-V LVTTL at B16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 100
    Info (169178): Pin abc_d[0] uses I/O standard 3.3-V LVTTL at P3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169178): Pin abc_d[1] uses I/O standard 3.3-V LVTTL at M6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169178): Pin abc_d[2] uses I/O standard 3.3-V LVTTL at N5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169178): Pin abc_d[3] uses I/O standard 3.3-V LVTTL at T2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169178): Pin abc_d[4] uses I/O standard 3.3-V LVTTL at R3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169178): Pin abc_d[5] uses I/O standard 3.3-V LVTTL at T3 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169178): Pin abc_d[6] uses I/O standard 3.3-V LVTTL at R4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169178): Pin abc_d[7] uses I/O standard 3.3-V LVTTL at T4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169178): Pin hdmi_sda uses I/O standard 3.3-V LVTTL at R13 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
    Info (169178): Pin exth_ha uses I/O standard 3.3-V LVTTL at N12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
    Info (169178): Pin exth_hb uses I/O standard 3.3-V LVTTL at N9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
    Info (169178): Pin exth_hd uses I/O standard 3.3-V LVTTL at R11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
    Info (169178): Pin exth_he uses I/O standard 3.3-V LVTTL at R12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
    Info (169178): Pin exth_hf uses I/O standard 3.3-V LVTTL at T11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
    Info (169178): Pin exth_hg uses I/O standard 3.3-V LVTTL at N11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
    Info (169178): Pin sr_dq[0] uses I/O standard 3.3-V LVTTL at A12 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[1] uses I/O standard 3.3-V LVTTL at E11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[2] uses I/O standard 3.3-V LVTTL at D11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[3] uses I/O standard 3.3-V LVTTL at C11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[4] uses I/O standard 3.3-V LVTTL at B11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[5] uses I/O standard 3.3-V LVTTL at A11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[6] uses I/O standard 3.3-V LVTTL at B10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[7] uses I/O standard 3.3-V LVTTL at A10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[8] uses I/O standard 3.3-V LVTTL at A5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[9] uses I/O standard 3.3-V LVTTL at E7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[10] uses I/O standard 3.3-V LVTTL at B5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[11] uses I/O standard 3.3-V LVTTL at A4 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[12] uses I/O standard 3.3-V LVTTL at E6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[13] uses I/O standard 3.3-V LVTTL at D6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[14] uses I/O standard 3.3-V LVTTL at C6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sr_dq[15] uses I/O standard 3.3-V LVTTL at D5 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169178): Pin sd_dat[0] uses I/O standard 3.3-V LVTTL at F15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
    Info (169178): Pin sd_dat[1] uses I/O standard 3.3-V LVTTL at M10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
    Info (169178): Pin sd_dat[2] uses I/O standard 3.3-V LVTTL at F14 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
    Info (169178): Pin sd_dat[3] uses I/O standard 3.3-V LVTTL at F16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
    Info (169178): Pin spi_clk uses I/O standard 3.3-V LVTTL at P6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
    Info (169178): Pin spi_miso uses I/O standard 3.3-V LVTTL at M7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
    Info (169178): Pin spi_mosi uses I/O standard 3.3-V LVTTL at M8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 88
    Info (169178): Pin spi_cs_esp_n uses I/O standard 3.3-V LVTTL at N8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 89
    Info (169178): Pin spi_cs_flash_n uses I/O standard 3.3-V LVTTL at N6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 90
    Info (169178): Pin esp_io0 uses I/O standard 3.3-V LVTTL at L8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
    Info (169178): Pin esp_int uses I/O standard 3.3-V LVTTL at P8 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 94
    Info (169178): Pin i2c_scl uses I/O standard 3.3-V LVTTL at C16 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
    Info (169178): Pin i2c_sda uses I/O standard 3.3-V LVTTL at C15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
    Info (169178): Pin gpio[0] uses I/O standard 3.3-V LVTTL at L7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169178): Pin gpio[1] uses I/O standard 3.3-V LVTTL at P9 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169178): Pin gpio[2] uses I/O standard 3.3-V LVTTL at T6 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169178): Pin gpio[3] uses I/O standard 3.3-V LVTTL at R10 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169178): Pin gpio[4] uses I/O standard 3.3-V LVTTL at T7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169178): Pin gpio[5] uses I/O standard 3.3-V LVTTL at R7 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169178): Pin hdmi_scl uses I/O standard 3.3-V LVTTL at M11 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
    Info (169178): Pin hdmi_hpd uses I/O standard 3.3-V LVTTL at T15 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 114
Warning (169203): PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Intel FPGA requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Intel recommends termination method as specified in the Application Note 447.
    Info (169178): Pin flash_miso uses I/O standard 3.3-V LVTTL at H2 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 83
Warning (169064): Following 52 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
    Info (169065): Pin abc_d[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169065): Pin abc_d[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169065): Pin abc_d[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169065): Pin abc_d[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169065): Pin abc_d[4] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169065): Pin abc_d[5] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169065): Pin abc_d[6] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169065): Pin abc_d[7] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 18
    Info (169065): Pin hdmi_sda has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 112
    Info (169065): Pin exth_ha has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 46
    Info (169065): Pin exth_hb has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 47
    Info (169065): Pin exth_hd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 49
    Info (169065): Pin exth_he has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 50
    Info (169065): Pin exth_hf has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 51
    Info (169065): Pin exth_hg has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 52
    Info (169065): Pin sr_dq[0] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[1] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[2] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[3] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[4] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[5] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[6] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[7] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[8] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[9] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[10] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[11] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[12] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[13] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[14] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sr_dq[15] has a permanently enabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 60
    Info (169065): Pin sd_dat[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
    Info (169065): Pin sd_dat[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
    Info (169065): Pin sd_dat[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
    Info (169065): Pin sd_dat[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 70
    Info (169065): Pin spi_clk has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 86
    Info (169065): Pin spi_miso has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 87
    Info (169065): Pin spi_mosi has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 88
    Info (169065): Pin spi_cs_esp_n has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 89
    Info (169065): Pin spi_cs_flash_n has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 90
    Info (169065): Pin esp_io0 has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 93
    Info (169065): Pin esp_int has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 94
    Info (169065): Pin i2c_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 97
    Info (169065): Pin i2c_sda has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 98
    Info (169065): Pin gpio[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169065): Pin gpio[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169065): Pin gpio[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169065): Pin gpio[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169065): Pin gpio[4] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169065): Pin gpio[5] has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 106
    Info (169065): Pin hdmi_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 111
    Info (169065): Pin hdmi_hpd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 114
Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 29 warnings
    Info: Peak virtual memory: 1524 megabytes
    Info: Processing ended: Fri Aug  6 20:12:47 2021
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:07


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg.


+---------------------------------------------------------------+
; Assembler Summary                                             ;
+-----------------------+---------------------------------------+
; Assembler Status      ; Successful - Fri Aug  6 20:12:50 2021 ;
; Revision Name         ; max80                                 ;
; Top-level Entity Name ; max80                                 ;
; Family                ; Cyclone IV E                          ;
; Device                ; EP4CE15F17C8                          ;
+-----------------------+---------------------------------------+


+----------------------------------+
; Assembler Settings               ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+


+--------------------------------------------------------+
; Assembler Generated Files                              ;
+--------------------------------------------------------+
; File Name                                              ;
+--------------------------------------------------------+
; /home/hpa/abc80/max80/blinktest/output_files/max80.sof ;
; /home/hpa/abc80/max80/blinktest/output_files/max80.jam ;
; /home/hpa/abc80/max80/blinktest/output_files/max80.jbc ;
; /home/hpa/abc80/max80/blinktest/output_files/max80.pof ;
+--------------------------------------------------------+


+-------------------------------------+
; Assembler Device Options: max80.sof ;
+----------------+--------------------+
; Option         ; Setting            ;
+----------------+--------------------+
; JTAG usercode  ; 0x00111E47         ;
; Checksum       ; 0x00111E47         ;
+----------------+--------------------+


+-------------------------------------+
; Assembler Device Options: max80.jam ;
+-------------------------+-----------+
; Option                  ; Setting   ;
+-------------------------+-----------+
; JEDEC STAPL ASCII file  ;           ;
+-------------------------+-----------+


+-------------------------------------+
; Assembler Device Options: max80.jbc ;
+-----------------------+-------------+
; Option                ; Setting     ;
+-----------------------+-------------+
; STAPL Byte Code file  ;             ;
+-----------------------+-------------+


+-------------------------------------+
; Assembler Device Options: max80.pof ;
+--------------------+----------------+
; Option             ; Setting        ;
+--------------------+----------------+
; JTAG usercode      ; 0x00000000     ;
; Checksum           ; 0xFCE26A8B     ;
; Compression Ratio  ; 3              ;
+--------------------+----------------+


+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
    Info: Processing started: Fri Aug  6 20:12:48 2021
Info: Command: quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info (210117): Created JAM or JBC file for the specified chain: 
Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
Info (210117): Created JAM or JBC file for the specified chain: 
Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 569 megabytes
    Info: Processing ended: Fri Aug  6 20:12:50 2021
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 16          ;
; Maximum allowed            ; 8           ;
;                            ;             ;
; Average used               ; 1.04        ;
; Maximum used               ; 8           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-8         ;   0.6%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------+
; Power Analyzer Summary                                                                    ;
+----------------------------------------+--------------------------------------------------+
; Power Analyzer Status                  ; Successful - Fri Aug  6 20:12:54 2021            ;
; Quartus Prime Version                  ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition      ;
; Revision Name                          ; max80                                            ;
; Top-level Entity Name                  ; max80                                            ;
; Family                                 ; Cyclone IV E                                     ;
; Device                                 ; EP4CE15F17C8                                     ;
; Power Models                           ; Final                                            ;
; Total Thermal Power Dissipation        ; 217.59 mW                                        ;
; Core Dynamic Thermal Power Dissipation ; 37.20 mW                                         ;
; Core Static Thermal Power Dissipation  ; 60.20 mW                                         ;
; I/O Thermal Power Dissipation          ; 120.19 mW                                        ;
; Power Estimation Confidence            ; Low: user provided insufficient toggle rate data ;
+----------------------------------------+--------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Power Analyzer Settings                                                                                        ;
+------------------------------------------------------------------+-----------------------------+---------------+
; Option                                                           ; Setting                     ; Default Value ;
+------------------------------------------------------------------+-----------------------------+---------------+
; Use smart compilation                                            ; Off                         ; Off           ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On                          ; On            ;
; Enable compact report table                                      ; Off                         ; Off           ;
; Default Power Input I/O Toggle Rate                              ; 12.5%                       ; 12.5%         ;
; Preset Cooling Solution                                          ; No Heat Sink With Still Air ;               ;
; Board thermal model                                              ; None (CONSERVATIVE)         ;               ;
; VCCA voltage                                                     ; 2.5V                        ;               ;
; Default Power Toggle Rate                                        ; 12.5%                       ; 12.5%         ;
; Use vectorless estimation                                        ; On                          ; On            ;
; Use Input Files                                                  ; Off                         ; Off           ;
; Filter Glitches in VCD File Reader                               ; On                          ; On            ;
; Power Analyzer Report Signal Activity                            ; Off                         ; Off           ;
; Power Analyzer Report Power Dissipation                          ; Off                         ; Off           ;
; Device Power Characteristics                                     ; TYPICAL                     ; TYPICAL       ;
; Automatically Compute Junction Temperature                       ; On                          ; On            ;
; Specified Junction Temperature                                   ; 25                          ; 25            ;
; Ambient Temperature                                              ; 25                          ; 25            ;
; Use Custom Cooling Solution                                      ; Off                         ; Off           ;
; Board Temperature                                                ; 25                          ; 25            ;
+------------------------------------------------------------------+-----------------------------+---------------+


+----------------------------------------------+
; Indeterminate Toggle Rates                   ;
+----------------+-----------------------------+
; Node           ; Reason                      ;
+----------------+-----------------------------+
; abc_clk        ; No valid clock domain found ;
; abc_a[0]       ; No valid clock domain found ;
; abc_a[1]       ; No valid clock domain found ;
; abc_a[2]       ; No valid clock domain found ;
; abc_a[3]       ; No valid clock domain found ;
; abc_a[4]       ; No valid clock domain found ;
; abc_a[5]       ; No valid clock domain found ;
; abc_a[6]       ; No valid clock domain found ;
; abc_a[7]       ; No valid clock domain found ;
; abc_a[8]       ; No valid clock domain found ;
; abc_a[9]       ; No valid clock domain found ;
; abc_a[10]      ; No valid clock domain found ;
; abc_a[11]      ; No valid clock domain found ;
; abc_a[12]      ; No valid clock domain found ;
; abc_a[13]      ; No valid clock domain found ;
; abc_a[14]      ; No valid clock domain found ;
; abc_a[15]      ; No valid clock domain found ;
; abc_rst_n      ; No valid clock domain found ;
; abc_cs_n       ; No valid clock domain found ;
; abc_out_n[0]   ; No valid clock domain found ;
; abc_out_n[1]   ; No valid clock domain found ;
; abc_out_n[2]   ; No valid clock domain found ;
; abc_out_n[3]   ; No valid clock domain found ;
; abc_out_n[4]   ; No valid clock domain found ;
; abc_inp_n[0]   ; No valid clock domain found ;
; abc_inp_n[1]   ; No valid clock domain found ;
; abc_xmemfl_n   ; No valid clock domain found ;
; abc_xmemw800_n ; No valid clock domain found ;
; abc_xmemw80_n  ; No valid clock domain found ;
; abc_xinpstb_n  ; No valid clock domain found ;
; abc_xoutpstb_n ; No valid clock domain found ;
; exth_hc        ; No valid clock domain found ;
; exth_hh        ; No valid clock domain found ;
; tty_txd        ; No valid clock domain found ;
; tty_rts        ; No valid clock domain found ;
; tty_dtr        ; No valid clock domain found ;
; flash_miso     ; No valid clock domain found ;
; rtc_int_n      ; No valid clock domain found ;
; abc_d[0]       ; No valid clock domain found ;
; abc_d[1]       ; No valid clock domain found ;
; abc_d[2]       ; No valid clock domain found ;
; abc_d[3]       ; No valid clock domain found ;
; abc_d[4]       ; No valid clock domain found ;
; abc_d[5]       ; No valid clock domain found ;
; abc_d[6]       ; No valid clock domain found ;
; abc_d[7]       ; No valid clock domain found ;
; hdmi_sda       ; No valid clock domain found ;
; exth_ha        ; No valid clock domain found ;
; exth_hb        ; No valid clock domain found ;
; exth_hd        ; No valid clock domain found ;
; exth_he        ; No valid clock domain found ;
; exth_hf        ; No valid clock domain found ;
; exth_hg        ; No valid clock domain found ;
; sr_dq[0]       ; No valid clock domain found ;
; sr_dq[1]       ; No valid clock domain found ;
; sr_dq[2]       ; No valid clock domain found ;
; sr_dq[3]       ; No valid clock domain found ;
; sr_dq[4]       ; No valid clock domain found ;
; sr_dq[5]       ; No valid clock domain found ;
; sr_dq[6]       ; No valid clock domain found ;
; sr_dq[7]       ; No valid clock domain found ;
; sr_dq[8]       ; No valid clock domain found ;
; sr_dq[9]       ; No valid clock domain found ;
; sr_dq[10]      ; No valid clock domain found ;
; sr_dq[11]      ; No valid clock domain found ;
; sr_dq[12]      ; No valid clock domain found ;
; sr_dq[13]      ; No valid clock domain found ;
; sr_dq[14]      ; No valid clock domain found ;
; sr_dq[15]      ; No valid clock domain found ;
; sd_dat[0]      ; No valid clock domain found ;
; sd_dat[1]      ; No valid clock domain found ;
; sd_dat[2]      ; No valid clock domain found ;
; sd_dat[3]      ; No valid clock domain found ;
; spi_clk        ; No valid clock domain found ;
; spi_miso       ; No valid clock domain found ;
; spi_mosi       ; No valid clock domain found ;
; spi_cs_esp_n   ; No valid clock domain found ;
; spi_cs_flash_n ; No valid clock domain found ;
; esp_io0        ; No valid clock domain found ;
; esp_int        ; No valid clock domain found ;
; i2c_scl        ; No valid clock domain found ;
; i2c_sda        ; No valid clock domain found ;
; gpio[0]        ; No valid clock domain found ;
; gpio[1]        ; No valid clock domain found ;
; gpio[2]        ; No valid clock domain found ;
; gpio[3]        ; No valid clock domain found ;
; gpio[4]        ; No valid clock domain found ;
; gpio[5]        ; No valid clock domain found ;
; hdmi_scl       ; No valid clock domain found ;
; hdmi_hpd       ; No valid clock domain found ;
+----------------+-----------------------------+


+----------------------------------------------------------------------+
; Operating Conditions Used                                            ;
+-----------------------------------------+----------------------------+
; Setting                                 ; Value                      ;
+-----------------------------------------+----------------------------+
; Device power characteristics            ; Typical                    ;
;                                         ;                            ;
; Voltages                                ;                            ;
;     VCCINT                              ; 1.20 V                     ;
;     VCCA                                ; 2.50 V                     ;
;     VCCD                                ; 1.20 V                     ;
;     3.3-V LVTTL I/O Standard            ; 3.3 V                      ;
;     2.5 V I/O Standard                  ; 2.5 V                      ;
;     LVDS I/O Standard                   ; 2.5 V                      ;
;                                         ;                            ;
; Auto computed junction temperature      ; 31.4 degrees Celsius       ;
;     Ambient temperature                 ; 25.0 degrees Celsius       ;
;     Junction-to-Case thermal resistance ; 7.30 degrees Celsius/Watt  ;
;     Case-to-Ambient thermal resistance  ; 22.30 degrees Celsius/Watt ;
;                                         ;                            ;
; Board model used                        ; Typical                    ;
+-----------------------------------------+----------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Block                                                                                                           ;
+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ;
+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Block Type                                                                                                                                                                                              ;
+---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
; Block Type                            ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ;
+---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
; PLL                                   ; 22.56 mW                          ; 22.56 mW                    ; --                             ; 0.00 mW                       ;  111.003                                                  ;
; Combinational cell                    ; 0.41 mW                           ; 0.34 mW                     ; --                             ; 0.07 mW                       ;    7.976                                                  ;
; Clock control block                   ; 11.75 mW                          ; 0.00 mW                     ; --                             ; 11.75 mW                      ;  180.003                                                  ;
; Register cell                         ; 2.48 mW                           ; 1.87 mW                     ; --                             ; 0.61 mW                       ;   13.191                                                  ;
; Double Data Rate I/O Output Circuitry ; 0.49 mW                           ; 0.49 mW                     ; --                             ; 0.00 mW                       ;    0.000                                                  ;
; I/O register                          ; 0.21 mW                           ; 0.21 mW                     ; --                             ; 0.00 mW                       ;   12.000                                                  ;
; I/O                                   ; 93.12 mW                          ; 3.58 mW                     ; 89.55 mW                       ; 0.00 mW                       ;    2.266                                                  ;
+---------------------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Hierarchy                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                      ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name                                                                                                ;
+-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
; |max80                                                          ; 131.02 mW (96.32 mW)                 ; 29.05 mW (4.25 mW)              ; 89.55 mW (89.55 mW)               ; 12.43 mW (2.52 mW)                ; |max80                                                                                                             ;
;     |hard_block:auto_generated_inst                             ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hard_block:auto_generated_inst                                                                              ;
;     |tmdsenc:hdmitmds[0].enc                                    ; 0.16 mW (0.16 mW)                    ; 0.13 mW (0.13 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[0].enc                                                                                     ;
;     |tmdsenc:hdmitmds[1].enc                                    ; 0.14 mW (0.14 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|tmdsenc:hdmitmds[1].enc                                                                                     ;
;     |tmdsenc:hdmitmds[2].enc                                    ; 0.15 mW (0.15 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|tmdsenc:hdmitmds[2].enc                                                                                     ;
;     |transpose:hdmitranspose                                    ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|transpose:hdmitranspose                                                                                     ;
;     |hdmitx:hdmitx                                              ; 18.88 mW (0.00 mW)                   ; 13.23 mW (0.00 mW)              ; --                                ; 5.65 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx                                                                                               ;
;         |altlvds_tx:ALTLVDS_TX_component                        ; 18.88 mW (0.00 mW)                   ; 13.23 mW (0.00 mW)              ; --                                ; 5.65 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component                                                               ;
;             |hdmitx_lvds_tx:auto_generated                      ; 18.88 mW (17.24 mW)                  ; 13.23 mW (11.89 mW)             ; --                                ; 5.65 mW (5.35 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated                                 ;
;                 |hdmitx_cntr:cntr2                              ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2               ;
;                 |hdmitx_cntr:cntr13                             ; 0.10 mW (0.10 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13              ;
;                 |hdmitx_ddio_out:ddio_out                       ; 0.37 mW (0.37 mW)                    ; 0.37 mW (0.37 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out        ;
;                 |hdmitx_shift_reg:outclk_shift_h                ; 0.11 mW (0.11 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h ;
;                 |hdmitx_shift_reg:outclk_shift_l                ; 0.09 mW (0.09 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.02 mW (0.02 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l ;
;                 |hdmitx_ddio_out1:outclock_ddio                 ; 0.12 mW (0.12 mW)                    ; 0.12 mW (0.12 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio  ;
;                 |hdmitx_shift_reg1:shift_reg23                  ; 0.12 mW (0.12 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.03 mW (0.03 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23   ;
;                 |hdmitx_shift_reg1:shift_reg24                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24   ;
;                 |hdmitx_shift_reg1:shift_reg25                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25   ;
;                 |hdmitx_shift_reg1:shift_reg26                  ; 0.12 mW (0.12 mW)                    ; 0.08 mW (0.08 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26   ;
;                 |hdmitx_shift_reg1:shift_reg27                  ; 0.14 mW (0.14 mW)                    ; 0.10 mW (0.10 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27   ;
;                 |hdmitx_shift_reg1:shift_reg28                  ; 0.13 mW (0.13 mW)                    ; 0.09 mW (0.09 mW)               ; --                                ; 0.04 mW (0.04 mW)                 ; |max80|hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28   ;
;     |pll:pll                                                    ; 15.38 mW (0.00 mW)                   ; 11.21 mW (0.00 mW)              ; --                                ; 4.17 mW (0.00 mW)                 ; |max80|pll:pll                                                                                                     ;
;         |altpll:altpll_component                                ; 15.38 mW (0.00 mW)                   ; 11.21 mW (0.00 mW)              ; --                                ; 4.17 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component                                                                             ;
;             |pll_altpll:auto_generated                          ; 15.38 mW (15.38 mW)                  ; 11.21 mW (11.21 mW)             ; --                                ; 4.17 mW (4.17 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated                                                   ;
;                 |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2   ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2      ;
;                 |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4  ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4     ;
;                 |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5    ;
;                 |pll_cntr:phasestep_counter                     ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr:phasestep_counter                        ;
;                 |pll_cntr1:pll_internal_phasestep               ; 0.00 mW (0.00 mW)                    ; 0.00 mW (0.00 mW)               ; --                                ; 0.00 mW (0.00 mW)                 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_cntr1:pll_internal_phasestep                  ;
+-----------------------------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------------------------------------+
(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it.

(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Core Dynamic Thermal Power Dissipation by Clock Domain                                                                                                 ;
+-----------------------------------------------------------------------------------------------------+-----------------------+--------------------------+
; Clock Domain                                                                                        ; Clock Frequency (MHz) ; Total Core Dynamic Power ;
+-----------------------------------------------------------------------------------------------------+-----------------------+--------------------------+
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]                          ; 96.00                 ; 12.46                    ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1]                          ; 96.00                 ; 2.68                     ;
; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2]                          ; 36.00                 ; 1.39                     ;
; clock_48                                                                                            ; 48.00                 ; 0.00                     ;
; rst_n                                                                                               ; 96.00                 ; 2.49                     ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|fast_clock              ; 180.02                ; 18.12                    ;
; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|wire_lvds_tx_pll_clk[1] ; 36.00                 ; 0.75                     ;
; rtc_32khz                                                                                           ; 0.03                  ; 0.00                     ;
+-----------------------------------------------------------------------------------------------------+-----------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Current Drawn from Voltage Supplies Summary                                                                                        ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; VCCINT         ; 56.74 mA                ; 13.06 mA                  ; 43.69 mA                 ; 56.74 mA                         ;
; VCCIO          ; 28.27 mA                ; 1.01 mA                   ; 27.26 mA                 ; 28.27 mA                         ;
; VCCA           ; 21.83 mA                ; 3.55 mA                   ; 18.28 mA                 ; 21.83 mA                         ;
; VCCD           ; 19.19 mA                ; 11.40 mA                  ; 7.78 mA                  ; 19.19 mA                         ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.


+-----------------------------------------------------------------------------------------------+
; VCCIO Supply Current Drawn by I/O Bank                                                        ;
+----------+---------------+---------------------+-----------------------+----------------------+
; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ;
+----------+---------------+---------------------+-----------------------+----------------------+
; 1        ; 3.3V          ; 1.27 mA             ; 0.00 mA               ; 1.27 mA              ;
; 2        ; 3.3V          ; 1.31 mA             ; 0.00 mA               ; 1.31 mA              ;
; 3        ; 3.3V          ; 1.46 mA             ; 0.00 mA               ; 1.46 mA              ;
; 4        ; 3.3V          ; 1.53 mA             ; 0.15 mA               ; 1.38 mA              ;
; 5        ; 2.5V          ; 17.77 mA            ; 0.03 mA               ; 17.74 mA             ;
; 6        ; 3.3V          ; 1.25 mA             ; 0.00 mA               ; 1.25 mA              ;
; 7        ; 3.3V          ; 1.43 mA             ; 0.00 mA               ; 1.43 mA              ;
; 8        ; 3.3V          ; 2.25 mA             ; 0.82 mA               ; 1.43 mA              ;
+----------+---------------+---------------------+-----------------------+----------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; VCCIO Supply Current Drawn by Voltage                                                                                             ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; 2.5V          ; 17.77 mA                ; 0.03 mA                   ; 17.74 mA                 ; 17.77 mA                         ;
; 3.3V          ; 10.50 mA                ; 0.98 mA                   ; 9.53 mA                  ; 10.50 mA                         ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.  
(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Confidence Metric Details                                                                                                                        ;
+----------------------------------------------------------------------------------------+-------------+-------------+-------------+---------------+
; Data Source                                                                            ; Total       ; Pin         ; Registered  ; Combinational ;
+----------------------------------------------------------------------------------------+-------------+-------------+-------------+---------------+
; Simulation (from file)                                                                 ;             ;             ;             ;               ;
;     -- Number of signals with Toggle Rate from Simulation                              ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)      ;
;     -- Number of signals with Static Probability from Simulation                       ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)      ;
;                                                                                        ;             ;             ;             ;               ;
; Node, entity or clock assignment                                                       ;             ;             ;             ;               ;
;     -- Number of signals with Toggle Rate from Node, entity or clock assignment        ; 8 (0.9%)    ; 2 (1.0%)    ; 1 (0.5%)    ; 5 (1.0%)      ;
;     -- Number of signals with Static Probability from Node, entity or clock assignment ; 8 (0.9%)    ; 2 (1.0%)    ; 1 (0.5%)    ; 5 (1.0%)      ;
;                                                                                        ;             ;             ;             ;               ;
; Vectorless estimation                                                                  ;             ;             ;             ;               ;
;     -- Number of signals with Toggle Rate from Vectorless estimation                   ; 813 (89.2%) ; 103 (52.8%) ; 220 (99.5%) ; 490 (99.0%)   ;
;     -- Number of signals with Zero toggle rate, from Vectorless estimation             ; 214 (23.5%) ; 99 (50.8%)  ; 1 (0.5%)    ; 114 (23.0%)   ;
;     -- Number of signals with Static Probability from Vectorless estimation            ; 813 (89.2%) ; 103 (52.8%) ; 220 (99.5%) ; 490 (99.0%)   ;
;                                                                                        ;             ;             ;             ;               ;
; Default assignment                                                                     ;             ;             ;             ;               ;
;     -- Number of signals with Toggle Rate from Default assignment                      ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)    ; 0 (0.0%)      ;
;     -- Number of signals with Static Probability from Default assignment               ; 90 (9.9%)   ; 90 (46.2%)  ; 0 (0.0%)    ; 0 (0.0%)      ;
;                                                                                        ;             ;             ;             ;               ;
; Assumed 0                                                                              ;             ;             ;             ;               ;
;     -- Number of signals with Toggle Rate assumed 0                                    ; 90 (9.9%)   ; 90 (46.2%)  ; 0 (0.0%)    ; 0 (0.0%)      ;
+----------------------------------------------------------------------------------------+-------------+-------------+-------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Activities                                                                                                                           ;
+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ;
+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings".


+-------------------------+
; Power Analyzer Messages ;
+-------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Power Analyzer
    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
    Info: Processing started: Fri Aug  6 20:12:52 2021
Info: Command: quartus_pow --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity pll_altpll
        Info (332166): set_false_path -from ** -to *phasedone_state* 
        Info (332166): set_false_path -from ** -to *internal_phasestep* 
Warning (332173): Ignored filter: *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition
Warning (332048): Ignored set_false_path: Argument <to> is not an object ID
Warning (332173): Ignored filter: *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition
Warning (332048): Ignored set_false_path: Argument <to> is not an object ID
Info (332104): Reading SDC File: 'max80.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[0]} {pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[1]} {pll|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 4 -multiply_by 3 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[2]} {pll|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -multiply_by 5 -phase -90.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]}
    Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -phase -18.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at max80.sdc(30): *|synchronizer:*|qreg0* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 30
Warning (332049): Ignored set_multicycle_path at max80.sdc(31): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
    Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
    -start -setup 2 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
Warning (332049): Ignored set_multicycle_path at max80.sdc(33): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
    Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
    -start -hold -1 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
Warning (332174): Ignored filter at max80.sdc(37): sld_signaltap:* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
Warning (332049): Ignored set_false_path at max80.sdc(37): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
    Info (332050): set_false_path -to [get_registers sld_signaltap:*] File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info (223000): Starting Vectorless Power Activity Estimation
Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
Info (223001): Completed Vectorless Power Activity Estimation
Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (215049): Average toggle rate for this design is 10.833 millions of transitions / sec
Info (215031): Total thermal power estimate for the design is 217.59 mW
Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
    Info: Peak virtual memory: 1021 megabytes
    Info: Processing ended: Fri Aug  6 20:12:54 2021
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


----------------
; Legal Notice ;
----------------
Copyright (C) 2020  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+-----------------------------------------------------------------------------+
; Timing Analyzer Summary                                                     ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Timing Analyzer       ; Legacy Timing Analyzer                              ;
; Revision Name         ; max80                                               ;
; Device Family         ; Cyclone IV E                                        ;
; Device Name           ; EP4CE15F17C8                                        ;
; Timing Models         ; Final                                               ;
; Delay Model           ; Combined                                            ;
; Rise/Fall Delays      ; Enabled                                             ;
+-----------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 16          ;
; Maximum allowed            ; 8           ;
;                            ;             ;
; Average used               ; 1.05        ;
; Maximum used               ; 8           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   1.2%      ;
;     Processor 3            ;   0.7%      ;
;     Processors 4-8         ;   0.7%      ;
+----------------------------+-------------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; max80.sdc     ; OK     ; Fri Aug  6 20:12:55 2021 ;
+---------------+--------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                      ;
+---------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------+-----------------------------------------------------------------+-------------------------------------------------------------------+
; Clock Name                                                    ; Type      ; Period    ; Frequency  ; Rise   ; Fall      ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                          ; Source                                                          ; Targets                                                           ;
+---------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------+-----------------------------------------------------------------+-------------------------------------------------------------------+
; clock_48                                                      ; Base      ; 20.834    ; 48.0 MHz   ; 0.000  ; 10.417    ;            ;           ;             ;       ;        ;           ;            ;          ;                                                 ;                                                                 ; { clock_48 }                                                      ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; Generated ; 5.555     ; 180.02 MHz ; -1.388 ; 1.389     ; 50.00      ; 1         ; 5           ; -90.0 ;        ;           ;            ; false    ; pll|altpll_component|auto_generated|pll1|clk[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0] ; { hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] } ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; Generated ; 27.778    ; 36.0 MHz   ; -1.388 ; 12.501    ; 50.00      ; 1         ; 1           ; -18.0 ;        ;           ;            ; false    ; pll|altpll_component|auto_generated|pll1|clk[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0] ; { hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] } ;
; pll|altpll_component|auto_generated|pll1|clk[0]               ; Generated ; 10.417    ; 96.0 MHz   ; 0.000  ; 5.208     ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; clock_48                                        ; pll|altpll_component|auto_generated|pll1|inclk[0]               ; { pll|altpll_component|auto_generated|pll1|clk[0] }               ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; Generated ; 10.417    ; 96.0 MHz   ; 0.000  ; 5.208     ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; clock_48                                        ; pll|altpll_component|auto_generated|pll1|inclk[0]               ; { pll|altpll_component|auto_generated|pll1|clk[1] }               ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; Generated ; 27.778    ; 36.0 MHz   ; 0.000  ; 13.889    ; 50.00      ; 4         ; 3           ;       ;        ;           ;            ; false    ; clock_48                                        ; pll|altpll_component|auto_generated|pll1|inclk[0]               ; { pll|altpll_component|auto_generated|pll1|clk[2] }               ;
; rst_n                                                         ; Generated ; 10.417    ; 96.0 MHz   ; 0.000  ; 5.208     ;            ; 1         ; 1           ;       ;        ;           ;            ; false    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1]                 ; { rst_n }                                                         ;
; rtc_32khz                                                     ; Base      ; 30517.579 ; 0.03 MHz   ; 0.000  ; 15258.789 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                 ;                                                                 ; { rtc_32khz }                                                     ;
+---------------------------------------------------------------+-----------+-----------+------------+--------+-----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------+-----------------------------------------------------------------+-------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                  ;
+------------+-----------------+---------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                    ; Note ;
+------------+-----------------+---------------------------------------------------------------+------+
; 96.2 MHz   ; 96.2 MHz        ; pll|altpll_component|auto_generated|pll1|clk[2]               ;      ;
; 187.69 MHz ; 187.69 MHz      ; pll|altpll_component|auto_generated|pll1|clk[1]               ;      ;
; 274.05 MHz ; 274.05 MHz      ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ;      ;
; 341.88 MHz ; 341.88 MHz      ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ;      ;
+------------+-----------------+---------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+----------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                    ;
+---------------------------------------------------------------+--------+---------------+
; Clock                                                         ; Slack  ; End Point TNS ;
+---------------------------------------------------------------+--------+---------------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 1.906  ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 5.089  ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 17.383 ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 22.698 ; 0.000         ;
+---------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                    ;
+---------------------------------------------------------------+-------+---------------+
; Clock                                                         ; Slack ; End Point TNS ;
+---------------------------------------------------------------+-------+---------------+
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 0.466 ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.504 ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 0.576 ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 2.295 ; 0.000         ;
+---------------------------------------------------------------+-------+---------------+


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+-------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                         ;
+---------------------------------------------------------------+-----------+---------------+
; Clock                                                         ; Slack     ; End Point TNS ;
+---------------------------------------------------------------+-----------+---------------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 2.477     ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 4.909     ; 0.000         ;
; clock_48                                                      ; 10.341    ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 13.586    ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 13.589    ; 0.000         ;
; rtc_32khz                                                     ; 30513.579 ; 0.000         ;
+---------------------------------------------------------------+-----------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                             ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                ; To Node                                                                                                                      ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 1.906 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.118     ; 3.402      ;
; 1.985 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.124     ; 2.861      ;
; 1.998 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.190     ; 3.368      ;
; 2.020 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.117     ; 2.833      ;
; 2.042 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.190     ; 3.324      ;
; 2.046 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.190     ; 3.320      ;
; 2.101 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.115     ; 2.754      ;
; 2.242 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.226      ;
; 2.242 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.226      ;
; 2.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.215      ;
; 2.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.215      ;
; 2.278 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.190      ;
; 2.278 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.190      ;
; 2.278 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.190      ;
; 2.279 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.189      ;
; 2.280 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.188      ;
; 2.280 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.188      ;
; 2.281 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.187      ;
; 2.307 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 3.161      ;
; 2.368 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.190     ; 2.998      ;
; 2.412 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.190     ; 2.954      ;
; 2.412 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.190     ; 2.954      ;
; 2.478 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.118     ; 2.830      ;
; 2.509 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.855      ;
; 2.585 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.892      ;
; 2.621 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.088     ; 2.847      ;
; 2.629 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.848      ;
; 2.633 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.844      ;
; 2.702 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.775      ;
; 2.711 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.124     ; 2.591      ;
; 2.721 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.756      ;
; 2.723 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.754      ;
; 2.746 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.731      ;
; 2.746 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.731      ;
; 2.751 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.726      ;
; 2.767 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.710      ;
; 2.771 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.706      ;
; 2.818 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.659      ;
; 2.823 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.654      ;
; 2.846 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.631      ;
; 2.866 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFHI ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.108     ; 1.996      ;
; 2.895 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.582      ;
; 2.902 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.575      ;
; 2.925 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.550      ;
; 2.928 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.547      ;
; 2.932 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.545      ;
; 2.945 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.532      ;
; 3.026 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.338      ;
; 3.060 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.415      ;
; 3.082 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.393      ;
; 3.164 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.313      ;
; 3.166 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.311      ;
; 3.178 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFLO ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.108     ; 2.140      ;
; 3.196 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 2.281      ;
; 3.225 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.249      ;
; 3.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.221      ;
; 3.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.191     ; 2.112      ;
; 3.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.108      ;
; 3.267 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.208      ;
; 3.275 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.199      ;
; 3.279 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 2.195      ;
; 3.346 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.018      ;
; 3.346 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.018      ;
; 3.346 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.018      ;
; 3.346 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.018      ;
; 3.346 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.018      ;
; 3.346 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.018      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.125      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.014      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.014      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.014      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.014      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.014      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.014      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.014      ;
; 3.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.192     ; 2.014      ;
; 3.405 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 2.070      ;
; 3.435 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.932      ;
; 3.435 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.932      ;
; 3.435 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.932      ;
; 3.435 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.932      ;
; 3.435 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.932      ;
; 3.435 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.932      ;
; 3.487 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 1.988      ;
; 3.506 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 1.971      ;
; 3.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.852      ;
; 3.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.852      ;
; 3.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.852      ;
; 3.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.852      ;
; 3.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.852      ;
; 3.515 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.189     ; 1.852      ;
; 3.580 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 1.895      ;
; 3.581 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 1.894      ;
; 3.582 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 1.893      ;
; 3.584 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.185     ; 1.787      ;
; 3.588 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.079     ; 1.889      ;
; 3.595 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 1.879      ;
; 3.597 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.082     ; 1.877      ;
; 3.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 1.875      ;
; 3.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.081     ; 1.875      ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                           ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 5.089 ; led_ctr[1]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 5.119      ;
; 5.110 ; led_ctr[1]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 5.099      ;
; 5.183 ; led_ctr[2]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 5.026      ;
; 5.235 ; led_ctr[1]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.974      ;
; 5.279 ; led_ctr[0]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.930      ;
; 5.291 ; led_ctr[0]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.917      ;
; 5.328 ; led_ctr[4]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.881      ;
; 5.404 ; led_ctr[2]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.804      ;
; 5.423 ; led_ctr[3]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.786      ;
; 5.436 ; led_ctr[3]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.772      ;
; 5.437 ; led_ctr[0]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.772      ;
; 5.470 ; led_ctr[6]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.739      ;
; 5.549 ; led_ctr[4]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.659      ;
; 5.550 ; led_ctr[2]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.659      ;
; 5.561 ; led_ctr[5]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.648      ;
; 5.582 ; led_ctr[3]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.627      ;
; 5.585 ; led_ctr[5]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.623      ;
; 5.617 ; led_ctr[8]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.592      ;
; 5.691 ; led_ctr[6]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.517      ;
; 5.695 ; led_ctr[4]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.514      ;
; 5.714 ; led_ctr[7]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.495      ;
; 5.727 ; led_ctr[7]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.481      ;
; 5.731 ; led_ctr[5]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.478      ;
; 5.766 ; led_ctr[10]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.443      ;
; 5.837 ; led_ctr[6]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.372      ;
; 5.838 ; led_ctr[8]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.370      ;
; 5.861 ; led_ctr[9]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.348      ;
; 5.873 ; led_ctr[7]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.336      ;
; 5.874 ; led_ctr[9]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.334      ;
; 5.913 ; led_ctr[12]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.296      ;
; 5.984 ; led_ctr[8]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.225      ;
; 5.987 ; led_ctr[10]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.221      ;
; 6.007 ; led_ctr[11]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.202      ;
; 6.020 ; led_ctr[11]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.188      ;
; 6.020 ; led_ctr[9]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.189      ;
; 6.059 ; led_ctr[14]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.150      ;
; 6.133 ; led_ctr[10]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.076      ;
; 6.134 ; led_ctr[12]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.074      ;
; 6.154 ; led_ctr[13]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.055      ;
; 6.166 ; led_ctr[11]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.043      ;
; 6.167 ; led_ctr[13]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 4.041      ;
; 6.202 ; led_ctr[16]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 4.007      ;
; 6.280 ; led_ctr[14]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.928      ;
; 6.280 ; led_ctr[12]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.929      ;
; 6.300 ; led_ctr[15]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.909      ;
; 6.313 ; led_ctr[15]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.895      ;
; 6.313 ; led_ctr[13]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.896      ;
; 6.350 ; led_ctr[18]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.859      ;
; 6.414 ; led_ctr[1]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.925      ;
; 6.423 ; led_ctr[16]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.785      ;
; 6.426 ; led_ctr[14]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.783      ;
; 6.446 ; led_ctr[17]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.763      ;
; 6.458 ; led_ctr[17]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.750      ;
; 6.459 ; led_ctr[15]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.750      ;
; 6.496 ; led_ctr[20]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.713      ;
; 6.560 ; led_ctr[1]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.779      ;
; 6.569 ; led_ctr[16]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.640      ;
; 6.571 ; led_ctr[18]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.637      ;
; 6.578 ; led_ctr[1]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.761      ;
; 6.591 ; led_ctr[19]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.618      ;
; 6.603 ; led_ctr[19]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.605      ;
; 6.604 ; led_ctr[17]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.605      ;
; 6.616 ; led_ctr[0]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.723      ;
; 6.638 ; led_ctr[22]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.571      ;
; 6.651 ; led_ctr[2]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.688      ;
; 6.681 ; led_ctr[2]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.658      ;
; 6.706 ; led_ctr[1]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.633      ;
; 6.717 ; led_ctr[20]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.491      ;
; 6.717 ; led_ctr[18]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.492      ;
; 6.724 ; led_ctr[1]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.615      ;
; 6.728 ; led_ctr[21]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.481      ;
; 6.747 ; led_ctr[0]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.592      ;
; 6.749 ; led_ctr[19]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.460      ;
; 6.752 ; led_ctr[21]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.456      ;
; 6.761 ; led_ctr[3]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.578      ;
; 6.762 ; led_ctr[0]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.577      ;
; 6.764 ; rst_ctr[0]               ; rst_n                    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.080     ; 3.574      ;
; 6.784 ; led_ctr[24]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.425      ;
; 6.796 ; led_ctr[4]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.543      ;
; 6.797 ; led_ctr[2]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.542      ;
; 6.826 ; led_ctr[4]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.513      ;
; 6.827 ; led_ctr[2]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.512      ;
; 6.852 ; led_ctr[1]               ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.487      ;
; 6.859 ; led_ctr[22]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.349      ;
; 6.863 ; led_ctr[20]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.346      ;
; 6.870 ; led_ctr[1]               ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.469      ;
; 6.882 ; led_ctr[23]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.327      ;
; 6.891 ; led_ctr[3]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.448      ;
; 6.893 ; led_ctr[0]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.446      ;
; 6.895 ; led_ctr[23]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.077     ; 3.313      ;
; 6.898 ; led_ctr[21]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.311      ;
; 6.907 ; led_ctr[3]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.432      ;
; 6.908 ; led_ctr[0]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.431      ;
; 6.910 ; led_ctr[5]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.429      ;
; 6.933 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.076     ; 3.276      ;
; 6.938 ; led_ctr[6]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.401      ;
; 6.942 ; led_ctr[4]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.397      ;
; 6.943 ; led_ctr[2]               ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.396      ;
; 6.968 ; led_ctr[6]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.371      ;
; 6.972 ; led_ctr[4]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.079     ; 3.367      ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                             ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node     ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 17.383 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 10.312     ;
; 17.892 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 9.811      ;
; 17.922 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 9.781      ;
; 17.932 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 9.763      ;
; 18.008 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 9.700      ;
; 18.038 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 9.665      ;
; 18.038 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 9.670      ;
; 18.060 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 9.635      ;
; 18.068 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 9.635      ;
; 18.535 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 9.160      ;
; 18.604 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 9.104      ;
; 18.609 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 9.086      ;
; 18.634 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 9.074      ;
; 18.640 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 9.068      ;
; 18.670 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 9.038      ;
; 18.670 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 9.038      ;
; 18.700 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 8.996      ;
; 18.705 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.990      ;
; 18.717 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 8.979      ;
; 18.798 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 8.898      ;
; 18.801 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 8.895      ;
; 18.858 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.850      ;
; 18.888 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.820      ;
; 18.990 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.718      ;
; 19.004 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.691      ;
; 19.004 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.691      ;
; 19.020 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.688      ;
; 19.030 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.678      ;
; 19.060 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.648      ;
; 19.070 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.625      ;
; 19.081 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.627      ;
; 19.094 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 8.602      ;
; 19.111 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.597      ;
; 19.154 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 8.542      ;
; 19.186 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.509      ;
; 19.212 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.483      ;
; 19.266 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.442      ;
; 19.293 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.402      ;
; 19.302 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.406      ;
; 19.325 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.370      ;
; 19.382 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.313      ;
; 19.457 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.251      ;
; 19.475 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 8.221      ;
; 19.478 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 8.218      ;
; 19.487 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.221      ;
; 19.501 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 8.202      ;
; 19.520 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.188      ;
; 19.521 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 8.182      ;
; 19.561 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 8.142      ;
; 19.577 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 8.122      ;
; 19.617 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 8.082      ;
; 19.617 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 8.082      ;
; 19.647 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 8.056      ;
; 19.652 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.056      ;
; 19.667 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 8.036      ;
; 19.681 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.014      ;
; 19.681 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 8.014      ;
; 19.692 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 8.016      ;
; 19.735 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.960      ;
; 19.743 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 7.965      ;
; 19.747 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.948      ;
; 19.781 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.914      ;
; 19.831 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 7.865      ;
; 19.838 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.857      ;
; 19.840 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.855      ;
; 19.842 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.853      ;
; 19.850 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.853      ;
; 19.857 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.846      ;
; 19.874 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.821      ;
; 19.921 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.774      ;
; 19.927 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.776      ;
; 19.940 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.763      ;
; 19.954 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.749      ;
; 19.974 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.729      ;
; 19.983 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 7.716      ;
; 19.996 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.699      ;
; 20.073 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.630      ;
; 20.086 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.617      ;
; 20.092 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 7.616      ;
; 20.100 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.603      ;
; 20.119 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 7.589      ;
; 20.120 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.583      ;
; 20.157 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.546      ;
; 20.179 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 7.520      ;
; 20.182 ; dummydata[12] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.513      ;
; 20.193 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.510      ;
; 20.238 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 7.461      ;
; 20.254 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.441      ;
; 20.268 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 7.431      ;
; 20.294 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 7.402      ;
; 20.311 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.083     ; 7.385      ;
; 20.324 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.078     ; 7.377      ;
; 20.338 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.084     ; 7.357      ;
; 20.357 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 7.342      ;
; 20.358 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 7.341      ;
; 20.384 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.080     ; 7.315      ;
; 20.385 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.078     ; 7.316      ;
; 20.387 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.078     ; 7.314      ;
; 20.411 ; dummydata[20] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.292      ;
; 20.411 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.076     ; 7.292      ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                          ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 22.698 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.636     ; 1.957      ;
; 22.751 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.635     ; 1.905      ;
; 22.868 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.642     ; 1.781      ;
; 22.918 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.636     ; 1.737      ;
; 22.980 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.635     ; 1.676      ;
; 23.040 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.614      ;
; 23.093 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.561      ;
; 23.183 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.638     ; 1.470      ;
; 23.189 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.465      ;
; 23.203 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.451      ;
; 23.231 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.423      ;
; 23.232 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.422      ;
; 23.233 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.638     ; 1.420      ;
; 23.242 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.412      ;
; 23.246 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.408      ;
; 23.263 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.641     ; 1.387      ;
; 23.263 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.638     ; 1.390      ;
; 23.266 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.636     ; 1.389      ;
; 23.274 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.637     ; 1.380      ;
; 23.278 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.638     ; 1.375      ;
; 23.563 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.640     ; 1.088      ;
; 23.574 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.641     ; 1.076      ;
; 23.583 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.640     ; 1.068      ;
; 23.584 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.641     ; 1.066      ;
; 23.600 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.641     ; 1.050      ;
; 23.603 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.640     ; 1.048      ;
; 23.603 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.641     ; 1.047      ;
; 23.609 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.638     ; 1.044      ;
; 23.769 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.640     ; 0.882      ;
; 23.770 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.640     ; 0.881      ;
; 24.853 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 27.778       ; -0.080     ; 2.846      ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                            ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 0.466 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.758      ;
; 0.467 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.758      ;
; 0.736 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.027      ;
; 0.737 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
; 0.737 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
; 0.737 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
; 0.737 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
; 0.738 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
; 0.738 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
; 0.739 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
; 0.739 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
; 0.739 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
; 0.739 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
; 0.740 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; led_ctr[21]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; led_ctr[15]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; led_ctr[13]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
; 0.741 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
; 0.741 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
; 0.742 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
; 0.758 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.049      ;
; 0.758 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.050      ;
; 0.955 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.246      ;
; 0.986 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.278      ;
; 1.091 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.382      ;
; 1.092 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
; 1.092 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
; 1.092 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
; 1.092 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
; 1.092 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
; 1.092 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
; 1.093 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; led_ctr[10]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
; 1.093 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
; 1.094 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.385      ;
; 1.094 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.385      ;
; 1.100 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.392      ;
; 1.101 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
; 1.101 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
; 1.102 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
; 1.102 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
; 1.103 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
; 1.103 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
; 1.103 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
; 1.109 ; rst_ctr[5]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.401      ;
; 1.110 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
; 1.110 ; rst_ctr[1]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
; 1.111 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
; 1.111 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
; 1.112 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.403      ;
; 1.112 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.403      ;
; 1.222 ; led_ctr[14]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.513      ;
; 1.222 ; led_ctr[2]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.513      ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                          ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                ; To Node                                                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 0.504 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.795      ;
; 0.507 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.797      ;
; 0.510 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.800      ;
; 0.511 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.802      ;
; 0.511 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.801      ;
; 0.512 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.803      ;
; 0.512 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.803      ;
; 0.513 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.803      ;
; 0.545 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.836      ;
; 0.643 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.934      ;
; 0.643 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.934      ;
; 0.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.934      ;
; 0.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.934      ;
; 0.644 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.935      ;
; 0.645 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.935      ;
; 0.646 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.936      ;
; 0.646 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.936      ;
; 0.646 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.937      ;
; 0.646 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.937      ;
; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.938      ;
; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.939      ;
; 0.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.943      ;
; 0.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.943      ;
; 0.693 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.983      ;
; 0.694 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.984      ;
; 0.695 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.986      ;
; 0.697 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.988      ;
; 0.697 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.988      ;
; 0.698 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.988      ;
; 0.699 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.989      ;
; 0.700 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.990      ;
; 0.701 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.991      ;
; 0.701 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.991      ;
; 0.701 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.992      ;
; 0.702 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.993      ;
; 0.702 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.992      ;
; 0.703 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.994      ;
; 0.703 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 0.994      ;
; 0.708 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 0.998      ;
; 0.710 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.001      ;
; 0.713 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.004      ;
; 0.730 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.021      ;
; 0.731 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.022      ;
; 0.731 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.022      ;
; 0.732 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.023      ;
; 0.736 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.027      ;
; 0.738 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.763 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.053      ;
; 0.763 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.054      ;
; 0.764 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.054      ;
; 0.764 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.054      ;
; 0.764 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.054      ;
; 0.764 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.055      ;
; 0.765 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.055      ;
; 0.792 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.078      ; 1.082      ;
; 0.793 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.084      ;
; 0.798 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.089      ;
; 0.798 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.089      ;
; 0.799 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.090      ;
; 0.822 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.113      ;
; 0.860 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.281      ;
; 0.867 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.189      ; 1.285      ;
; 0.869 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.194      ; 1.292      ;
; 0.876 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.194      ; 1.299      ;
; 0.877 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.195      ; 1.301      ;
; 0.885 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.197      ; 1.311      ;
; 0.893 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.184      ;
; 0.915 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.194      ; 1.338      ;
; 0.925 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.346      ;
; 0.926 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.347      ;
; 0.965 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.191      ; 1.385      ;
; 0.974 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.191      ; 1.394      ;
; 0.974 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.191      ; 1.394      ;
; 0.995 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.416      ;
; 0.996 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.417      ;
; 0.997 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.191      ; 1.417      ;
; 0.999 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.191      ; 1.419      ;
; 1.000 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.291      ;
; 1.002 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.293      ;
; 1.004 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.425      ;
; 1.007 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.428      ;
; 1.011 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.191      ; 1.431      ;
; 1.023 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.444      ;
; 1.037 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.458      ;
; 1.037 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.191      ; 1.457      ;
; 1.042 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.079      ; 1.333      ;
; 1.048 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.076      ; 1.336      ;
; 1.050 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.076      ; 1.338      ;
; 1.051 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.191      ; 1.471      ;
; 1.060 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.077      ; 1.349      ;
; 1.060 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.077      ; 1.349      ;
; 1.060 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.481      ;
; 1.090 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.511      ;
; 1.098 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.192      ; 1.519      ;
; 1.106 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.077      ; 1.395      ;
; 1.110 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.194      ; 1.533      ;
; 1.137 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.076      ; 1.425      ;
; 1.137 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.194      ; 1.560      ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                    ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                            ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 0.576 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 0.868      ;
; 0.673 ; dummydata[21]                        ; dummydata[22]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 0.965      ;
; 0.673 ; dummydata[10]                        ; dummydata[11]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 0.965      ;
; 0.746 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.038      ;
; 0.748 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.039      ;
; 0.749 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.041      ;
; 0.750 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.042      ;
; 0.750 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.042      ;
; 0.757 ; dummydata[1]                         ; dummydata[2]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.048      ;
; 0.791 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.083      ;
; 0.793 ; dummydata[6]                         ; dummydata[7]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.084      ;
; 0.799 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.090      ;
; 0.807 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.099      ;
; 0.835 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.127      ;
; 0.852 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.144      ;
; 0.853 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.145      ;
; 0.860 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.152      ;
; 0.915 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.207      ;
; 0.915 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.207      ;
; 0.931 ; dummydata[22]                        ; dummydata[23]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.223      ;
; 0.933 ; dummydata[12]                        ; dummydata[13]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.225      ;
; 0.938 ; dummydata[7]                         ; dummydata[8]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.229      ;
; 0.944 ; dummydata[3]                         ; dummydata[4]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.235      ;
; 0.945 ; dummydata[11]                        ; dummydata[12]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.237      ;
; 0.947 ; dummydata[14]                        ; dummydata[15]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.239      ;
; 0.952 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.243      ;
; 0.985 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.277      ;
; 1.055 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.345      ;
; 1.068 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.358      ;
; 1.069 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.359      ;
; 1.098 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.389      ;
; 1.098 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.389      ;
; 1.098 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.389      ;
; 1.098 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.389      ;
; 1.101 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.393      ;
; 1.102 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.394      ;
; 1.102 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.394      ;
; 1.102 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.394      ;
; 1.109 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.401      ;
; 1.111 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.402      ;
; 1.111 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.403      ;
; 1.118 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.410      ;
; 1.119 ; dummydata[19]                        ; dummydata[20]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.076      ; 1.407      ;
; 1.120 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.412      ;
; 1.120 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.411      ;
; 1.121 ; dummydata[22]                        ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.413      ;
; 1.193 ; dummydata[9]                         ; dummydata[10]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.485      ;
; 1.207 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.499      ;
; 1.211 ; dummydata[4]                         ; dummydata[5]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.502      ;
; 1.222 ; dummydata[23]                        ; dummydata[0]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.514      ;
; 1.232 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.524      ;
; 1.233 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.525      ;
; 1.234 ; dummydata[21]                        ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.526      ;
; 1.241 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.533      ;
; 1.242 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.534      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.254 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.546      ;
; 1.258 ; dummydata[18]                        ; dummydata[19]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.084      ; 1.554      ;
; 1.305 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.596      ;
; 1.319 ; dummydata[15]                        ; dummydata[16]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.611      ;
; 1.339 ; dummydata[8]                         ; dummydata[9]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.086      ; 1.637      ;
; 1.341 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.631      ;
; 1.343 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.084      ; 1.639      ;
; 1.344 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.084      ; 1.640      ;
; 1.344 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.084      ; 1.640      ;
; 1.347 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.084      ; 1.643      ;
; 1.357 ; dummydata[0]                         ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.649      ;
; 1.361 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.651      ;
; 1.365 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.084      ; 1.661      ;
; 1.367 ; dummydata[9]                         ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.076      ; 1.655      ;
; 1.385 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.677      ;
; 1.392 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.683      ;
; 1.408 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.698      ;
; 1.408 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.078      ; 1.698      ;
; 1.410 ; dummydata[8]                         ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.702      ;
; 1.445 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.736      ;
; 1.455 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.747      ;
; 1.455 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.747      ;
; 1.457 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.749      ;
; 1.458 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.750      ;
; 1.460 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.752      ;
; 1.478 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.770      ;
; 1.479 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.086      ; 1.777      ;
; 1.479 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.086      ; 1.777      ;
; 1.479 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.086      ; 1.777      ;
; 1.479 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.086      ; 1.777      ;
; 1.528 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.080      ; 1.820      ;
; 1.538 ; dummydata[2]                         ; dummydata[3]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.079      ; 1.829      ;
; 1.540 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.084      ; 1.836      ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                          ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 2.295 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.000        ; 0.080      ; 2.587      ;
; 2.971 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.141     ; 0.794      ;
; 2.972 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.141     ; 0.795      ;
; 3.114 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.141     ; 0.937      ;
; 3.147 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.140     ; 0.971      ;
; 3.156 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.140     ; 0.980      ;
; 3.159 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 0.985      ;
; 3.165 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.140     ; 0.989      ;
; 3.176 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.140     ; 1.000      ;
; 3.180 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.140     ; 1.004      ;
; 3.188 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.140     ; 1.012      ;
; 3.452 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.140     ; 1.276      ;
; 3.461 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 1.287      ;
; 3.478 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 1.304      ;
; 3.489 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.136     ; 1.317      ;
; 3.490 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 1.316      ;
; 3.493 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.136     ; 1.321      ;
; 3.493 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 1.319      ;
; 3.493 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.139     ; 1.318      ;
; 3.508 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.137     ; 1.335      ;
; 3.520 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 1.346      ;
; 3.528 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.137     ; 1.355      ;
; 3.530 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 1.356      ;
; 3.542 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.137     ; 1.369      ;
; 3.681 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.138     ; 1.507      ;
; 3.712 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.137     ; 1.539      ;
; 3.729 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.136     ; 1.557      ;
; 3.805 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.136     ; 1.633      ;
; 3.809 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.141     ; 1.632      ;
; 3.975 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.135     ; 1.804      ;
; 4.013 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.136     ; 1.841      ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                   ;
+------------+-----------------+---------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                    ; Note ;
+------------+-----------------+---------------------------------------------------------------+------+
; 101.61 MHz ; 101.61 MHz      ; pll|altpll_component|auto_generated|pll1|clk[2]               ;      ;
; 205.72 MHz ; 205.72 MHz      ; pll|altpll_component|auto_generated|pll1|clk[1]               ;      ;
; 287.6 MHz  ; 287.6 MHz       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ;      ;
; 373.41 MHz ; 373.41 MHz      ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ;      ;
+------------+-----------------+---------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+----------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                     ;
+---------------------------------------------------------------+--------+---------------+
; Clock                                                         ; Slack  ; End Point TNS ;
+---------------------------------------------------------------+--------+---------------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 2.078  ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 5.556  ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 17.936 ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 22.985 ; 0.000         ;
+---------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                     ;
+---------------------------------------------------------------+-------+---------------+
; Clock                                                         ; Slack ; End Point TNS ;
+---------------------------------------------------------------+-------+---------------+
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 0.418 ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.473 ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 0.537 ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 2.143 ; 0.000         ;
+---------------------------------------------------------------+-------+---------------+


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+-------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                          ;
+---------------------------------------------------------------+-----------+---------------+
; Clock                                                         ; Slack     ; End Point TNS ;
+---------------------------------------------------------------+-----------+---------------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 2.476     ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 4.909     ; 0.000         ;
; clock_48                                                      ; 10.354    ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 13.586    ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 13.588    ; 0.000         ;
; rtc_32khz                                                     ; 30513.579 ; 0.000         ;
+---------------------------------------------------------------+-----------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                              ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                ; To Node                                                                                                                      ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 2.078 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.103     ; 3.250      ;
; 2.212 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.105     ; 2.705      ;
; 2.241 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.110     ; 2.671      ;
; 2.259 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 3.131      ;
; 2.304 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.101     ; 2.617      ;
; 2.307 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 3.083      ;
; 2.311 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 3.079      ;
; 2.400 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.081      ;
; 2.400 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.081      ;
; 2.407 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.074      ;
; 2.407 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.074      ;
; 2.426 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.055      ;
; 2.426 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.055      ;
; 2.426 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.055      ;
; 2.427 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.054      ;
; 2.428 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.053      ;
; 2.429 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.052      ;
; 2.430 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.051      ;
; 2.461 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 3.020      ;
; 2.667 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 2.723      ;
; 2.669 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.105     ; 2.657      ;
; 2.672 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 2.716      ;
; 2.707 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 2.683      ;
; 2.707 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 2.683      ;
; 2.742 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.076     ; 2.739      ;
; 2.856 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.630      ;
; 2.856 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.110     ; 2.465      ;
; 2.904 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.582      ;
; 2.908 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.578      ;
; 2.959 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.527      ;
; 2.975 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.511      ;
; 2.999 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.487      ;
; 3.000 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.486      ;
; 3.017 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.469      ;
; 3.021 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.465      ;
; 3.023 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.463      ;
; 3.027 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.459      ;
; 3.034 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFHI ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.097     ; 1.891      ;
; 3.084 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.402      ;
; 3.104 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.380      ;
; 3.107 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.377      ;
; 3.108 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.378      ;
; 3.112 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.374      ;
; 3.142 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.344      ;
; 3.154 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.332      ;
; 3.157 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 2.231      ;
; 3.176 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.310      ;
; 3.210 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.071     ; 2.276      ;
; 3.235 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.249      ;
; 3.252 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.232      ;
; 3.299 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFLO ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.097     ; 2.035      ;
; 3.318 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.169      ;
; 3.322 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.165      ;
; 3.361 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.123      ;
; 3.369 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 2.118      ;
; 3.372 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 2.016      ;
; 3.392 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.998      ;
; 3.397 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.087      ;
; 3.401 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.083      ;
; 3.403 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.081      ;
; 3.406 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 2.078      ;
; 3.485 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.999      ;
; 3.485 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.903      ;
; 3.485 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.903      ;
; 3.485 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.903      ;
; 3.485 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.903      ;
; 3.485 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.903      ;
; 3.485 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.903      ;
; 3.491 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.897      ;
; 3.491 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.897      ;
; 3.491 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.897      ;
; 3.491 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.897      ;
; 3.491 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.897      ;
; 3.491 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.897      ;
; 3.491 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.897      ;
; 3.491 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.169     ; 1.897      ;
; 3.537 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.947      ;
; 3.556 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.834      ;
; 3.556 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.834      ;
; 3.556 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.834      ;
; 3.556 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.834      ;
; 3.556 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.834      ;
; 3.556 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.834      ;
; 3.615 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.869      ;
; 3.622 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 1.865      ;
; 3.637 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.753      ;
; 3.637 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.753      ;
; 3.637 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.753      ;
; 3.637 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.753      ;
; 3.637 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.753      ;
; 3.637 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.167     ; 1.753      ;
; 3.673 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.162     ; 1.722      ;
; 3.693 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.791      ;
; 3.696 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.788      ;
; 3.699 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.070     ; 1.788      ;
; 3.708 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.776      ;
; 3.709 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.775      ;
; 3.710 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.774      ;
; 3.711 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.164     ; 1.682      ;
; 3.728 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.073     ; 1.756      ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                            ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 5.556 ; led_ctr[1]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 4.662      ;
; 5.630 ; led_ctr[1]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.590      ;
; 5.690 ; led_ctr[2]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.530      ;
; 5.720 ; led_ctr[1]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.500      ;
; 5.759 ; led_ctr[0]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 4.459      ;
; 5.777 ; led_ctr[0]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.443      ;
; 5.816 ; led_ctr[4]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.404      ;
; 5.883 ; led_ctr[2]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 4.335      ;
; 5.884 ; led_ctr[3]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 4.334      ;
; 5.902 ; led_ctr[3]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.318      ;
; 5.923 ; led_ctr[0]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.297      ;
; 5.937 ; led_ctr[6]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.283      ;
; 6.009 ; led_ctr[4]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 4.209      ;
; 6.014 ; led_ctr[5]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 4.204      ;
; 6.020 ; led_ctr[5]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.200      ;
; 6.047 ; led_ctr[2]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.173      ;
; 6.048 ; led_ctr[3]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.172      ;
; 6.063 ; led_ctr[8]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.157      ;
; 6.130 ; led_ctr[6]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 4.088      ;
; 6.135 ; led_ctr[7]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 4.083      ;
; 6.153 ; led_ctr[7]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.067      ;
; 6.173 ; led_ctr[4]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.047      ;
; 6.178 ; led_ctr[5]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.042      ;
; 6.193 ; led_ctr[10]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 4.027      ;
; 6.256 ; led_ctr[8]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 3.962      ;
; 6.262 ; led_ctr[9]               ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 3.956      ;
; 6.279 ; led_ctr[9]               ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.941      ;
; 6.294 ; led_ctr[6]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.926      ;
; 6.299 ; led_ctr[7]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.921      ;
; 6.320 ; led_ctr[12]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.900      ;
; 6.386 ; led_ctr[10]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 3.832      ;
; 6.388 ; led_ctr[11]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 3.830      ;
; 6.406 ; led_ctr[11]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.814      ;
; 6.420 ; led_ctr[8]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.800      ;
; 6.426 ; led_ctr[9]               ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.794      ;
; 6.447 ; led_ctr[14]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.773      ;
; 6.513 ; led_ctr[12]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 3.705      ;
; 6.515 ; led_ctr[13]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 3.703      ;
; 6.533 ; led_ctr[13]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.687      ;
; 6.550 ; led_ctr[10]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.670      ;
; 6.552 ; led_ctr[11]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.668      ;
; 6.568 ; led_ctr[16]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.651      ;
; 6.640 ; led_ctr[15]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.577      ;
; 6.640 ; led_ctr[14]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.074     ; 3.578      ;
; 6.658 ; led_ctr[15]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.561      ;
; 6.677 ; led_ctr[12]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.543      ;
; 6.679 ; led_ctr[13]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.541      ;
; 6.696 ; led_ctr[18]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.523      ;
; 6.761 ; led_ctr[16]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.456      ;
; 6.765 ; led_ctr[17]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.452      ;
; 6.783 ; led_ctr[17]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.436      ;
; 6.804 ; led_ctr[15]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.415      ;
; 6.804 ; led_ctr[14]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.072     ; 3.416      ;
; 6.822 ; led_ctr[20]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.397      ;
; 6.841 ; led_ctr[1]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.508      ;
; 6.889 ; led_ctr[18]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.328      ;
; 6.890 ; led_ctr[19]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.327      ;
; 6.908 ; led_ctr[19]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.311      ;
; 6.925 ; led_ctr[16]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.294      ;
; 6.929 ; led_ctr[17]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.290      ;
; 6.943 ; led_ctr[22]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.276      ;
; 6.967 ; led_ctr[1]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.382      ;
; 7.006 ; led_ctr[1]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.343      ;
; 7.015 ; led_ctr[20]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.202      ;
; 7.021 ; led_ctr[21]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.196      ;
; 7.027 ; led_ctr[21]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.192      ;
; 7.044 ; led_ctr[0]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.305      ;
; 7.053 ; led_ctr[18]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.166      ;
; 7.054 ; led_ctr[19]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.165      ;
; 7.070 ; led_ctr[24]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.149      ;
; 7.072 ; rst_ctr[0]               ; rst_n                    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.071     ; 3.276      ;
; 7.093 ; led_ctr[1]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.256      ;
; 7.095 ; led_ctr[2]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.254      ;
; 7.132 ; led_ctr[1]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.217      ;
; 7.134 ; led_ctr[2]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.215      ;
; 7.136 ; led_ctr[22]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.081      ;
; 7.142 ; led_ctr[23]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 3.075      ;
; 7.159 ; led_ctr[23]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.060      ;
; 7.169 ; led_ctr[3]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.180      ;
; 7.170 ; led_ctr[0]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.179      ;
; 7.179 ; led_ctr[20]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.040      ;
; 7.182 ; led_ctr[0]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.167      ;
; 7.185 ; led_ctr[21]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.034      ;
; 7.199 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 3.020      ;
; 7.219 ; led_ctr[1]               ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.130      ;
; 7.221 ; led_ctr[4]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.128      ;
; 7.221 ; led_ctr[2]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.128      ;
; 7.258 ; led_ctr[1]               ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.091      ;
; 7.260 ; led_ctr[4]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.089      ;
; 7.260 ; led_ctr[2]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.089      ;
; 7.263 ; led_ctr[24]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 2.954      ;
; 7.268 ; led_ctr[25]              ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.075     ; 2.949      ;
; 7.286 ; led_ctr[25]              ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 2.933      ;
; 7.295 ; led_ctr[3]               ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.054      ;
; 7.296 ; led_ctr[0]               ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.053      ;
; 7.299 ; led_ctr[5]               ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.050      ;
; 7.300 ; led_ctr[22]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 2.919      ;
; 7.306 ; led_ctr[23]              ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.073     ; 2.913      ;
; 7.307 ; led_ctr[3]               ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.042      ;
; 7.308 ; led_ctr[0]               ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.070     ; 3.041      ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                              ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node     ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 17.936 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 9.771      ;
; 18.388 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 9.319      ;
; 18.466 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 9.251      ;
; 18.505 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 9.212      ;
; 18.569 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 9.142      ;
; 18.597 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 9.110      ;
; 18.652 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 9.059      ;
; 18.695 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 9.016      ;
; 18.778 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 8.933      ;
; 18.955 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 8.752      ;
; 19.049 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 8.658      ;
; 19.051 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.666      ;
; 19.108 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.609      ;
; 19.131 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 8.576      ;
; 19.137 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.072     ; 8.571      ;
; 19.139 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.072     ; 8.569      ;
; 19.147 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.570      ;
; 19.161 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.074     ; 8.545      ;
; 19.176 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.074     ; 8.530      ;
; 19.183 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.534      ;
; 19.222 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.495      ;
; 19.340 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.377      ;
; 19.379 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.338      ;
; 19.400 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 8.307      ;
; 19.400 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 8.307      ;
; 19.447 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 8.260      ;
; 19.469 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.072     ; 8.239      ;
; 19.508 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.209      ;
; 19.530 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.074     ; 8.176      ;
; 19.536 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.181      ;
; 19.547 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.170      ;
; 19.575 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.142      ;
; 19.578 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.139      ;
; 19.616 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 8.091      ;
; 19.617 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.100      ;
; 19.693 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 8.024      ;
; 19.716 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.991      ;
; 19.768 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.949      ;
; 19.792 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.915      ;
; 19.798 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.072     ; 7.910      ;
; 19.800 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.072     ; 7.908      ;
; 19.815 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.892      ;
; 19.878 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.066     ; 7.836      ;
; 19.893 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.814      ;
; 19.925 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.792      ;
; 19.953 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.764      ;
; 19.992 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.725      ;
; 20.022 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 7.687      ;
; 20.027 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.684      ;
; 20.038 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 7.671      ;
; 20.039 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 7.670      ;
; 20.061 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.646      ;
; 20.061 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.646      ;
; 20.081 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.630      ;
; 20.086 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.621      ;
; 20.093 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.624      ;
; 20.108 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.599      ;
; 20.121 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.596      ;
; 20.130 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.072     ; 7.578      ;
; 20.138 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.066     ; 7.576      ;
; 20.149 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.066     ; 7.565      ;
; 20.151 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.556      ;
; 20.153 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.558      ;
; 20.163 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.554      ;
; 20.168 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.539      ;
; 20.172 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.535      ;
; 20.207 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.504      ;
; 20.267 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.440      ;
; 20.322 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.385      ;
; 20.345 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.362      ;
; 20.394 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 7.315      ;
; 20.440 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 7.267      ;
; 20.485 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.226      ;
; 20.520 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.066     ; 7.194      ;
; 20.538 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.179      ;
; 20.539 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.172      ;
; 20.540 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.171      ;
; 20.583 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 7.126      ;
; 20.594 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.117      ;
; 20.595 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.066     ; 7.119      ;
; 20.611 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.100      ;
; 20.619 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.074     ; 7.087      ;
; 20.624 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.063     ; 7.093      ;
; 20.631 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.068     ; 7.081      ;
; 20.634 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.074     ; 7.072      ;
; 20.665 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.046      ;
; 20.666 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 7.045      ;
; 20.687 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.068     ; 7.025      ;
; 20.689 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.068     ; 7.023      ;
; 20.720 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.069     ; 6.991      ;
; 20.735 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 6.972      ;
; 20.736 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 6.973      ;
; 20.737 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.071     ; 6.972      ;
; 20.747 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 6.960      ;
; 20.748 ; dummydata[12] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 6.959      ;
; 20.752 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.066     ; 6.962      ;
; 20.780 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.066     ; 6.934      ;
; 20.791 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.066     ; 6.923      ;
; 20.799 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 6.908      ;
; 20.812 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.073     ; 6.895      ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                           ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 22.985 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.445     ; 1.862      ;
; 23.035 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.445     ; 1.812      ;
; 23.136 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 1.707      ;
; 23.188 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.445     ; 1.659      ;
; 23.235 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.445     ; 1.612      ;
; 23.309 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.536      ;
; 23.367 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.478      ;
; 23.439 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.406      ;
; 23.442 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.403      ;
; 23.460 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.446     ; 1.386      ;
; 23.482 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.446     ; 1.364      ;
; 23.484 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.361      ;
; 23.492 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.353      ;
; 23.502 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.343      ;
; 23.504 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.446     ; 1.342      ;
; 23.522 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 1.321      ;
; 23.522 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.323      ;
; 23.524 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.321      ;
; 23.536 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.444     ; 1.312      ;
; 23.542 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 1.303      ;
; 23.828 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 1.015      ;
; 23.833 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.448     ; 1.011      ;
; 23.842 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 1.001      ;
; 23.852 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.448     ; 0.992      ;
; 23.856 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.447     ; 0.989      ;
; 23.868 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 0.975      ;
; 23.874 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 0.969      ;
; 23.875 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 0.968      ;
; 24.047 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 0.796      ;
; 24.048 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -1.449     ; 0.795      ;
; 25.100 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 27.778       ; -0.071     ; 2.609      ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                             ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 0.418 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.684      ;
; 0.419 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.684      ;
; 0.685 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.951      ;
; 0.685 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.950      ;
; 0.685 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.950      ;
; 0.685 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.950      ;
; 0.686 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.952      ;
; 0.686 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.952      ;
; 0.686 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.952      ;
; 0.686 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.951      ;
; 0.686 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.951      ;
; 0.687 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.953      ;
; 0.688 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688 ; led_ctr[21]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.953      ;
; 0.689 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; led_ctr[15]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.954      ;
; 0.689 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.954      ;
; 0.690 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.956      ;
; 0.691 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; led_ctr[13]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.956      ;
; 0.691 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.956      ;
; 0.691 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.956      ;
; 0.692 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.957      ;
; 0.692 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.957      ;
; 0.709 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.975      ;
; 0.709 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 0.974      ;
; 0.851 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.116      ;
; 0.875 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.141      ;
; 1.006 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.272      ;
; 1.006 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.272      ;
; 1.007 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
; 1.007 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
; 1.007 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
; 1.007 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
; 1.007 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.272      ;
; 1.008 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.273      ;
; 1.008 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.273      ;
; 1.008 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.273      ;
; 1.008 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; led_ctr[10]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.273      ;
; 1.009 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
; 1.009 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
; 1.009 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
; 1.009 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.274      ;
; 1.009 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.275      ;
; 1.009 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.274      ;
; 1.011 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.277      ;
; 1.012 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.278      ;
; 1.013 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.279      ;
; 1.013 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.278      ;
; 1.013 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.278      ;
; 1.022 ; rst_ctr[5]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.288      ;
; 1.022 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.288      ;
; 1.022 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.287      ;
; 1.023 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.289      ;
; 1.024 ; rst_ctr[1]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.290      ;
; 1.024 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.290      ;
; 1.024 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.290      ;
; 1.024 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.289      ;
; 1.025 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.291      ;
; 1.025 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.291      ;
; 1.025 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.290      ;
; 1.025 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.290      ;
; 1.026 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
; 1.026 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
; 1.026 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
; 1.026 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.291      ;
; 1.026 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.292      ;
; 1.026 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.070      ; 1.291      ;
; 1.098 ; led_ctr[14]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.364      ;
; 1.099 ; led_ctr[18]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 1.365      ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                ; To Node                                                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 0.473 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.738      ;
; 0.474 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.740      ;
; 0.476 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.742      ;
; 0.480 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.745      ;
; 0.480 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.746      ;
; 0.480 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.746      ;
; 0.481 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.746      ;
; 0.482 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.747      ;
; 0.507 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.772      ;
; 0.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.865      ;
; 0.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.866      ;
; 0.600 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.866      ;
; 0.601 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.866      ;
; 0.601 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.866      ;
; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.867      ;
; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.867      ;
; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.867      ;
; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.868      ;
; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.868      ;
; 0.602 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.868      ;
; 0.603 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.869      ;
; 0.603 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.868      ;
; 0.604 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.869      ;
; 0.609 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.874      ;
; 0.610 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.875      ;
; 0.614 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.880      ;
; 0.616 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.881      ;
; 0.618 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.884      ;
; 0.619 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.885      ;
; 0.620 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.886      ;
; 0.621 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.887      ;
; 0.621 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.887      ;
; 0.622 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.888      ;
; 0.626 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.892      ;
; 0.630 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.895      ;
; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.913      ;
; 0.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.913      ;
; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.914      ;
; 0.648 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.913      ;
; 0.650 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.915      ;
; 0.651 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.916      ;
; 0.652 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.918      ;
; 0.652 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.918      ;
; 0.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.919      ;
; 0.655 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.921      ;
; 0.656 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.922      ;
; 0.657 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.922      ;
; 0.658 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.923      ;
; 0.658 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.923      ;
; 0.713 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.978      ;
; 0.713 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.979      ;
; 0.715 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.980      ;
; 0.715 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.980      ;
; 0.715 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.980      ;
; 0.715 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 0.980      ;
; 0.715 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 0.981      ;
; 0.735 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.001      ;
; 0.737 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.003      ;
; 0.744 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.009      ;
; 0.744 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.009      ;
; 0.745 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.010      ;
; 0.765 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.170      ; 1.147      ;
; 0.770 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.035      ;
; 0.772 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.166      ; 1.150      ;
; 0.775 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.171      ; 1.158      ;
; 0.778 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.171      ; 1.161      ;
; 0.782 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.172      ; 1.166      ;
; 0.788 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.173      ; 1.173      ;
; 0.816 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.071      ; 1.082      ;
; 0.817 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.171      ; 1.200      ;
; 0.822 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.203      ;
; 0.823 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.204      ;
; 0.854 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.235      ;
; 0.863 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.244      ;
; 0.868 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.249      ;
; 0.887 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.268      ;
; 0.888 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.269      ;
; 0.890 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.155      ;
; 0.891 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.272      ;
; 0.892 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.273      ;
; 0.894 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.275      ;
; 0.900 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.281      ;
; 0.903 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.168      ;
; 0.904 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.285      ;
; 0.917 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.298      ;
; 0.927 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.308      ;
; 0.928 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.309      ;
; 0.935 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.198      ;
; 0.936 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.317      ;
; 0.937 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.200      ;
; 0.944 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.207      ;
; 0.944 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.207      ;
; 0.944 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.070      ; 1.209      ;
; 0.944 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.325      ;
; 0.966 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.347      ;
; 0.974 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.169      ; 1.355      ;
; 0.983 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.068      ; 1.246      ;
; 0.994 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.171      ; 1.377      ;
; 1.011 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.171      ; 1.394      ;
; 1.016 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.171      ; 1.399      ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                     ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                            ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 0.537 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.803      ;
; 0.625 ; dummydata[21]                        ; dummydata[22]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.891      ;
; 0.626 ; dummydata[10]                        ; dummydata[11]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.892      ;
; 0.696 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.962      ;
; 0.696 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.962      ;
; 0.697 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.963      ;
; 0.697 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.963      ;
; 0.697 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.962      ;
; 0.698 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.963      ;
; 0.701 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.967      ;
; 0.701 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 0.967      ;
; 0.704 ; dummydata[1]                         ; dummydata[2]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 0.969      ;
; 0.735 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.001      ;
; 0.742 ; dummydata[6]                         ; dummydata[7]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.007      ;
; 0.743 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.008      ;
; 0.750 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.016      ;
; 0.779 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.045      ;
; 0.799 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.065      ;
; 0.801 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.067      ;
; 0.805 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.071      ;
; 0.863 ; dummydata[12]                        ; dummydata[13]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.129      ;
; 0.871 ; dummydata[22]                        ; dummydata[23]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.137      ;
; 0.873 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.138      ;
; 0.874 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.140      ;
; 0.874 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.140      ;
; 0.878 ; dummydata[7]                         ; dummydata[8]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.143      ;
; 0.883 ; dummydata[11]                        ; dummydata[12]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.149      ;
; 0.885 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.150      ;
; 0.886 ; dummydata[3]                         ; dummydata[4]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.151      ;
; 0.888 ; dummydata[14]                        ; dummydata[15]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.154      ;
; 0.938 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.203      ;
; 0.963 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.228      ;
; 0.965 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.230      ;
; 1.002 ; dummydata[22]                        ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.267      ;
; 1.010 ; dummydata[19]                        ; dummydata[20]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.274      ;
; 1.016 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.282      ;
; 1.017 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.283      ;
; 1.017 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.283      ;
; 1.017 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.282      ;
; 1.019 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.285      ;
; 1.020 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.285      ;
; 1.022 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.288      ;
; 1.022 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.288      ;
; 1.032 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.298      ;
; 1.034 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.300      ;
; 1.035 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.300      ;
; 1.054 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.319      ;
; 1.054 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.319      ;
; 1.054 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.319      ;
; 1.054 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.319      ;
; 1.067 ; dummydata[9]                         ; dummydata[10]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.333      ;
; 1.091 ; dummydata[4]                         ; dummydata[5]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.356      ;
; 1.102 ; dummydata[23]                        ; dummydata[0]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.368      ;
; 1.111 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.377      ;
; 1.114 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.380      ;
; 1.123 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.389      ;
; 1.138 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.404      ;
; 1.139 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.405      ;
; 1.150 ; dummydata[21]                        ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.415      ;
; 1.169 ; dummydata[18]                        ; dummydata[19]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.437      ;
; 1.172 ; dummydata[15]                        ; dummydata[16]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.438      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.180 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.072      ; 1.447      ;
; 1.191 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.456      ;
; 1.209 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.074      ; 1.478      ;
; 1.211 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.074      ; 1.480      ;
; 1.211 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.074      ; 1.480      ;
; 1.212 ; dummydata[9]                         ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.476      ;
; 1.212 ; dummydata[8]                         ; dummydata[9]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.076      ; 1.483      ;
; 1.215 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.074      ; 1.484      ;
; 1.217 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.482      ;
; 1.217 ; dummydata[0]                         ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.482      ;
; 1.222 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.487      ;
; 1.228 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.074      ; 1.497      ;
; 1.248 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.513      ;
; 1.254 ; dummydata[8]                         ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.522      ;
; 1.261 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.526      ;
; 1.317 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.583      ;
; 1.318 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.584      ;
; 1.318 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.583      ;
; 1.320 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.585      ;
; 1.344 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.609      ;
; 1.348 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.614      ;
; 1.349 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.615      ;
; 1.352 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.617      ;
; 1.352 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.617      ;
; 1.387 ; dummydata[1]                         ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.073      ; 1.655      ;
; 1.391 ; dummydata[5]                         ; dummydata[6]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.070      ; 1.656      ;
; 1.391 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.657      ;
; 1.406 ; dummydata[20]                        ; dummydata[21]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.071      ; 1.672      ;
; 1.418 ; dummydata[16]                        ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.069      ; 1.682      ;
; 1.429 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.075      ; 1.699      ;
; 1.429 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.075      ; 1.699      ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                           ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 2.143 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.000        ; 0.071      ; 2.409      ;
; 2.800 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 0.738      ;
; 2.801 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 0.739      ;
; 2.930 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 0.868      ;
; 2.941 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 0.882      ;
; 2.949 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.008     ; 0.888      ;
; 2.958 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 0.896      ;
; 2.961 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 0.899      ;
; 2.965 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 0.903      ;
; 2.984 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 0.922      ;
; 2.997 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.008     ; 0.936      ;
; 3.200 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 1.138      ;
; 3.216 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.157      ;
; 3.235 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.176      ;
; 3.236 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.177      ;
; 3.241 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.005     ; 1.183      ;
; 3.241 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.182      ;
; 3.241 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.007     ; 1.181      ;
; 3.252 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.004     ; 1.195      ;
; 3.258 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.005     ; 1.200      ;
; 3.267 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.208      ;
; 3.270 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.211      ;
; 3.270 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.211      ;
; 3.286 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.005     ; 1.228      ;
; 3.430 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.371      ;
; 3.450 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.004     ; 1.393      ;
; 3.458 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.006     ; 1.399      ;
; 3.518 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.004     ; 1.461      ;
; 3.519 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.009     ; 1.457      ;
; 3.690 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.004     ; 1.633      ;
; 3.723 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -1.004     ; 1.666      ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                     ;
+---------------------------------------------------------------+--------+---------------+
; Clock                                                         ; Slack  ; End Point TNS ;
+---------------------------------------------------------------+--------+---------------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 3.884  ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 8.115  ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 23.218 ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 24.670 ; 0.000         ;
+---------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                     ;
+---------------------------------------------------------------+-------+---------------+
; Clock                                                         ; Slack ; End Point TNS ;
+---------------------------------------------------------------+-------+---------------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.194 ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 0.194 ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 0.247 ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.930 ; 0.000         ;
+---------------------------------------------------------------+-------+---------------+


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+-------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                          ;
+---------------------------------------------------------------+-----------+---------------+
; Clock                                                         ; Slack     ; End Point TNS ;
+---------------------------------------------------------------+-----------+---------------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 2.563     ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; 4.993     ; 0.000         ;
; clock_48                                                      ; 10.004    ; 0.000         ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; 13.673    ; 0.000         ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 13.674    ; 0.000         ;
; rtc_32khz                                                     ; 30513.579 ; 0.000         ;
+---------------------------------------------------------------+-----------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                              ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                ; To Node                                                                                                                      ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 3.884 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.065     ; 1.355      ;
; 3.884 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.059     ; 1.552      ;
; 3.943 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.060     ; 1.301      ;
; 3.999 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 1.452      ;
; 4.007 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_0~DFFHI       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.056     ; 1.241      ;
; 4.015 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.490      ;
; 4.016 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.489      ;
; 4.016 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.489      ;
; 4.016 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 1.435      ;
; 4.018 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.487      ;
; 4.018 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.487      ;
; 4.019 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.486      ;
; 4.019 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.486      ;
; 4.020 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 1.431      ;
; 4.027 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.478      ;
; 4.029 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.476      ;
; 4.029 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.476      ;
; 4.031 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.474      ;
; 4.050 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.455      ;
; 4.117 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_2~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.061     ; 1.317      ;
; 4.163 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 1.288      ;
; 4.168 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 1.283      ;
; 4.179 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 1.272      ;
; 4.190 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 1.259      ;
; 4.192 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]     ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.037     ; 1.313      ;
; 4.256 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out|ddio_outa_1~DFFLO       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.065     ; 1.174      ;
; 4.290 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.216      ;
; 4.305 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.201      ;
; 4.307 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.199      ;
; 4.311 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.195      ;
; 4.331 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.175      ;
; 4.334 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.172      ;
; 4.336 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.170      ;
; 4.347 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.159      ;
; 4.350 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.156      ;
; 4.357 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.149      ;
; 4.362 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.144      ;
; 4.367 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.139      ;
; 4.371 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]            ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.135      ;
; 4.380 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFHI ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.057     ; 0.867      ;
; 4.403 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.103      ;
; 4.411 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 1.093      ;
; 4.413 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.093      ;
; 4.421 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.085      ;
; 4.421 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.085      ;
; 4.421 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]             ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 1.085      ;
; 4.424 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 1.080      ;
; 4.427 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 1.022      ;
; 4.445 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 1.059      ;
; 4.453 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 1.051      ;
; 4.465 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.039     ; 1.038      ;
; 4.476 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.039     ; 1.027      ;
; 4.481 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.039     ; 1.022      ;
; 4.484 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.092     ; 0.966      ;
; 4.486 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.039     ; 1.017      ;
; 4.504 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio|ddio_outa_0~DFFLO ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.057     ; 0.934      ;
; 4.524 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.925      ;
; 4.539 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 0.967      ;
; 4.541 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 0.965      ;
; 4.550 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.899      ;
; 4.550 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.899      ;
; 4.550 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.899      ;
; 4.550 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.899      ;
; 4.550 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.899      ;
; 4.550 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.899      ;
; 4.552 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.952      ;
; 4.553 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.036     ; 0.953      ;
; 4.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.889      ;
; 4.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.889      ;
; 4.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.889      ;
; 4.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.889      ;
; 4.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.889      ;
; 4.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.889      ;
; 4.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.889      ;
; 4.560 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.093     ; 0.889      ;
; 4.574 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.930      ;
; 4.617 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.834      ;
; 4.617 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.834      ;
; 4.617 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.834      ;
; 4.617 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.834      ;
; 4.617 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.834      ;
; 4.617 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.834      ;
; 4.618 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.886      ;
; 4.633 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.039     ; 0.870      ;
; 4.636 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.039     ; 0.867      ;
; 4.636 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                           ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.868      ;
; 4.641 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.863      ;
; 4.642 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.862      ;
; 4.647 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.857      ;
; 4.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.798      ;
; 4.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.798      ;
; 4.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.798      ;
; 4.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.798      ;
; 4.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.798      ;
; 4.653 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.091     ; 0.798      ;
; 4.654 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.850      ;
; 4.654 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.850      ;
; 4.654 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.086     ; 0.802      ;
; 4.655 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.849      ;
; 4.655 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 5.555        ; -0.038     ; 0.849      ;
+-------+--------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                               ;
+-------+-------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node   ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 8.115 ; led_ctr[1]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.203      ;
; 8.142 ; led_ctr[1]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 2.174      ;
; 8.149 ; led_ctr[2]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.169      ;
; 8.193 ; led_ctr[0]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.125      ;
; 8.200 ; led_ctr[2]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 2.116      ;
; 8.201 ; led_ctr[1]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.117      ;
; 8.210 ; led_ctr[0]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 2.106      ;
; 8.217 ; led_ctr[4]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.101      ;
; 8.259 ; led_ctr[2]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.059      ;
; 8.261 ; led_ctr[3]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.057      ;
; 8.268 ; led_ctr[4]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 2.048      ;
; 8.269 ; led_ctr[0]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.049      ;
; 8.278 ; led_ctr[3]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 2.038      ;
; 8.281 ; led_ctr[6]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.037      ;
; 8.327 ; led_ctr[4]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.991      ;
; 8.330 ; led_ctr[5]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.988      ;
; 8.332 ; led_ctr[6]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.984      ;
; 8.337 ; led_ctr[3]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.981      ;
; 8.346 ; led_ctr[5]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.970      ;
; 8.349 ; led_ctr[8]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.969      ;
; 8.391 ; led_ctr[6]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.927      ;
; 8.397 ; led_ctr[7]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.921      ;
; 8.400 ; led_ctr[8]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.916      ;
; 8.405 ; led_ctr[5]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.913      ;
; 8.414 ; led_ctr[7]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.902      ;
; 8.421 ; led_ctr[10] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.897      ;
; 8.459 ; led_ctr[8]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.859      ;
; 8.465 ; led_ctr[9]  ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.853      ;
; 8.472 ; led_ctr[10] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.844      ;
; 8.473 ; led_ctr[7]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.845      ;
; 8.481 ; led_ctr[9]  ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.835      ;
; 8.489 ; led_ctr[12] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.829      ;
; 8.531 ; led_ctr[10] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.787      ;
; 8.533 ; led_ctr[11] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.785      ;
; 8.540 ; led_ctr[12] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.776      ;
; 8.540 ; led_ctr[9]  ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.778      ;
; 8.550 ; led_ctr[11] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.766      ;
; 8.557 ; led_ctr[14] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.761      ;
; 8.599 ; led_ctr[12] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.719      ;
; 8.601 ; led_ctr[13] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.717      ;
; 8.608 ; led_ctr[14] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.708      ;
; 8.609 ; led_ctr[11] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.709      ;
; 8.618 ; led_ctr[13] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.040     ; 1.698      ;
; 8.620 ; led_ctr[16] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.697      ;
; 8.667 ; led_ctr[14] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.651      ;
; 8.669 ; led_ctr[15] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.648      ;
; 8.671 ; led_ctr[16] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.041     ; 1.644      ;
; 8.672 ; led_ctr[1]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.697      ;
; 8.677 ; led_ctr[13] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 1.641      ;
; 8.686 ; led_ctr[15] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.041     ; 1.629      ;
; 8.691 ; led_ctr[18] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.626      ;
; 8.700 ; led_ctr[1]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.669      ;
; 8.730 ; led_ctr[16] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.587      ;
; 8.730 ; led_ctr[2]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.639      ;
; 8.734 ; led_ctr[2]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.635      ;
; 8.736 ; led_ctr[17] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.581      ;
; 8.740 ; led_ctr[1]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.629      ;
; 8.740 ; led_ctr[0]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.629      ;
; 8.742 ; led_ctr[18] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.041     ; 1.573      ;
; 8.745 ; led_ctr[15] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.572      ;
; 8.753 ; led_ctr[17] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.041     ; 1.562      ;
; 8.759 ; led_ctr[20] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.558      ;
; 8.768 ; led_ctr[1]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.601      ;
; 8.778 ; led_ctr[0]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.591      ;
; 8.798 ; led_ctr[4]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.571      ;
; 8.798 ; led_ctr[2]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.571      ;
; 8.801 ; led_ctr[18] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.516      ;
; 8.802 ; led_ctr[4]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.567      ;
; 8.802 ; led_ctr[2]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.567      ;
; 8.804 ; led_ctr[19] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.513      ;
; 8.808 ; led_ctr[1]  ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.561      ;
; 8.808 ; led_ctr[3]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.561      ;
; 8.808 ; led_ctr[0]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.561      ;
; 8.810 ; led_ctr[20] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.041     ; 1.505      ;
; 8.812 ; led_ctr[17] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.505      ;
; 8.820 ; led_ctr[19] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.041     ; 1.495      ;
; 8.823 ; led_ctr[22] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.494      ;
; 8.836 ; led_ctr[1]  ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.533      ;
; 8.846 ; led_ctr[3]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.523      ;
; 8.846 ; led_ctr[0]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.523      ;
; 8.862 ; led_ctr[6]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.507      ;
; 8.866 ; led_ctr[6]  ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.503      ;
; 8.866 ; led_ctr[4]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.503      ;
; 8.866 ; led_ctr[2]  ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.503      ;
; 8.869 ; led_ctr[20] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.448      ;
; 8.870 ; led_ctr[4]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.499      ;
; 8.870 ; led_ctr[2]  ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.499      ;
; 8.873 ; led_ctr[21] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.444      ;
; 8.874 ; led_ctr[22] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.041     ; 1.441      ;
; 8.876 ; led_ctr[1]  ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.493      ;
; 8.876 ; led_ctr[5]  ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.493      ;
; 8.876 ; led_ctr[3]  ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.493      ;
; 8.876 ; led_ctr[0]  ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.493      ;
; 8.879 ; led_ctr[19] ; led_ctr[28]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.438      ;
; 8.882 ; rst_ctr[0]  ; rst_n                    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.486      ;
; 8.888 ; led_ctr[21] ; led_ctr[26]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.041     ; 1.427      ;
; 8.891 ; led_ctr[24] ; led_ctr[27]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.039     ; 1.426      ;
; 8.904 ; led_ctr[1]  ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.465      ;
; 8.914 ; led_ctr[3]  ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.455      ;
; 8.914 ; led_ctr[0]  ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.455      ;
+-------+-------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                              ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node     ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 23.218 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 4.509      ;
; 23.243 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 4.489      ;
; 23.247 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 4.485      ;
; 23.311 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 4.421      ;
; 23.315 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 4.417      ;
; 23.466 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 4.261      ;
; 23.501 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 4.237      ;
; 23.515 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 4.223      ;
; 23.536 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 4.191      ;
; 23.536 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 4.191      ;
; 23.545 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 4.182      ;
; 23.721 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 4.006      ;
; 23.728 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.999      ;
; 23.751 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.987      ;
; 23.773 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.965      ;
; 23.784 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.943      ;
; 23.787 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.951      ;
; 23.797 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.036     ; 3.932      ;
; 23.802 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.036     ; 3.927      ;
; 23.811 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.916      ;
; 23.840 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.898      ;
; 23.854 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.884      ;
; 23.858 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.870      ;
; 23.859 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.869      ;
; 23.879 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.859      ;
; 23.893 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.845      ;
; 23.936 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.792      ;
; 23.950 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.780      ;
; 23.959 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.779      ;
; 23.959 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.779      ;
; 23.967 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.036     ; 3.762      ;
; 23.968 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.762      ;
; 23.968 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.762      ;
; 23.973 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.765      ;
; 23.973 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.765      ;
; 23.998 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.740      ;
; 24.012 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.726      ;
; 24.023 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.715      ;
; 24.046 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.681      ;
; 24.062 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.665      ;
; 24.090 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.648      ;
; 24.091 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.636      ;
; 24.105 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.031     ; 3.629      ;
; 24.115 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.036     ; 3.614      ;
; 24.119 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.608      ;
; 24.120 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.610      ;
; 24.120 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.036     ; 3.609      ;
; 24.129 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.598      ;
; 24.129 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.609      ;
; 24.131 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.601      ;
; 24.133 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.605      ;
; 24.135 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.597      ;
; 24.147 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.591      ;
; 24.176 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.552      ;
; 24.177 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.551      ;
; 24.199 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.533      ;
; 24.203 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.529      ;
; 24.209 ; dummydata[6]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.529      ;
; 24.209 ; dummydata[1]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.529      ;
; 24.218 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.510      ;
; 24.220 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.508      ;
; 24.222 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.508      ;
; 24.229 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.499      ;
; 24.248 ; dummydata[8]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.490      ;
; 24.254 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.474      ;
; 24.261 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.031     ; 3.473      ;
; 24.267 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.031     ; 3.467      ;
; 24.285 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.036     ; 3.444      ;
; 24.290 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.440      ;
; 24.293 ; dummydata[17] ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.437      ;
; 24.300 ; dummydata[13] ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.428      ;
; 24.303 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.429      ;
; 24.307 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.425      ;
; 24.310 ; dummydata[16] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.417      ;
; 24.319 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.413      ;
; 24.323 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.409      ;
; 24.339 ; dummydata[14] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.388      ;
; 24.367 ; dummydata[9]  ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.360      ;
; 24.371 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.361      ;
; 24.374 ; dummydata[10] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.353      ;
; 24.375 ; dummydata[0]  ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.357      ;
; 24.377 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.031     ; 3.357      ;
; 24.383 ; dummydata[2]  ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.355      ;
; 24.387 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.345      ;
; 24.391 ; dummydata[23] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.341      ;
; 24.421 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.027     ; 3.317      ;
; 24.424 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.303      ;
; 24.433 ; dummydata[18] ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.294      ;
; 24.444 ; dummydata[7]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.031     ; 3.290      ;
; 24.469 ; dummydata[12] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.258      ;
; 24.471 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.261      ;
; 24.475 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.255      ;
; 24.479 ; dummydata[19] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.035     ; 3.251      ;
; 24.483 ; dummydata[4]  ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.031     ; 3.251      ;
; 24.488 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.244      ;
; 24.491 ; dummydata[5]  ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.033     ; 3.241      ;
; 24.500 ; dummydata[11] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.038     ; 3.227      ;
; 24.533 ; dummydata[3]  ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.031     ; 3.201      ;
; 24.536 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.192      ;
; 24.538 ; dummydata[15] ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 27.778       ; -0.037     ; 3.190      ;
+--------+---------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                           ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 24.670 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.761     ; 0.846      ;
; 24.673 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.760     ; 0.844      ;
; 24.712 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.766     ; 0.799      ;
; 24.741 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.761     ; 0.775      ;
; 24.779 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.760     ; 0.738      ;
; 24.818 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.697      ;
; 24.834 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.681      ;
; 24.859 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.656      ;
; 24.868 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.647      ;
; 24.874 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.761     ; 0.642      ;
; 24.879 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.636      ;
; 24.880 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.761     ; 0.636      ;
; 24.881 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.634      ;
; 24.887 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.761     ; 0.629      ;
; 24.888 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.627      ;
; 24.894 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.761     ; 0.622      ;
; 24.895 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.620      ;
; 24.897 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.763     ; 0.617      ;
; 24.907 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.608      ;
; 24.915 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.765     ; 0.597      ;
; 25.050 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.765     ; 0.462      ;
; 25.051 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.764     ; 0.462      ;
; 25.055 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.765     ; 0.457      ;
; 25.058 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.764     ; 0.455      ;
; 25.062 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.762     ; 0.453      ;
; 25.064 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.765     ; 0.448      ;
; 25.067 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.765     ; 0.445      ;
; 25.068 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.765     ; 0.444      ;
; 25.138 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.765     ; 0.374      ;
; 25.140 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 26.390       ; -0.765     ; 0.372      ;
; 26.550 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 27.778       ; -0.036     ; 1.179      ;
+--------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]'                                                                                                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                ; To Node                                                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 0.194 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.196 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
; 0.198 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.198 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.199 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.319      ;
; 0.199 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.319      ;
; 0.199 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.319      ;
; 0.226 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.346      ;
; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.372      ;
; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.253 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.373      ;
; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.373      ;
; 0.254 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.374      ;
; 0.255 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.374      ;
; 0.255 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.374      ;
; 0.255 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.375      ;
; 0.255 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.375      ;
; 0.259 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.378      ;
; 0.260 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.379      ;
; 0.261 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.381      ;
; 0.263 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.382      ;
; 0.263 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.383      ;
; 0.263 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.382      ;
; 0.263 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.382      ;
; 0.264 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.383      ;
; 0.265 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.385      ;
; 0.265 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.384      ;
; 0.266 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.386      ;
; 0.267 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.387      ;
; 0.268 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.388      ;
; 0.268 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.388      ;
; 0.268 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.388      ;
; 0.269 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.389      ;
; 0.270 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.390      ;
; 0.271 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.391      ;
; 0.274 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.394      ;
; 0.277 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.397      ;
; 0.277 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.397      ;
; 0.277 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.397      ;
; 0.278 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.398      ;
; 0.278 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.398      ;
; 0.281 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.401      ;
; 0.301 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.421      ;
; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.421      ;
; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.421      ;
; 0.302 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
; 0.303 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.422      ;
; 0.303 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4] ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.422      ;
; 0.307 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.499      ;
; 0.317 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.437      ;
; 0.319 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.035      ; 0.438      ;
; 0.324 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.444      ;
; 0.324 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.444      ;
; 0.325 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.445      ;
; 0.327 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.093      ; 0.521      ;
; 0.328 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.089      ; 0.518      ;
; 0.330 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.092      ; 0.523      ;
; 0.335 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.455      ;
; 0.336 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.096      ; 0.533      ;
; 0.336 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.094      ; 0.531      ;
; 0.336 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]        ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.528      ;
; 0.336 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a                                 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]         ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.528      ;
; 0.338 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.458      ;
; 0.343 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.093      ; 0.537      ;
; 0.349 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.090      ; 0.540      ;
; 0.354 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.090      ; 0.545      ;
; 0.357 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.090      ; 0.548      ;
; 0.358 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.550      ;
; 0.359 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.551      ;
; 0.362 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.554      ;
; 0.363 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.090      ; 0.554      ;
; 0.363 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.090      ; 0.554      ;
; 0.364 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.556      ;
; 0.365 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.090      ; 0.556      ;
; 0.373 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.565      ;
; 0.374 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.566      ;
; 0.380 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.090      ; 0.571      ;
; 0.381 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.501      ;
; 0.383 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.575      ;
; 0.385 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.090      ; 0.576      ;
; 0.392 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.584      ;
; 0.397 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.091      ; 0.589      ;
; 0.410 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.093      ; 0.604      ;
; 0.411 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.531      ;
; 0.423 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.036      ; 0.543      ;
; 0.425 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]                                    ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.093      ; 0.619      ;
; 0.426 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.034      ; 0.544      ;
; 0.426 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]         ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]                                    ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.034      ; 0.544      ;
; 0.427 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]                                   ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; -0.003       ; 0.093      ; 0.621      ;
; 0.432 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.033      ; 0.549      ;
; 0.434 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11                                       ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.033      ; 0.551      ;
; 0.440 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]        ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]                                   ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000        ; 0.034      ; 0.558      ;
+-------+--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                             ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                ; To Node                  ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 0.194 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.314      ;
; 0.293 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.412      ;
; 0.294 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; led_ctr[21]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; led_ctr[15]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
; 0.294 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
; 0.294 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
; 0.294 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
; 0.295 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
; 0.295 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
; 0.296 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; led_ctr[13]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
; 0.296 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
; 0.300 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.419      ;
; 0.366 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.485      ;
; 0.384 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.504      ;
; 0.441 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.561      ;
; 0.442 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
; 0.443 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
; 0.443 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
; 0.443 ; led_ctr[10]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
; 0.443 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
; 0.444 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
; 0.444 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
; 0.444 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
; 0.444 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
; 0.452 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
; 0.453 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
; 0.453 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
; 0.454 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
; 0.455 ; rst_ctr[5]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
; 0.456 ; rst_ctr[1]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.575      ;
; 0.456 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.575      ;
; 0.457 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
; 0.457 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
; 0.504 ; led_ctr[14]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.624      ;
; 0.505 ; rst_ctr[4]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.625      ;
+-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                     ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                            ; To Node                              ; Launch Clock                                    ; Latch Clock                                     ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
; 0.247 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.366      ;
; 0.278 ; dummydata[21]                        ; dummydata[22]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.397      ;
; 0.278 ; dummydata[10]                        ; dummydata[11]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.397      ;
; 0.298 ; dummydata[1]                         ; dummydata[2]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.417      ;
; 0.299 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.419      ;
; 0.300 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.419      ;
; 0.301 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.420      ;
; 0.320 ; tmdsenc:hdmitmds[2].enc|disparity[3] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.439      ;
; 0.322 ; dummydata[6]                         ; dummydata[7]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.441      ;
; 0.324 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.444      ;
; 0.327 ; tmdsenc:hdmitmds[0].enc|disparity[3] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.446      ;
; 0.346 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.465      ;
; 0.350 ; dummydata[22]                        ; dummydata[23]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.469      ;
; 0.351 ; dummydata[12]                        ; dummydata[13]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.470      ;
; 0.353 ; dummydata[7]                         ; dummydata[8]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.472      ;
; 0.354 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.473      ;
; 0.356 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.475      ;
; 0.356 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.475      ;
; 0.356 ; dummydata[11]                        ; dummydata[12]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.475      ;
; 0.358 ; dummydata[14]                        ; dummydata[15]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.477      ;
; 0.358 ; dummydata[3]                         ; dummydata[4]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.477      ;
; 0.364 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.483      ;
; 0.364 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.483      ;
; 0.367 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.487      ;
; 0.384 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.503      ;
; 0.416 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.535      ;
; 0.416 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.535      ;
; 0.416 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.535      ;
; 0.416 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.535      ;
; 0.424 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.034      ; 0.542      ;
; 0.426 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.034      ; 0.544      ;
; 0.427 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.034      ; 0.545      ;
; 0.438 ; dummydata[22]                        ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.557      ;
; 0.447 ; dummydata[19]                        ; dummydata[20]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.033      ; 0.564      ;
; 0.447 ; tmdsenc:hdmitmds[1].enc|disparity[2] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.567      ;
; 0.448 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.567      ;
; 0.449 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.568      ;
; 0.449 ; tmdsenc:hdmitmds[2].enc|disparity[2] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.568      ;
; 0.449 ; tmdsenc:hdmitmds[0].enc|disparity[2] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.568      ;
; 0.459 ; dummydata[4]                         ; dummydata[5]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.578      ;
; 0.459 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.579      ;
; 0.459 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.578      ;
; 0.460 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.579      ;
; 0.462 ; tmdsenc:hdmitmds[1].enc|disparity[1] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.582      ;
; 0.462 ; tmdsenc:hdmitmds[0].enc|disparity[1] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.581      ;
; 0.463 ; tmdsenc:hdmitmds[2].enc|disparity[1] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.582      ;
; 0.466 ; dummydata[9]                         ; dummydata[10]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.585      ;
; 0.468 ; dummydata[23]                        ; dummydata[0]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.587      ;
; 0.479 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.599      ;
; 0.493 ; dummydata[21]                        ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.612      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[1].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[6]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[4]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.499 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[2]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.619      ;
; 0.511 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.630      ;
; 0.512 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.631      ;
; 0.514 ; tmdsenc:hdmitmds[0].enc|disparity[0] ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.633      ;
; 0.515 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.635      ;
; 0.515 ; tmdsenc:hdmitmds[2].enc|disparity[0] ; tmdsenc:hdmitmds[2].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.634      ;
; 0.518 ; dummydata[15]                        ; dummydata[16]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.637      ;
; 0.519 ; dummydata[8]                         ; dummydata[9]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.040      ; 0.643      ;
; 0.534 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.034      ; 0.652      ;
; 0.534 ; dummydata[18]                        ; dummydata[19]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.655      ;
; 0.540 ; dummydata[0]                         ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.659      ;
; 0.541 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.664      ;
; 0.542 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.665      ;
; 0.543 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.666      ;
; 0.543 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.034      ; 0.661      ;
; 0.544 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.034      ; 0.662      ;
; 0.544 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.034      ; 0.662      ;
; 0.545 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[9]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.668      ;
; 0.545 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[8]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.668      ;
; 0.555 ; dummydata[17]                        ; tmdsenc:hdmitmds[2].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.674      ;
; 0.557 ; dummydata[9]                         ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.033      ; 0.674      ;
; 0.559 ; dummydata[8]                         ; tmdsenc:hdmitmds[0].enc|qreg[7]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.037      ; 0.680      ;
; 0.567 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[5]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.687      ;
; 0.568 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[3]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.688      ;
; 0.574 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.694      ;
; 0.576 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.040      ; 0.700      ;
; 0.576 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.040      ; 0.700      ;
; 0.576 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[1] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.040      ; 0.700      ;
; 0.576 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[0].enc|disparity[0] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.040      ; 0.700      ;
; 0.578 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.698      ;
; 0.580 ; tmdsenc:hdmitmds[1].enc|disparity[3] ; tmdsenc:hdmitmds[1].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.700      ;
; 0.581 ; tmdsenc:hdmitmds[1].enc|disparity[0] ; tmdsenc:hdmitmds[1].enc|disparity[3] ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.036      ; 0.701      ;
; 0.600 ; dummydata[5]                         ; dummydata[6]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.719      ;
; 0.608 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[0]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.731      ;
; 0.608 ; tmdsenc:hdmitmds[0].enc|denreg       ; tmdsenc:hdmitmds[2].enc|qreg[1]      ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.039      ; 0.731      ;
; 0.616 ; dummydata[2]                         ; dummydata[3]                         ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.735      ;
; 0.618 ; dummydata[20]                        ; dummydata[21]                        ; pll|altpll_component|auto_generated|pll1|clk[2] ; pll|altpll_component|auto_generated|pll1|clk[2] ; 0.000        ; 0.035      ; 0.737      ;
+-------+--------------------------------------+--------------------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]'                                                                                                                                                                                                                                                                           ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                  ; Latch Clock                                                   ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+
; 0.930 ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.000        ; 0.036      ; 1.050      ;
; 2.003 ; tmdsenc:hdmitmds[0].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.314      ;
; 2.004 ; tmdsenc:hdmitmds[2].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.315      ;
; 2.064 ; tmdsenc:hdmitmds[0].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.375      ;
; 2.069 ; tmdsenc:hdmitmds[0].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.382      ;
; 2.070 ; tmdsenc:hdmitmds[1].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.524     ; 0.382      ;
; 2.072 ; tmdsenc:hdmitmds[2].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.383      ;
; 2.075 ; tmdsenc:hdmitmds[2].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.386      ;
; 2.078 ; tmdsenc:hdmitmds[2].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.389      ;
; 2.081 ; tmdsenc:hdmitmds[2].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.392      ;
; 2.083 ; tmdsenc:hdmitmds[1].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.524     ; 0.395      ;
; 2.197 ; tmdsenc:hdmitmds[2].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.525     ; 0.508      ;
; 2.208 ; tmdsenc:hdmitmds[0].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.521      ;
; 2.212 ; tmdsenc:hdmitmds[2].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.525      ;
; 2.214 ; tmdsenc:hdmitmds[0].enc|qreg[9]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.527      ;
; 2.216 ; tmdsenc:hdmitmds[2].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.521     ; 0.531      ;
; 2.220 ; tmdsenc:hdmitmds[1].enc|qreg[0]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.521     ; 0.535      ;
; 2.221 ; tmdsenc:hdmitmds[1].enc|qreg[7]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.534      ;
; 2.222 ; tmdsenc:hdmitmds[0].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.535      ;
; 2.224 ; tmdsenc:hdmitmds[1].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.537      ;
; 2.224 ; tmdsenc:hdmitmds[1].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.522     ; 0.538      ;
; 2.228 ; tmdsenc:hdmitmds[1].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.541      ;
; 2.232 ; tmdsenc:hdmitmds[1].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.522     ; 0.546      ;
; 2.233 ; tmdsenc:hdmitmds[1].enc|qreg[2]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.522     ; 0.547      ;
; 2.281 ; tmdsenc:hdmitmds[2].enc|qreg[6]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.523     ; 0.594      ;
; 2.296 ; tmdsenc:hdmitmds[1].enc|qreg[4]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.522     ; 0.610      ;
; 2.319 ; tmdsenc:hdmitmds[0].enc|qreg[5]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.521     ; 0.634      ;
; 2.346 ; tmdsenc:hdmitmds[0].enc|qreg[3]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.521     ; 0.661      ;
; 2.366 ; tmdsenc:hdmitmds[2].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.526     ; 0.676      ;
; 2.419 ; tmdsenc:hdmitmds[0].enc|qreg[1]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]   ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.520     ; 0.735      ;
; 2.422 ; tmdsenc:hdmitmds[0].enc|qreg[8]                                                          ; hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]    ; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; -1.388       ; -0.521     ; 0.737      ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+--------------+------------+------------+


----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                        ;
+----------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                          ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+----------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                               ; 1.906  ; 0.194 ; N/A      ; N/A     ; 2.476               ;
;  clock_48                                                      ; N/A    ; N/A   ; N/A      ; N/A     ; 10.004              ;
;  hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 1.906  ; 0.194 ; N/A      ; N/A     ; 2.476               ;
;  hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 22.698 ; 0.930 ; N/A      ; N/A     ; 13.588              ;
;  pll|altpll_component|auto_generated|pll1|clk[1]               ; 5.089  ; 0.194 ; N/A      ; N/A     ; 4.909               ;
;  pll|altpll_component|auto_generated|pll1|clk[2]               ; 17.383 ; 0.247 ; N/A      ; N/A     ; 13.586              ;
;  rtc_32khz                                                     ; N/A    ; N/A   ; N/A      ; N/A     ; 30513.579           ;
; Design-wide TNS                                                ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  clock_48                                                      ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  pll|altpll_component|auto_generated|pll1|clk[1]               ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  pll|altpll_component|auto_generated|pll1|clk[2]               ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  rtc_32khz                                                     ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
+----------------------------------------------------------------+--------+-------+----------+---------+---------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; abc_d_oe       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_rdy_x      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_resin_x    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_int80_x    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_int800_x   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_nmi_x      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_xm_x       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_master     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_a_oe       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_d_ce_n     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_clk         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_cke         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_ba[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_ba[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_a[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dqm[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dqm[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_cs_n        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_we_n        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_cas_n       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_ras_n       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sd_clk         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sd_cmd         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; tty_rxd        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; tty_cts        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; flash_cs_n     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; flash_clk      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; flash_mosi     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; led[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; led[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; led[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; hdmi_d[0]      ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
; hdmi_d[1]      ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
; hdmi_d[2]      ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
; hdmi_clk       ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
; abc_d[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_d[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_d[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_d[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_d[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_d[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_d[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; abc_d[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; hdmi_sda       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; exth_ha        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; exth_hb        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; exth_hd        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; exth_he        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; exth_hf        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; exth_hg        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sr_dq[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sd_dat[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sd_dat[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sd_dat[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; sd_dat[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; spi_clk        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; spi_miso       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; spi_mosi       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; spi_cs_esp_n   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; spi_cs_flash_n ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; esp_io0        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; esp_int        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; i2c_scl        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; i2c_sda        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; gpio[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; gpio[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; gpio[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; gpio[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; gpio[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; gpio[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; hdmi_scl       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; hdmi_hpd       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; hdmi_d[0](n)   ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
; hdmi_d[1](n)   ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
; hdmi_d[2](n)   ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
; hdmi_clk(n)    ; LVDS         ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; open                ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; 100 Ohm            ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-------------------------------------------------------------------+
; Input Transition Times                                            ;
+----------------+--------------+-----------------+-----------------+
; Pin            ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------------+--------------+-----------------+-----------------+
; abc_clk        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[0]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[1]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[2]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[3]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[4]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[5]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[6]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[7]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[8]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[9]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[10]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[11]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[12]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[13]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[14]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_a[15]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_rst_n      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_cs_n       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_out_n[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_out_n[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_out_n[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_out_n[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_out_n[4]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_inp_n[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_inp_n[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_xmemfl_n   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_xmemw800_n ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_xmemw80_n  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_xinpstb_n  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_xoutpstb_n ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; exth_hc        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; exth_hh        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; tty_txd        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; tty_rts        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; tty_dtr        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; flash_miso     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; rtc_32khz      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; rtc_int_n      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_d[0]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_d[1]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_d[2]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_d[3]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_d[4]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_d[5]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_d[6]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; abc_d[7]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; hdmi_sda       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; exth_ha        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; exth_hb        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; exth_hd        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; exth_he        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; exth_hf        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; exth_hg        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[0]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[1]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[2]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[3]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[4]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[5]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[6]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[7]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[8]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[9]       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[10]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[11]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[12]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[13]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[14]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sr_dq[15]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sd_dat[0]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sd_dat[1]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sd_dat[2]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; sd_dat[3]      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; spi_clk        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; spi_miso       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; spi_mosi       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; spi_cs_esp_n   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; spi_cs_flash_n ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; esp_io0        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; esp_int        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; i2c_scl        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; i2c_sda        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; gpio[0]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; gpio[1]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; gpio[2]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; gpio[3]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; gpio[4]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; gpio[5]        ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; hdmi_scl       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; hdmi_hpd       ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; clock_48       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+----------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; abc_d_oe       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_rdy_x      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_resin_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_int80_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_int800_x   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
; abc_nmi_x      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_xm_x       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; abc_master     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_a_oe       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; abc_d_ce_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_clk         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_cke         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_ba[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
; sr_ba[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_a[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dqm[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dqm[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_cs_n        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_we_n        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_cas_n       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_ras_n       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sd_clk         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; sd_cmd         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; tty_rxd        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.09 V              ; -0.00842 V          ; 0.277 V                              ; 0.268 V                              ; 5.24e-09 s                  ; 3.95e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.09 V             ; -0.00842 V         ; 0.277 V                             ; 0.268 V                             ; 5.24e-09 s                 ; 3.95e-09 s                 ; No                        ; Yes                       ;
; tty_cts        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; flash_cs_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.61e-08 V                   ; 3.09 V              ; -0.0154 V           ; 0.101 V                              ; 0.226 V                              ; 2.13e-09 s                  ; 2.1e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.61e-08 V                  ; 3.09 V             ; -0.0154 V          ; 0.101 V                             ; 0.226 V                             ; 2.13e-09 s                 ; 2.1e-09 s                  ; Yes                       ; No                        ;
; flash_clk      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.63e-09 V                   ; 3.17 V              ; -0.033 V            ; 0.146 V                              ; 0.089 V                              ; 4.42e-10 s                  ; 4e-10 s                     ; No                         ; Yes                        ; 3.08 V                      ; 3.63e-09 V                  ; 3.17 V             ; -0.033 V           ; 0.146 V                             ; 0.089 V                             ; 4.42e-10 s                 ; 4e-10 s                    ; No                        ; Yes                       ;
; flash_mosi     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.61e-08 V                   ; 3.09 V              ; -0.0154 V           ; 0.101 V                              ; 0.226 V                              ; 2.13e-09 s                  ; 2.1e-09 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.61e-08 V                  ; 3.09 V             ; -0.0154 V          ; 0.101 V                             ; 0.226 V                             ; 2.13e-09 s                 ; 2.1e-09 s                  ; Yes                       ; No                        ;
; led[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; led[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; led[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; hdmi_d[0]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
; hdmi_d[1]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
; hdmi_d[2]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
; hdmi_clk       ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
; abc_d[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_d[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_d[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_d[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_d[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_d[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
; abc_d[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; abc_d[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; hdmi_sda       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; exth_ha        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
; exth_hb        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; exth_hd        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; exth_he        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; exth_hf        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; exth_hg        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
; sr_dq[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sr_dq[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
; sr_dq[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sd_dat[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; sd_dat[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; sd_dat[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.09 V              ; -0.00842 V          ; 0.277 V                              ; 0.268 V                              ; 5.24e-09 s                  ; 3.95e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.09 V             ; -0.00842 V         ; 0.277 V                             ; 0.268 V                             ; 5.24e-09 s                 ; 3.95e-09 s                 ; No                        ; Yes                       ;
; sd_dat[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; spi_clk        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.09 V              ; -0.00919 V          ; 0.272 V                              ; 0.279 V                              ; 4.99e-09 s                  ; 3.74e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.09 V             ; -0.00919 V         ; 0.272 V                             ; 0.279 V                             ; 4.99e-09 s                 ; 3.74e-09 s                 ; No                        ; Yes                       ;
; spi_miso       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; spi_mosi       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; spi_cs_esp_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; spi_cs_flash_n ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; esp_io0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; esp_int        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; i2c_scl        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; i2c_sda        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.79e-09 V                   ; 3.13 V              ; -0.0451 V           ; 0.284 V                              ; 0.25 V                               ; 1.14e-09 s                  ; 8.82e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.79e-09 V                  ; 3.13 V             ; -0.0451 V          ; 0.284 V                             ; 0.25 V                              ; 1.14e-09 s                 ; 8.82e-10 s                 ; No                        ; Yes                       ;
; gpio[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; gpio[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; gpio[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; gpio[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; gpio[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; gpio[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; hdmi_scl       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; hdmi_hpd       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 9.45e-09 V                   ; 3.15 V              ; -0.0747 V           ; 0.2 V                                ; 0.271 V                              ; 6.5e-10 s                   ; 4.56e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 9.45e-09 V                  ; 3.15 V             ; -0.0747 V          ; 0.2 V                               ; 0.271 V                             ; 6.5e-10 s                  ; 4.56e-10 s                 ; No                        ; Yes                       ;
; hdmi_d[0](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
; hdmi_d[1](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
; hdmi_d[2](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
; hdmi_clk(n)    ; LVDS         ; 0 s                 ; 0 s                 ; 0.41 V                       ; -0.41 V                      ; -                   ; -                   ; -                                    ; -                                    ; 3.79e-10 s                  ; 3.8e-10 s                   ; Yes                        ; Yes                        ; 0.41 V                      ; -0.41 V                     ; -                  ; -                  ; -                                   ; -                                   ; 3.79e-10 s                 ; 3.8e-10 s                  ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; abc_d_oe       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_rdy_x      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_resin_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_int80_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_int800_x   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
; abc_nmi_x      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_xm_x       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; abc_master     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_a_oe       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; abc_d_ce_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_clk         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_cke         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_ba[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
; sr_ba[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_a[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dqm[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dqm[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_cs_n        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_we_n        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_cas_n       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_ras_n       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sd_clk         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; sd_cmd         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; tty_rxd        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.08 V              ; -0.00375 V          ; 0.284 V                              ; 0.246 V                              ; 6.17e-09 s                  ; 4.91e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.08 V             ; -0.00375 V         ; 0.284 V                             ; 0.246 V                             ; 6.17e-09 s                 ; 4.91e-09 s                 ; No                        ; Yes                       ;
; tty_cts        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; flash_cs_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.24e-06 V                   ; 3.08 V              ; -0.00575 V          ; 0.055 V                              ; 0.187 V                              ; 2.59e-09 s                  ; 2.64e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.24e-06 V                  ; 3.08 V             ; -0.00575 V         ; 0.055 V                             ; 0.187 V                             ; 2.59e-09 s                 ; 2.64e-09 s                 ; Yes                       ; Yes                       ;
; flash_clk      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.58e-07 V                   ; 3.13 V              ; -0.0413 V           ; 0.178 V                              ; 0.078 V                              ; 4.81e-10 s                  ; 4.67e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.58e-07 V                  ; 3.13 V             ; -0.0413 V          ; 0.178 V                             ; 0.078 V                             ; 4.81e-10 s                 ; 4.67e-10 s                 ; Yes                       ; Yes                       ;
; flash_mosi     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.24e-06 V                   ; 3.08 V              ; -0.00575 V          ; 0.055 V                              ; 0.187 V                              ; 2.59e-09 s                  ; 2.64e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.24e-06 V                  ; 3.08 V             ; -0.00575 V         ; 0.055 V                             ; 0.187 V                             ; 2.59e-09 s                 ; 2.64e-09 s                 ; Yes                       ; Yes                       ;
; led[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; led[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; led[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[0]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[1]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[2]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_clk       ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; abc_d[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_d[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_d[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_d[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_d[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_d[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
; abc_d[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; abc_d[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_sda       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; exth_ha        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
; exth_hb        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; exth_hd        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; exth_he        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; exth_hf        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; exth_hg        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
; sr_dq[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sr_dq[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
; sr_dq[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sd_dat[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; sd_dat[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; sd_dat[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.08 V              ; -0.00375 V          ; 0.284 V                              ; 0.246 V                              ; 6.17e-09 s                  ; 4.91e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.08 V             ; -0.00375 V         ; 0.284 V                             ; 0.246 V                             ; 6.17e-09 s                 ; 4.91e-09 s                 ; No                        ; Yes                       ;
; sd_dat[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; spi_clk        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.08 V              ; -0.00449 V          ; 0.31 V                               ; 0.243 V                              ; 5.79e-09 s                  ; 4.66e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.08 V             ; -0.00449 V         ; 0.31 V                              ; 0.243 V                             ; 5.79e-09 s                 ; 4.66e-09 s                 ; No                        ; Yes                       ;
; spi_miso       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; spi_mosi       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; spi_cs_esp_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; spi_cs_flash_n ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; esp_io0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; esp_int        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; i2c_scl        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; i2c_sda        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.21e-07 V                   ; 3.11 V              ; -0.0305 V           ; 0.284 V                              ; 0.283 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.21e-07 V                  ; 3.11 V             ; -0.0305 V          ; 0.284 V                             ; 0.283 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; gpio[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; gpio[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; gpio[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; gpio[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; gpio[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; gpio[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_scl       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_hpd       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.76e-07 V                   ; 3.12 V              ; -0.0504 V           ; 0.296 V                              ; 0.208 V                              ; 6.98e-10 s                  ; 6.34e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.76e-07 V                  ; 3.12 V             ; -0.0504 V          ; 0.296 V                             ; 0.208 V                             ; 6.98e-10 s                 ; 6.34e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[0](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[1](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[2](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_clk(n)    ; LVDS         ; 0 s                 ; 0 s                 ; 0.355 V                      ; -0.355 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.82e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.355 V                     ; -0.355 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.82e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; abc_d_oe       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_rdy_x      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_resin_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_int80_x    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_int800_x   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
; abc_nmi_x      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_xm_x       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; abc_master     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_a_oe       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; abc_d_ce_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_clk         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_cke         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_ba[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
; sr_ba[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_a[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dqm[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dqm[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_cs_n        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_we_n        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_cas_n       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_ras_n       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sd_clk         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; sd_cmd         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; tty_rxd        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.48 V              ; -0.0129 V           ; 0.351 V                              ; 0.278 V                              ; 4.12e-09 s                  ; 3.46e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.48 V             ; -0.0129 V          ; 0.351 V                             ; 0.278 V                             ; 4.12e-09 s                 ; 3.46e-09 s                 ; No                        ; No                        ;
; tty_cts        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; flash_cs_n     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.329 V                              ; 1.74e-09 s                  ; 1.76e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.329 V                             ; 1.74e-09 s                 ; 1.76e-09 s                 ; No                        ; No                        ;
; flash_clk      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.59e-08 V                   ; 3.58 V              ; -0.0705 V           ; 0.234 V                              ; 0.092 V                              ; 2.93e-10 s                  ; 3.09e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.59e-08 V                  ; 3.58 V             ; -0.0705 V          ; 0.234 V                             ; 0.092 V                             ; 2.93e-10 s                 ; 3.09e-10 s                 ; Yes                       ; Yes                       ;
; flash_mosi     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.329 V                              ; 1.74e-09 s                  ; 1.76e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.329 V                             ; 1.74e-09 s                 ; 1.76e-09 s                 ; No                        ; No                        ;
; led[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; led[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; led[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; hdmi_d[0]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[1]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[2]      ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_clk       ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; abc_d[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_d[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_d[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_d[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_d[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_d[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
; abc_d[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; abc_d[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; hdmi_sda       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; exth_ha        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
; exth_hb        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; exth_hd        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; exth_he        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; exth_hf        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; exth_hg        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
; sr_dq[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sr_dq[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
; sr_dq[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sd_dat[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; sd_dat[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; sd_dat[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.48 V              ; -0.0129 V           ; 0.351 V                              ; 0.278 V                              ; 4.12e-09 s                  ; 3.46e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.48 V             ; -0.0129 V          ; 0.351 V                             ; 0.278 V                             ; 4.12e-09 s                 ; 3.46e-09 s                 ; No                        ; No                        ;
; sd_dat[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; spi_clk        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.48 V              ; -0.014 V            ; 0.359 V                              ; 0.292 V                              ; 3.93e-09 s                  ; 3.26e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.92e-07 V                  ; 3.48 V             ; -0.014 V           ; 0.359 V                             ; 0.292 V                             ; 3.93e-09 s                 ; 3.26e-09 s                 ; No                        ; No                        ;
; spi_miso       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; spi_mosi       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; spi_cs_esp_n   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; spi_cs_flash_n ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; esp_io0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; esp_int        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; i2c_scl        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; i2c_sda        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.3e-07 V                    ; 3.55 V              ; -0.053 V            ; 0.335 V                              ; 0.361 V                              ; 9.06e-10 s                  ; 7.36e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.3e-07 V                   ; 3.55 V             ; -0.053 V           ; 0.335 V                             ; 0.361 V                             ; 9.06e-10 s                 ; 7.36e-10 s                 ; No                        ; No                        ;
; gpio[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; gpio[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; gpio[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; gpio[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; gpio[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; gpio[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; hdmi_scl       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; hdmi_hpd       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.92e-07 V                   ; 3.58 V              ; -0.0891 V           ; 0.324 V                              ; 0.191 V                              ; 4.6e-10 s                   ; 4.21e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.92e-07 V                  ; 3.58 V             ; -0.0891 V          ; 0.324 V                             ; 0.191 V                             ; 4.6e-10 s                  ; 4.21e-10 s                 ; No                        ; Yes                       ;
; hdmi_d[0](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[1](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_d[2](n)   ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
; hdmi_clk(n)    ; LVDS         ; 0 s                 ; 0 s                 ; 0.526 V                      ; -0.526 V                     ; -                   ; -                   ; -                                    ; -                                    ; 3.81e-10 s                  ; 3.83e-10 s                  ; Yes                        ; Yes                        ; 0.526 V                     ; -0.526 V                    ; -                  ; -                  ; -                                   ; -                                   ; 3.81e-10 s                 ; 3.83e-10 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                 ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------+------------+------------+----------+
; From Clock                                                    ; To Clock                                                      ; RR Paths   ; FR Paths   ; RF Paths   ; FF Paths ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------+------------+------------+----------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 180        ; 0          ; 0          ; 0        ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 98         ; 0          ; 0          ; 0        ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 1          ; 0          ; 0          ; 0        ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 30         ; 0          ; 0          ; 0        ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; pll|altpll_component|auto_generated|pll1|clk[1]               ; 609        ; 0          ; 0          ; 0        ;
; rst_n                                                         ; pll|altpll_component|auto_generated|pll1|clk[1]               ; false path ; false path ; 0          ; 0        ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; pll|altpll_component|auto_generated|pll1|clk[2]               ; 9603       ; 0          ; 0          ; 0        ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; rst_n                                                         ; false path ; 0          ; false path ; 0        ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                  ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------+------------+------------+----------+
; From Clock                                                    ; To Clock                                                      ; RR Paths   ; FR Paths   ; RF Paths   ; FF Paths ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------+------------+------------+----------+
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 180        ; 0          ; 0          ; 0        ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; 98         ; 0          ; 0          ; 0        ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 1          ; 0          ; 0          ; 0        ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; 30         ; 0          ; 0          ; 0        ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; pll|altpll_component|auto_generated|pll1|clk[1]               ; 609        ; 0          ; 0          ; 0        ;
; rst_n                                                         ; pll|altpll_component|auto_generated|pll1|clk[1]               ; false path ; false path ; 0          ; 0        ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; pll|altpll_component|auto_generated|pll1|clk[2]               ; 9603       ; 0          ; 0          ; 0        ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; rst_n                                                         ; false path ; 0          ; false path ; 0        ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+--------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                           ;
+------------+-------------------------------------------------+------------+------------+----------+----------+
; From Clock ; To Clock                                        ; RR Paths   ; FR Paths   ; RF Paths ; FF Paths ;
+------------+-------------------------------------------------+------------+------------+----------+----------+
; rst_n      ; pll|altpll_component|auto_generated|pll1|clk[1] ; false path ; false path ; 0        ; 0        ;
; rst_n      ; pll|altpll_component|auto_generated|pll1|clk[2] ; false path ; false path ; 0        ; 0        ;
+------------+-------------------------------------------------+------------+------------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+--------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                            ;
+------------+-------------------------------------------------+------------+------------+----------+----------+
; From Clock ; To Clock                                        ; RR Paths   ; FR Paths   ; RF Paths ; FF Paths ;
+------------+-------------------------------------------------+------------+------------+----------+----------+
; rst_n      ; pll|altpll_component|auto_generated|pll1|clk[1] ; false path ; false path ; 0        ; 0        ;
; rst_n      ; pll|altpll_component|auto_generated|pll1|clk[2] ; false path ; false path ; 0        ; 0        ;
+------------+-------------------------------------------------+------------+------------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths Summary                    ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 0     ; 0    ;
; Unconstrained Input Port Paths  ; 0     ; 0    ;
; Unconstrained Output Ports      ; 12    ; 12   ;
; Unconstrained Output Port Paths ; 12    ; 12   ;
+---------------------------------+-------+------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Status Summary                                                                                                                                    ;
+---------------------------------------------------------------+---------------------------------------------------------------+-----------+-------------+
; Target                                                        ; Clock                                                         ; Type      ; Status      ;
+---------------------------------------------------------------+---------------------------------------------------------------+-----------+-------------+
; clock_48                                                      ; clock_48                                                      ; Base      ; Constrained ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] ; Generated ; Constrained ;
; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] ; Generated ; Constrained ;
; pll|altpll_component|auto_generated|pll1|clk[0]               ; pll|altpll_component|auto_generated|pll1|clk[0]               ; Generated ; Constrained ;
; pll|altpll_component|auto_generated|pll1|clk[1]               ; pll|altpll_component|auto_generated|pll1|clk[1]               ; Generated ; Constrained ;
; pll|altpll_component|auto_generated|pll1|clk[2]               ; pll|altpll_component|auto_generated|pll1|clk[2]               ; Generated ; Constrained ;
; rst_n                                                         ; rst_n                                                         ; Generated ; Constrained ;
; rtc_32khz                                                     ; rtc_32khz                                                     ; Base      ; Constrained ;
+---------------------------------------------------------------+---------------------------------------------------------------+-----------+-------------+


+------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                           ;
+--------------+---------------------------------------------------------------------------------------+
; Output Port  ; Comment                                                                               ;
+--------------+---------------------------------------------------------------------------------------+
; hdmi_clk     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_clk(n)  ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[0]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[0](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[1]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[1](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[2]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[2](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sr_clk       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------+---------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                           ;
+--------------+---------------------------------------------------------------------------------------+
; Output Port  ; Comment                                                                               ;
+--------------+---------------------------------------------------------------------------------------+
; hdmi_clk     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_clk(n)  ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[0]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[0](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[1]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[1](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[2]    ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; hdmi_d[2](n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[1]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3]       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sr_clk       ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+--------------+---------------------------------------------------------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
    Info: Processing started: Fri Aug  6 20:12:54 2021
Info: Command: quartus_sta --lower_priority max80 -c max80
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity pll_altpll
        Info (332166): set_false_path -from ** -to *phasedone_state* 
        Info (332166): set_false_path -from ** -to *internal_phasestep* 
Warning (332174): Ignored filter at qsta_default_script.tcl(1297): *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
Warning (332049): Ignored set_false_path at qsta_default_script.tcl(1297): Argument <to> is not an object ID File: /opt/altera/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
    Info (332050): read_sdc File: /opt/altera/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
Warning (332174): Ignored filter at qsta_default_script.tcl(1297): *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
Warning (332049): Ignored set_false_path at qsta_default_script.tcl(1297): Argument <to> is not an object ID File: /opt/altera/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
    Info (332050): read_sdc File: /opt/altera/20.1/quartus/common/tcl/internal/qsta_default_script.tcl Line: 1297
Info (332104): Reading SDC File: 'max80.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[0]} {pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[1]} {pll|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 4 -multiply_by 3 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[2]} {pll|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -multiply_by 5 -phase -90.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0]}
    Info (332110): create_generated_clock -source {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|inclk[0]} -phase -18.00 -duty_cycle 50.00 -name {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]} {hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at max80.sdc(30): *|synchronizer:*|qreg0* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 30
Warning (332049): Ignored set_multicycle_path at max80.sdc(31): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
    Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
    -start -setup 2 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 31
Warning (332049): Ignored set_multicycle_path at max80.sdc(33): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
    Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
    -start -hold -1 File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 33
Warning (332174): Ignored filter at max80.sdc(37): sld_signaltap:* could not be matched with a register File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
Warning (332049): Ignored set_false_path at max80.sdc(37): Argument <to> is an empty collection File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
    Info (332050): set_false_path -to [get_registers sld_signaltap:*] File: /home/hpa/abc80/max80/blinktest/max80.sdc Line: 37
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 1.906
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     1.906               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     5.089               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.383               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    22.698               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
Info (332146): Worst-case hold slack is 0.466
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.466               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.504               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     0.576               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     2.295               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 2.477
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     2.477               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     4.909               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    10.341               0.000 clock_48 
    Info (332119):    13.586               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    13.589               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
    Info (332119): 30513.579               0.000 rtc_32khz 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info (332146): Worst-case setup slack is 2.078
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     2.078               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     5.556               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.936               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    22.985               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
Info (332146): Worst-case hold slack is 0.418
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.418               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.473               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     0.537               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     2.143               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 2.476
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     2.476               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     4.909               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    10.354               0.000 clock_48 
    Info (332119):    13.586               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    13.588               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
    Info (332119): 30513.579               0.000 rtc_32khz 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info (332146): Worst-case setup slack is 3.884
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     3.884               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     8.115               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    23.218               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    24.670               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
Info (332146): Worst-case hold slack is 0.194
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.194               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     0.194               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.247               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.930               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 2.563
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     2.563               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[0] 
    Info (332119):     4.993               0.000 pll|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    10.004               0.000 clock_48 
    Info (332119):    13.673               0.000 pll|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    13.674               0.000 hdmitx|ALTLVDS_TX_component|auto_generated|lvds_tx_pll|clk[1] 
    Info (332119): 30513.579               0.000 rtc_32khz 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings
    Info: Peak virtual memory: 728 megabytes
    Info: Processing ended: Fri Aug  6 20:12:56 2021
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Fri Aug  6 20:12:57 2021 ;
; Revision Name             ; max80                                 ;
; Top-level Entity Name     ; max80                                 ;
; Family                    ; Cyclone IV E                          ;
; Simulation Files Creation ; Successful                            ;
+---------------------------+---------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                                           ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option                                                                                            ; Setting                   ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
; Generate functional simulation netlist                                                            ; On                        ;
; Truncate long hierarchy paths                                                                     ; Off                       ;
; Map illegal HDL characters                                                                        ; On                        ;
; Flatten buses into individual nodes                                                               ; Off                       ;
; Maintain hierarchy                                                                                ; Off                       ;
; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
; Enable glitch filtering                                                                           ; On                        ;
; Generate Power Estimate Scripts                                                                   ; All output signals        ;
; Test Bench design instance name                                                                   ; max80                     ;
; Do not write top level VHDL entity                                                                ; Off                       ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
; Architecture name in VHDL output netlist                                                          ; structure                 ;
; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
+---------------------------------------------------------------------------------------------------+---------------------------+


+----------------------------------------------------------------------------------+
; Simulation Generated Files                                                       ;
+----------------------------------------------------------------------------------+
; Generated Files                                                                  ;
+----------------------------------------------------------------------------------+
; /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80.vo                     ;
; /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl ;
+----------------------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
    Info: Processing started: Fri Aug  6 20:12:57 2021
Info: Command: quartus_eda --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
Info (204020): Writing VCD Dump Commands for all nodes to /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 816 megabytes
    Info: Processing ended: Fri Aug  6 20:12:57 2021
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:00