Aucune description

H. Peter Anvin 2441395031 fpga/sam.sv: Verilog model for SmartAid Magnum il y a 1 an
abc 3dd521c55c abc: new directory with ABC programs; first: read/set RTC il y a 3 ans
common 5cebedf6c4 Merge branch 'main' of ssh://terminus.zytor.com/git/abc80/max80/fw il y a 1 an
drivers 79e6a716a5 drivers: .inf file for Windows (untested) il y a 1 an
esp32 30a38c6163 esp32: move pin definitions to a header file il y a 1 an
fpga 2441395031 fpga/sam.sv: Verilog model for SmartAid Magnum il y a 1 an
img 50f7f572a3 WIP: ringbuffer system between ESP32 and FPGA il y a 2 ans
rv32 9af9dcb725 Update binaries il y a 1 an
tools f2c2a12b99 gnu tools: include autoconf/automake sources il y a 1 an
.gitattributes e1878a396f Detect the presence of an ABC-bus by looking for a clock signal il y a 3 ans
.gitignore 937addeb1f Source code and build mechanism for ABC(80) ROMS il y a 1 an
.gitmodules bfcdff61ed Remove unused module esp32/lite-uploader il y a 1 an
LICENSE 83af2b9ff4 Add LICENSE file il y a 3 ans
Makefile 5c8b28bc2a Makefile: fix version string in "make setver-*" il y a 1 an
riscv-opts.mk 8544ceec29 tools: update gnu tools; remove annoying riscv wrapper il y a 2 ans
version.h.sed 8df4011a1e www: show build info on status screen; prep for unified build info il y a 2 ans
version.vh.sed 8df4011a1e www: show build info on status screen; prep for unified build info il y a 2 ans