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max80_fw
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cleanup-start
dma-queue
esplink
i2c
main
newpagemap
newqreg
setverwww
simpleio
slow
sysvars
uart-rework
unaligned
v1.2.x
v1.2
v1.1
v1.0
v0.0
max80_fw
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ip
H. Peter Anvin
30d5acc569
Change core clock to 168 MHz and video clock to 48 MHz
3 年之前
..
ddio_out.v
43d9806872
Remove unused assignments; use a DDIO buffer for sr_clk
3 年之前
hdmitx.v
30d5acc569
Change core clock to 168 MHz and video clock to 48 MHz
3 年之前
pll.v
30d5acc569
Change core clock to 168 MHz and video clock to 48 MHz
3 年之前