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max80_fw
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fpga
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ip
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int_osc
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synthesis
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submodules
H. Peter Anvin 980eaf0400 Restructure clock tree; better sdram timing; random number generator il y a 3 ans
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altera_int_osc.v 980eaf0400 Restructure clock tree; better sdram timing; random number generator il y a 3 ans