max80_fw/fpga/bypass_main.qsf

# -*- tcl -*-

set_global_assignment -name TOP_LEVEL_ENTITY bypass
set_global_assignment -name SYSTEMVERILOG_FILE bypass.sv

set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE15F17C8
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:21:14  DECEMBER 22, 2021"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name DEVICE_MIGRATION_LIST EP4CE15F17C8
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VCCA_USER_VOLTAGE 2.5V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name MUX_RESTRUCTURE AUTO
set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
set_global_assignment -name STRATIXIII_UPDATE_MODE STANDARD
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name GENERATE_JBC_FILE ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk

set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_*
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCQ128A

set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V

set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:scripts/preflow.tcl"
set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/postmodule.tcl"

set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"

set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testclk -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME testclk -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME max80 -section_id testclk
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id testclk
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testclk -section_id testclk
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/testclk.sv -section_id testclk
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation

set_global_assignment -name OCP_HW_EVAL DISABLE
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON

set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS ON
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
set_global_assignment -name POWER_USE_TA_VALUE 35

set_global_assignment -name SOURCE_FILE bypass.pins
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl

set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rtc_32khz
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdo
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tck
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdi
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tms
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_clk
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to board_id

set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR /home/hpa/abc80/max80/fw/fpga/bsdl -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan