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- module clk_buf
- #(
- parameter bit invert = 1'b0,
- parameter bit noddio = 1'b0
- )
- (
- input clk,
- output pin
- );
- generate
- if ( noddio )
- begin
- assign pin = clk ^ invert;
- end
- else
- begin
- ddio_out ddiobuf (
- .aclr ( 1'b0 ),
- .datain_h ( ~invert ),
- .datain_l ( invert ),
- .outclock ( clk ),
- .dataout ( pin )
- );
- end
- endgenerate
- endmodule
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