max80_fw/fpga/dirty.sv

//
// dirty.sv
//
// SDRAM dirty bit
//
// Tracks dirty SDRAM pages on a 4K granularity. Currently accessed
// from the CPU one bit at a time, but could be improved.
// W1C semantics from the CPU.
//

module dirty
  #(parameter pagebits = 13,
    parameter pages = 1 << pagebits
    )
   (
    input		 rst_n,
    input		 clk,
    input [pagebits-1:0] dirty_pg,
    input		 dirty_stb,

    input  [31:2]	 cpu_addr,
    input  [ 3:0]	 cpu_wstrb,
    input  [31:0]	 cpu_wdata,
    output [31:0]	 cpu_rdata
    );

   assign cpu_rdata[31:1] = 'b0;

   dirtyram ram (
		 .clock (clk),

		 .address_a	(cpu_addr[pagebits+1:2]),
		 .data_a	(1'b0),
		 .wren_a	(cpu_wstrb[0] & cpu_wdata[0]),
		 .q_a		(cpu_rdata[0]),
		 .rden_a	(1'b1),

		 .address_b	(dirty_pg),
		 .data_b	(1'b1),
		 .wren_b	(dirty_stb),
		 .q_b		( ),
		 .rden_b	(1'b0)
		 );
endmodule