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- create_clock -name "clock_48" -period 20.834ns [get_ports {clock_48}]
- derive_pll_clocks
- derive_clock_uncertainty
- create_generated_clock -name rst_n \
- -source [get_nets pll|*clk\[1\]] \
- [get_registers rst_n]
- set main_clocks [get_clocks pll|*]
- set_clock_groups -asynchronous \
- -group $main_clocks \
- -group [get_clocks rst_n]
- set sdram_out_clk [get_clocks pll|*|clk\[0\]]
- set sdram_clk [get_clocks pll|*|clk\[4\]]
- set cpu_clk [get_clocks pll|*|clk\[1\]]
- set vid_clk [get_clocks pll|*|clk\[2\]]
- set flash_clk [get_clocks pll|*|clk\[3\]]
- set sr_data_out [remove_from_collection [get_ports sr_*] sr_clk]
- set sr_data_in [get_ports sr_dq\[*\]]
- set_max_skew -to $sr_data_out 0.100ns
- set_input_delay -clock $sdram_clk 0.500ns $sr_data_in
- set synchro_inputs [get_registers *|synchronizer:*|qreg0*]
- set_multicycle_path -from [all_clocks] -to $synchro_inputs \
- -start -setup 2
- set_multicycle_path -from [all_clocks] -to $synchro_inputs \
- -start -hold 1
- set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
- -start -setup 2
- set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
- -start -hold 0
- set_false_path -to [get_registers sld_signaltap:*]
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