Implement WRITE BUFFER and WRITE WITH VERIFY commands

Also fixes a problem with SD card initialisation not setting
the clock back to normal on an error condition. The next
initialisation attempt ends up running the card at a very slow
rate.

lib/SCSI2SD/CHANGELOG

@@ -1,3 +1,9 @@
+201501??		4.1.1
+	- Fix MODE SENSE bug when the allocation length is less than the
+	page size.
+	- Add WRITE BUFFER and WRITE AND VERIFY support.
+	- Fix rare case of very slow performance
+
 20150201		4.1
 	- Rewrite of the SD card interface to fix compatibility problems.
 		This fixes write issues with Samsung SD cards.

lib/SCSI2SD/readme.txt

@@ -82,6 +82,11 @@ Compatibility
         Alpha 21264 CPU, 667MHz, with a QLogic SCSI controller in a PCI slot 
     SCSI-based Macintosh Powerbooks (2.5" SCSI2SD)
         Also reported to work on Thinkpad 860 running Win NT 4.0 PowerPC. 
+	Data General MV/2500DC running AOS/VS
+		Vendor: MICROoP
+		Product: 1578-15       UP
+		Revision: DG02
+		Device-type modifier: 0x4c
 
 Samplers
 
@@ -105,3 +110,6 @@ Other
 
     HP 16601A, 16700A logic analyzers
     Fluke 9100 series 
+	Reftek RT-72A Seismic datalogger.
+		http://www.iris.iris.edu/passcal/Reftek/72A-R-005-00.1.pdf
+		http://www.iris.iris.edu/passcal/Manual/rtfm.s3a.13.html

lib/SCSI2SD/software/SCSI2SD/src/bits.c

@@ -14,6 +14,9 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
+
 #include "bits.h"
 
 const uint8 Lookup_OddParity[] =
@@ -45,3 +48,5 @@ uint8 countBits(uint8 value)
 	}
 	return i;
 }
+
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/cdrom.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -327,3 +329,5 @@ int scsiCDRomCommand()
 
 	return commandHandled;
 }
+
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/config.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "config.h"
@@ -30,7 +32,7 @@
 
 #include <string.h>
 
-static const uint16_t FIRMWARE_VERSION = 0x0410;
+static const uint16_t FIRMWARE_VERSION = 0x0411;
 
 enum USB_ENDPOINTS
 {
@@ -274,7 +276,7 @@ void debugPoll()
 		hidBuffer[26] = blockDev.state;
 		hidBuffer[27] = scsiDev.lastSenseASC >> 8;
 		hidBuffer[28] = scsiDev.lastSenseASC;
-
+		hidBuffer[29] = scsiReadDBxPins();
 
 		hidBuffer[58] = sdDev.capacity >> 24;
 		hidBuffer[59] = sdDev.capacity >> 16;
@@ -323,6 +325,11 @@ void debugResume()
 	Debug_Timer_Start();
 }
 
+int isDebugEnabled()
+{
+	return usbReady;
+}
+
 // Public method for storing MODE SELECT results.
 void configSave(int scsiId, uint16_t bytesPerSector)
 {
@@ -377,4 +384,4 @@ const TargetConfig* getConfigById(int scsiId)
 
 }
 
-
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/debug.h

@@ -20,6 +20,7 @@
 void debugInit(void);
 void debugPause(void);
 void debugResume(void);
+int isDebugEnabled(void);
 
 #endif
 

lib/SCSI2SD/software/SCSI2SD/src/diagnostic.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -162,4 +164,54 @@ void scsiReadBuffer()
 			(allocLength > MAX_SECTOR_SIZE) ? MAX_SECTOR_SIZE : allocLength;
 		scsiDev.phase = DATA_IN;
 	}
+	else
+	{
+		// error.
+		scsiDev.status = CHECK_CONDITION;
+		scsiDev.target->sense.code = ILLEGAL_REQUEST;
+		scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
+		scsiDev.phase = STATUS;
+	}
+}
+
+// Callback after the DATA OUT phase is complete.
+static void doWriteBuffer(void)
+{
+	if (scsiDev.status == GOOD) // skip if we've already encountered an error
+	{
+		// scsiDev.dataLen bytes are in scsiDev.data
+		// Don't shift it down 4 bytes ... this space is taken by
+		// the read buffer header anyway
+		scsiDev.phase = STATUS;
+	}
 }
+
+void scsiWriteBuffer()
+{
+	// WRITE BUFFER
+	// Used for testing the speed of the SCSI interface.
+	uint8 mode = scsiDev.data[1] & 7;
+
+	int allocLength =
+		(((uint32) scsiDev.cdb[6]) << 16) +
+		(((uint32) scsiDev.cdb[7]) << 8) +
+		scsiDev.cdb[8];
+
+	if (mode == 0 && allocLength <= sizeof(scsiDev.data))
+	{
+		scsiDev.dataLen = allocLength;
+		scsiDev.phase = DATA_OUT;
+		scsiDev.postDataOutHook = doWriteBuffer;
+	}
+	else
+	{
+		// error.
+		scsiDev.status = CHECK_CONDITION;
+		scsiDev.target->sense.code = ILLEGAL_REQUEST;
+		scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
+		scsiDev.phase = STATUS;
+	}
+}
+
+
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/diagnostic.h

@@ -19,6 +19,7 @@
 
 void scsiSendDiagnostic(void);
 void scsiReceiveDiagnostic(void);
+void scsiWriteBuffer(void);
 void scsiReadBuffer(void);
 
 #endif

lib/SCSI2SD/software/SCSI2SD/src/disk.c

@@ -15,6 +15,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -38,7 +40,7 @@ static int doSdInit()
 	if (blockDev.state & DISK_PRESENT)
 	{
 		result = sdInit();
-	
+
 		if (result)
 		{
 			blockDev.state = blockDev.state | DISK_INITIALISED;
@@ -167,8 +169,8 @@ static void doReadCapacity()
 
 static void doWrite(uint32 lba, uint32 blocks)
 {
-	if ((blockDev.state & DISK_WP) ||
-		(scsiDev.target->cfg->deviceType == CONFIG_OPTICAL))
+	if (unlikely(blockDev.state & DISK_WP) ||
+		unlikely(scsiDev.target->cfg->deviceType == CONFIG_OPTICAL))
 
 	{
 		scsiDev.status = CHECK_CONDITION;
@@ -176,12 +178,13 @@ static void doWrite(uint32 lba, uint32 blocks)
 		scsiDev.target->sense.asc = WRITE_PROTECTED;
 		scsiDev.phase = STATUS;
 	}
-	else if (((uint64) lba) + blocks >
+	else if (unlikely(((uint64) lba) + blocks >
 		getScsiCapacity(
 			scsiDev.target->cfg->sdSectorStart,
 			scsiDev.target->liveCfg.bytesPerSector,
 			scsiDev.target->cfg->scsiSectors
-			))
+			)
+		))
 	{
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = ILLEGAL_REQUEST;
@@ -201,7 +204,7 @@ static void doWrite(uint32 lba, uint32 blocks)
 		// No need for single-block writes atm.  Overhead of the
 		// multi-block write is minimal.
 		transfer.multiBlock = 1;
-		
+
 		sdWriteMultiSectorPrep();
 	}
 }
@@ -213,7 +216,7 @@ static void doRead(uint32 lba, uint32 blocks)
 		scsiDev.target->cfg->sdSectorStart,
 		scsiDev.target->liveCfg.bytesPerSector,
 		scsiDev.target->cfg->scsiSectors);
-	if (((uint64) lba) + blocks > capacity)
+	if (unlikely(((uint64) lba) + blocks > capacity))
 	{
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = ILLEGAL_REQUEST;
@@ -230,7 +233,7 @@ static void doRead(uint32 lba, uint32 blocks)
 		scsiDev.dataLen = 0; // No data yet
 
 		if ((blocks == 1) ||
-			(((uint64) lba) + blocks == capacity)
+			unlikely(((uint64) lba) + blocks == capacity)
 			)
 		{
 			// We get errors on reading the last sector using a multi-sector
@@ -264,7 +267,11 @@ static void doSeek(uint32 lba)
 static int doTestUnitReady()
 {
 	int ready = 1;
-	if (!(blockDev.state & DISK_STARTED))
+	if (likely(blockDev.state == (DISK_STARTED | DISK_PRESENT | DISK_INITIALISED)))
+	{
+		// nothing to do.
+	}
+	else if (unlikely(!(blockDev.state & DISK_STARTED)))
 	{
 		ready = 0;
 		scsiDev.status = CHECK_CONDITION;
@@ -272,7 +279,7 @@ static int doTestUnitReady()
 		scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED;
 		scsiDev.phase = STATUS;
 	}
-	else if (!(blockDev.state & DISK_PRESENT))
+	else if (unlikely(!(blockDev.state & DISK_PRESENT)))
 	{
 		ready = 0;
 		scsiDev.status = CHECK_CONDITION;
@@ -280,7 +287,7 @@ static int doTestUnitReady()
 		scsiDev.target->sense.asc = MEDIUM_NOT_PRESENT;
 		scsiDev.phase = STATUS;
 	}
-	else if (!(blockDev.state & DISK_INITIALISED))
+	else if (unlikely(!(blockDev.state & DISK_INITIALISED)))
 	{
 		ready = 0;
 		scsiDev.status = CHECK_CONDITION;
@@ -297,7 +304,7 @@ int scsiDiskCommand()
 	int commandHandled = 1;
 
 	uint8 command = scsiDev.cdb[0];
-	if (command == 0x1B)
+	if (unlikely(command == 0x1B))
 	{
 		// START STOP UNIT
 		// Enable or disable media access operations.
@@ -318,36 +325,16 @@ int scsiDiskCommand()
 			blockDev.state &= ~DISK_STARTED;
 		}
 	}
-	else if (command == 0x00)
+	else if (unlikely(command == 0x00))
 	{
 		// TEST UNIT READY
 		doTestUnitReady();
 	}
-	else if (!doTestUnitReady())
+	else if (unlikely(!doTestUnitReady()))
 	{
 		// Status and sense codes already set by doTestUnitReady
 	}
-	else if (command == 0x04)
-	{
-		// FORMAT UNIT
-		// We don't really do any formatting, but we need to read the correct
-		// number of bytes in the DATA_OUT phase to make the SCSI host happy.
-
-		int fmtData = (scsiDev.cdb[1] & 0x10) ? 1 : 0;
-		if (fmtData)
-		{
-			// We need to read the parameter list, but we don't know how
-			// big it is yet. Start with the header.
-			scsiDev.dataLen = 4;
-			scsiDev.phase = DATA_OUT;
-			scsiDev.postDataOutHook = doFormatUnitHeader;
-		}
-		else
-		{
-			// No data to read, we're already finished!
-		}
-	}
-	else if (command == 0x08)
+	else if (likely(command == 0x08))
 	{
 		// READ(6)
 		uint32 lba =
@@ -355,11 +342,10 @@ int scsiDiskCommand()
 			(((uint32) scsiDev.cdb[2]) << 8) +
 			scsiDev.cdb[3];
 		uint32 blocks = scsiDev.cdb[4];
-		if (blocks == 0) blocks = 256;
+		if (unlikely(blocks == 0)) blocks = 256;
 		doRead(lba, blocks);
 	}
-
-	else if (command == 0x28)
+	else if (likely(command == 0x28))
 	{
 		// READ(10)
 		// Ignore all cache control bits - we don't support a memory cache.
@@ -375,90 +361,110 @@ int scsiDiskCommand()
 
 		doRead(lba, blocks);
 	}
-
-	else if (command == 0x25)
+	else if (likely(command == 0x0A))
 	{
-		// READ CAPACITY
-		doReadCapacity();
-	}
-
-	else if (command == 0x0B)
-	{
-		// SEEK(6)
+		// WRITE(6)
 		uint32 lba =
 			(((uint32) scsiDev.cdb[1] & 0x1F) << 16) +
 			(((uint32) scsiDev.cdb[2]) << 8) +
 			scsiDev.cdb[3];
-
-		doSeek(lba);
+		uint32 blocks = scsiDev.cdb[4];
+		if (unlikely(blocks == 0)) blocks = 256;
+		doWrite(lba, blocks);
 	}
-
-	else if (command == 0x2B)
+	else if (likely(command == 0x2A) || // WRITE(10)
+		unlikely(command == 0x2E)) // WRITE AND VERIFY
 	{
-		// SEEK(10)
+		// Ignore all cache control bits - we don't support a memory cache.
+		// Don't bother verifying either. The SD card likely stores ECC
+		// along with each flash row.
+
 		uint32 lba =
 			(((uint32) scsiDev.cdb[2]) << 24) +
 			(((uint32) scsiDev.cdb[3]) << 16) +
 			(((uint32) scsiDev.cdb[4]) << 8) +
 			scsiDev.cdb[5];
+		uint32 blocks =
+			(((uint32) scsiDev.cdb[7]) << 8) +
+			scsiDev.cdb[8];
 
-		doSeek(lba);
+		doWrite(lba, blocks);
 	}
-	else if (command == 0x0A)
+
+	else if (unlikely(command == 0x04))
 	{
-		// WRITE(6)
+		// FORMAT UNIT
+		// We don't really do any formatting, but we need to read the correct
+		// number of bytes in the DATA_OUT phase to make the SCSI host happy.
+
+		int fmtData = (scsiDev.cdb[1] & 0x10) ? 1 : 0;
+		if (fmtData)
+		{
+			// We need to read the parameter list, but we don't know how
+			// big it is yet. Start with the header.
+			scsiDev.dataLen = 4;
+			scsiDev.phase = DATA_OUT;
+			scsiDev.postDataOutHook = doFormatUnitHeader;
+		}
+		else
+		{
+			// No data to read, we're already finished!
+		}
+	}
+	else if (unlikely(command == 0x25))
+	{
+		// READ CAPACITY
+		doReadCapacity();
+	}
+	else if (unlikely(command == 0x0B))
+	{
+		// SEEK(6)
 		uint32 lba =
 			(((uint32) scsiDev.cdb[1] & 0x1F) << 16) +
 			(((uint32) scsiDev.cdb[2]) << 8) +
 			scsiDev.cdb[3];
-		uint32 blocks = scsiDev.cdb[4];
-		if (blocks == 0) blocks = 256;
-		doWrite(lba, blocks);
+
+		doSeek(lba);
 	}
 
-	else if (command == 0x2A)
+	else if (unlikely(command == 0x2B))
 	{
-		// WRITE(10)
-		// Ignore all cache control bits - we don't support a memory cache.
-
+		// SEEK(10)
 		uint32 lba =
 			(((uint32) scsiDev.cdb[2]) << 24) +
 			(((uint32) scsiDev.cdb[3]) << 16) +
 			(((uint32) scsiDev.cdb[4]) << 8) +
 			scsiDev.cdb[5];
-		uint32 blocks =
-			(((uint32) scsiDev.cdb[7]) << 8) +
-			scsiDev.cdb[8];
 
-		doWrite(lba, blocks);
+		doSeek(lba);
 	}
-	else if (command == 0x36)
+	else if (unlikely(command == 0x36))
 	{
 		// LOCK UNLOCK CACHE
 		// We don't have a cache to lock data into. do nothing.
 	}
-	else if (command == 0x34)
+	else if (unlikely(command == 0x34))
 	{
 		// PRE-FETCH.
 		// We don't have a cache to pre-fetch into. do nothing.
 	}
-	else if (command == 0x1E)
+	else if (unlikely(command == 0x1E))
 	{
 		// PREVENT ALLOW MEDIUM REMOVAL
 		// Not much we can do to prevent the user removing the SD card.
 		// do nothing.
 	}
-	else if (command == 0x01)
+	else if (unlikely(command == 0x01))
 	{
 		// REZERO UNIT
 		// Set the lun to a vendor-specific state. Ignore.
 	}
-	else if (command == 0x35)
+	else if (unlikely(command == 0x35))
 	{
 		// SYNCHRONIZE CACHE
 		// We don't have a cache. do nothing.
 	}
-	else if (command == 0x2F)
+	else if (unlikely(command == 0x2F))
 	{
 		// VERIFY
 		// TODO: When they supply data to verify, we should read the data and
@@ -512,15 +518,27 @@ void scsiDiskPoll()
 		int scsiActive = 0;
 		int sdActive = 0;
 		while ((i < totalSDSectors) &&
-			(scsiDev.phase == DATA_IN) &&
-			!scsiDev.resetFlag)
+			likely(scsiDev.phase == DATA_IN) &&
+			likely(!scsiDev.resetFlag))
 		{
-			if ((sdActive == 1) && sdReadSectorDMAPoll())
+			// Wait for the next DMA interrupt. It's beneficial to halt the
+			// processor to give the DMA controller more memory bandwidth to
+			// work with.
+			// We're optimistically assuming a race condition won't occur
+			// between these checks and the interrupt handers. The 1ms
+			// systick timer interrupt saves us on the event of a race.
+			int scsiBusy = scsiDMABusy();
+			int sdBusy = sdDMABusy();
+			if (scsiBusy && sdBusy) __WFI();
+
+			if (sdActive && !sdBusy && sdReadSectorDMAPoll())
 			{
 				sdActive = 0;
 				prep++;
 			}
-			else if ((sdActive == 0) && (prep - i < buffers) && (prep < totalSDSectors))
+			else if (!sdActive &&
+				(prep - i < buffers) &&
+				(prep < totalSDSectors))
 			{
 				// Start an SD transfer if we have space.
 				if (transfer.multiBlock)
@@ -534,12 +552,12 @@ void scsiDiskPoll()
 				sdActive = 1;
 			}
 
-			if ((scsiActive == 1) && scsiWriteDMAPoll())
+			if (scsiActive && !scsiBusy && scsiWriteDMAPoll())
 			{
 				scsiActive = 0;
 				++i;
 			}
-			else if ((scsiActive == 0) && ((prep - i) > 0))
+			else if (!scsiActive && ((prep - i) > 0))
 			{
 				int dmaBytes = SD_SECTOR_SIZE;
 				if ((i % sdPerScsi) == (sdPerScsi - 1))
@@ -575,16 +593,26 @@ void scsiDiskPoll()
 		int sdActive = 0;
 
 		while ((i < totalSDSectors) &&
-			((scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase.
+			(likely(scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase.
 				scsiComplete) &&
-			!scsiDev.resetFlag)
+			likely(!scsiDev.resetFlag))
 		{
-			if ((sdActive == 1) && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))
+			// Wait for the next DMA interrupt. It's beneficial to halt the
+			// processor to give the DMA controller more memory bandwidth to
+			// work with.
+			// We're optimistically assuming a race condition won't occur
+			// between these checks and the interrupt handers. The 1ms
+			// systick timer interrupt saves us on the event of a race.
+			int scsiBusy = scsiDMABusy();
+			int sdBusy = sdDMABusy();
+			if (scsiBusy && sdBusy) __WFI();
+
+			if (sdActive && !sdBusy && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))
 			{
 				sdActive = 0;
 				i++;
 			}
-			else if ((sdActive == 0) && ((prep - i) > 0))
+			else if (!sdActive && ((prep - i) > 0))
 			{
 				// Start an SD transfer if we have space.
 				sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]);
@@ -593,16 +621,16 @@ void scsiDiskPoll()
 
 			uint32_t now = getTime_ms();
 
-			if ((scsiActive == 1) && scsiReadDMAPoll())
+			if (scsiActive && !scsiBusy && scsiReadDMAPoll())
 			{
 				scsiActive = 0;
 				++prep;
 				lastActivityTime = now;
 			}
-			else if ((scsiActive == 0) &&
+			else if (!scsiActive &&
 				((prep - i) < buffers) &&
 				(prep < totalSDSectors) &&
-				!scsiDisconnected)
+				likely(!scsiDisconnected))
 			{
 				int dmaBytes = SD_SECTOR_SIZE;
 				if ((prep % sdPerScsi) == (sdPerScsi - 1))
@@ -615,10 +643,10 @@ void scsiDiskPoll()
 			}
 			else if (
 				(scsiActive == 0) &&
-				!scsiDisconnected &&
-				scsiDev.discPriv &&
-				(diffTime_ms(lastActivityTime, now) >= 20) &&
-				(scsiDev.phase == DATA_OUT))
+				likely(!scsiDisconnected) &&
+				unlikely(scsiDev.discPriv) &&
+				unlikely(diffTime_ms(lastActivityTime, now) >= 20) &&
+				likely(scsiDev.phase == DATA_OUT))
 			{
 				// We're transferring over the SCSI bus faster than the SD card
 				// can write.  There is no more buffer space once we've finished
@@ -631,12 +659,12 @@ void scsiDiskPoll()
 				scsiDisconnected = 1;
 				lastActivityTime = getTime_ms();
 			}
-			else if (scsiDisconnected &&
+			else if (unlikely(scsiDisconnected) &&
 				(
 					(prep == i) || // Buffers empty.
 					// Send some messages every 100ms so we don't timeout.
 					// At a minimum, a reselection involves an IDENTIFY message.
-					(diffTime_ms(lastActivityTime, now) >= 100)
+					unlikely(diffTime_ms(lastActivityTime, now) >= 100)
 				))
 			{
 				int reconnected = scsiReconnect();
@@ -652,13 +680,13 @@ void scsiDiskPoll()
 				}
 			}
 			else if (
-				!scsiComplete &&
+				likely(!scsiComplete) &&
 				(sdActive == 1) &&
 				(prep == totalSDSectors) && // All scsi data read and buffered
-				!scsiDev.discPriv && // Prefer disconnect where possible.
-				(diffTime_ms(lastActivityTime, now) >= 150) &&
+				likely(!scsiDev.discPriv) && // Prefer disconnect where possible.
+				unlikely(diffTime_ms(lastActivityTime, now) >= 150) &&
 
-				(scsiDev.phase == DATA_OUT) &&
+				likely(scsiDev.phase == DATA_OUT) &&
 				!(scsiDev.cdb[scsiDev.cdbLen - 1] & 0x01) // Not linked command
 				)
 			{
@@ -685,8 +713,8 @@ void scsiDiskPoll()
 		}
 		while (
 			!scsiDev.resetFlag &&
-			scsiDisconnected &&
-			(diffTime_ms(lastActivityTime, getTime_ms()) <= 10000))
+			unlikely(scsiDisconnected) &&
+			(elapsedTime_ms(lastActivityTime) <= 10000))
 		{
 			scsiDisconnected = !scsiReconnect();
 		}
@@ -723,7 +751,7 @@ void scsiDiskReset()
 	transfer.currentBlock = 0;
 
 	// Cancel long running commands!
-	if (transfer.inProgress == 1)
+	if (unlikely(transfer.inProgress == 1))
 	{
 		if (transfer.dir == TRANSFER_WRITE)
 		{
@@ -736,8 +764,6 @@ void scsiDiskReset()
 	}
 	transfer.inProgress = 0;
 	transfer.multiBlock = 0;
-		//		SD_CS_Write(1);
-
 }
 
 void scsiDiskInit()
@@ -757,3 +783,4 @@ void scsiDiskInit()
 	#endif
 }
 
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/inquiry.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -25,7 +27,7 @@
 static uint8 StandardResponse[] =
 {
 0x00, // "Direct-access device". AKA standard hard disk
-0x00, // device type qualifier
+0x00, // device type modifier
 0x02, // Complies with ANSI SCSI-2.
 0x01, // Response format is compatible with the old CCS format.
 0x1f, // standard length.
@@ -112,6 +114,7 @@ void scsiInquiry()
 		{
 			const TargetConfig* config = scsiDev.target->cfg;
 			memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse));
+			scsiDev.data[1] = scsiDev.target->cfg->deviceTypeModifier;
 			memcpy(&scsiDev.data[8], config->vendor, sizeof(config->vendor));
 			memcpy(&scsiDev.data[16], config->prodId, sizeof(config->prodId));
 			memcpy(&scsiDev.data[32], config->revision, sizeof(config->revision));
@@ -203,3 +206,4 @@ void scsiInquiry()
 	}
 }
 
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/led.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "led.h"
 
@@ -75,3 +77,4 @@ void ledOff()
 #endif
 }
 
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/main.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -59,13 +61,21 @@ int main()
 		scsiDiskPoll();
 		configPoll();
 
-		uint32_t now = getTime_ms();
-		if (diffTime_ms(lastSDPoll, now) > 200)
+		if (unlikely(scsiDev.phase == BUS_FREE))
 		{
-			lastSDPoll = now;
-			sdPoll();
+			if (unlikely(elapsedTime_ms(lastSDPoll) > 200))
+			{
+				lastSDPoll = getTime_ms();
+				sdPoll();
+			}
+			else
+			{
+				// Wait for our 1ms timer to save some power.
+				__WFI();
+			}
 		}
 	}
 	return 0;
 }
 
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/mode.c

@@ -15,6 +15,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -152,8 +154,6 @@ static void doModeSense(
 	}
 	else
 	{
-		int pageFound = 1;
-
 		////////////// Mode Parameter Header
 		////////////////////////////////////
 
@@ -243,22 +243,25 @@ static void doModeSense(
 			scsiDev.data[idx++] = bytesPerSector & 0xFF;
 		}
 
-		switch (pageCode)
-		{
-		case 0x3F:
-			// EVERYTHING
+		int pageFound = 0;
 
-		case 0x01:
+		if (pageCode == 0x01 || pageCode == 0x3F)
+		{
+			pageFound = 1;
 			pageIn(pc, idx, ReadWriteErrorRecoveryPage, sizeof(ReadWriteErrorRecoveryPage));
 			idx += sizeof(ReadWriteErrorRecoveryPage);
-			if (pageCode != 0x3f) break;
+		}
 
-		case 0x02:
+		if (pageCode == 0x02 || pageCode == 0x3F)
+		{
+			pageFound = 1;
 			pageIn(pc, idx, DisconnectReconnectPage, sizeof(DisconnectReconnectPage));
 			idx += sizeof(DisconnectReconnectPage);
-			if (pageCode != 0x3f) break;
+		}
 
-		case 0x03:
+		if (pageCode == 0x03 || pageCode == 0x3F)
+		{
+			pageFound = 1;
 			pageIn(pc, idx, FormatDevicePage, sizeof(FormatDevicePage));
 			if (pc != 0x01)
 			{
@@ -275,10 +278,11 @@ static void doModeSense(
 			}
 
 			idx += sizeof(FormatDevicePage);
-			if (pageCode != 0x3f) break;
+		}
 
-		case 0x04:
+		if (pageCode == 0x04 || pageCode == 0x3F)
 		{
+			pageFound = 1;
 			pageIn(pc, idx, RigidDiskDriveGeometry, sizeof(RigidDiskDriveGeometry));
 
 			if (pc != 0x01)
@@ -305,25 +309,40 @@ static void doModeSense(
 			}
 
 			idx += sizeof(RigidDiskDriveGeometry);
-			if (pageCode != 0x3f) break;
 		}
 
-		case 0x08:
+		// DON'T output the following pages for SCSI1 hosts. They get upset when
+		// we have more data to send than the allocation length provided.
+		// (ie. Try not to output any more pages below this comment)
+
+
+		if (!scsiDev.compatMode && (pageCode == 0x08 || pageCode == 0x3F))
+		{
+			pageFound = 1;
 			pageIn(pc, idx, CachingPage, sizeof(CachingPage));
 			idx += sizeof(CachingPage);
-			if (pageCode != 0x3f) break;
+		}
 
-		case 0x0A:
+		if (!scsiDev.compatMode && (pageCode == 0x0A || pageCode == 0x3F))
+		{
+			pageFound = 1;
 			pageIn(pc, idx, ControlModePage, sizeof(ControlModePage));
 			idx += sizeof(ControlModePage);
-			if (pageCode != 0x3f) break;
+		}
 
-		case 0x30:
+		if ((
+				(scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE) ||
+				(idx + sizeof(AppleVendorPage) <= allocLength)
+			) &&
+			(pageCode == 0x30 || pageCode == 0x3F))
+		{
+			pageFound = 1;
 			pageIn(pc, idx, AppleVendorPage, sizeof(AppleVendorPage));
 			idx += sizeof(AppleVendorPage);
-			break;
+		}
 
-		default:
+		if (!pageFound)
+		{
 			// Unknown Page Code
 			pageFound = 0;
 			scsiDev.status = CHECK_CONDITION;
@@ -331,15 +350,7 @@ static void doModeSense(
 			scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
 			scsiDev.phase = STATUS;
 		}
-
-
-		if (idx > allocLength)
-		{
-			// Chop the reply off early if shorter length is requested
-			idx = allocLength;
-		}
-
-		if (pageFound)
+		else
 		{
 			// Go back and fill out the mode data length
 			if (sixByteCmd)
@@ -353,17 +364,9 @@ static void doModeSense(
 				scsiDev.data[1] = (idx - 2);
 			}
 
-			scsiDev.dataLen = idx;
+			scsiDev.dataLen = idx > allocLength ? allocLength : idx;
 			scsiDev.phase = DATA_IN;
 		}
-		else
-		{
-			// Page not found
-			scsiDev.status = CHECK_CONDITION;
-			scsiDev.target->sense.code = ILLEGAL_REQUEST;
-			scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB;
-			scsiDev.phase = STATUS;
-		}
 	}
 }
 
@@ -538,4 +541,4 @@ int scsiModeCommand()
 	return commandHandled;
 }
 
-
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/scsi.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -28,6 +30,7 @@
 #include "disk.h"
 #include "time.h"
 #include "cdrom.h"
+#include "debug.h"
 
 #include <string.h>
 
@@ -50,7 +53,16 @@ static void enter_BusFree()
 {
 	// This delay probably isn't needed for most SCSI hosts, but it won't
 	// hurt either. It's possible some of the samplers needed this delay.
-	CyDelayUs(2);
+	if (scsiDev.compatMode)
+	{
+		CyDelayUs(2);
+	}
+
+	if (scsiDev.status != GOOD && isDebugEnabled())
+	{
+		// We want to capture debug information for failure cases.
+		CyDelay(64);
+	}
 
 	SCSI_ClearPin(SCSI_Out_BSY);
 	// We now have a Bus Clear Delay of 800ns to release remaining signals.
@@ -75,7 +87,7 @@ void process_MessageIn()
 	scsiEnterPhase(MESSAGE_IN);
 	scsiWriteByte(scsiDev.msgIn);
 
-	if (scsiDev.atnFlag)
+	if (unlikely(scsiDev.atnFlag))
 	{
 		// If there was a parity error, we go
 		// back to MESSAGE_OUT first, get out parity error message, then come
@@ -253,7 +265,7 @@ static void process_Command()
 
 	scsiDev.cmdCount++;
 
-	if (scsiDev.resetFlag)
+	if (unlikely(scsiDev.resetFlag))
 	{
 		// Don't log bogus commands
 		scsiDev.cmdCount--;
@@ -340,6 +352,12 @@ static void process_Command()
 	{
 		enter_Status(CONFLICT);
 	}
+	else if (scsiDiskCommand())
+	{
+		// Already handled.
+		// check for the performance-critical read/write
+		// commands ASAP.
+	}
 	else if (command == 0x1C)
 	{
 		scsiReceiveDiagnostic();
@@ -348,14 +366,17 @@ static void process_Command()
 	{
 		scsiSendDiagnostic();
 	}
+	else if (command == 0x3B)
+	{
+		scsiWriteBuffer();
+	}
 	else if (command == 0x3C)
 	{
 		scsiReadBuffer();
 	}
 	else if (
-		!scsiModeCommand() &&
-		!scsiDiskCommand() &&
-		!scsiCDRomCommand())
+		!scsiCDRomCommand() &&
+		!scsiModeCommand())
 	{
 		scsiDev.target->sense.code = ILLEGAL_REQUEST;
 		scsiDev.target->sense.asc = INVALID_COMMAND_OPERATION_CODE;
@@ -515,7 +536,7 @@ static void process_SelectionPhase()
 	if (!bsy && sel &&
 		target &&
 		(goodParity || !(target->cfg->flags & CONFIG_ENABLE_PARITY) || !atnFlag) &&
-		(maskBitCount <= 2))
+		likely(maskBitCount <= 2))
 	{
 		scsiDev.target = target;
 
@@ -546,7 +567,7 @@ static void process_SelectionPhase()
 		scsiDev.selCount++;
 
 		// Wait until the end of the selection phase.
-		while (!scsiDev.resetFlag)
+		while (likely(!scsiDev.resetFlag))
 		{
 			if (!SCSI_ReadFilt(SCSI_Filt_SEL))
 			{
@@ -686,20 +707,32 @@ static void process_MessageOut()
 		// Extended message.
 		int msgLen = scsiReadByte();
 		if (msgLen == 0) msgLen = 256;
+		uint8_t extmsg[256];
 		for (i = 0; i < msgLen && !scsiDev.resetFlag; ++i)
 		{
 			// Discard bytes.
-			scsiReadByte();
+			extmsg[i] = scsiReadByte();
+		}
+		
+		if (extmsg[0] == 3 && msgLen == 2) // Wide Data Request
+		{
+			// Negotiate down to 8bit
+			scsiEnterPhase(MESSAGE_IN);
+			static const uint8_t WDTR[] = {0x01, 0x02, 0x03, 0x00};
+			scsiWrite(WDTR, sizeof(WDTR));
+		}
+		else if (extmsg[0] == 1 && msgLen == 5) // Synchronous data request
+		{
+			// Negotiate back to async
+			scsiEnterPhase(MESSAGE_IN);
+			static const uint8_t SDTR[] = {0x01, 0x03, 0x01, 0x00, 0x00};
+			scsiWrite(SDTR, sizeof(SDTR));
+		}
+		else
+		{
+			// Not supported
+			messageReject();
 		}
-
-		// We don't support ANY extended messages.
-		// Modify Data Pointer:  We don't support reselection.
-		// Wide Data Transfer Request: No. 8bit only.
-		// Synchronous data transfer request. No, we can't do that.
-		// We don't support any 2-byte messages either.
-		// And we don't support any optional 1-byte messages.
-		// In each case, the correct response is MESSAGE REJECT.
-		messageReject();
 	}
 	else
 	{
@@ -712,7 +745,7 @@ static void process_MessageOut()
 
 void scsiPoll(void)
 {
-	if (scsiDev.resetFlag)
+	if (unlikely(scsiDev.resetFlag))
 	{
 		scsiReset();
 		if ((scsiDev.resetFlag = SCSI_ReadFilt(SCSI_Filt_RST)))
@@ -932,7 +965,7 @@ int scsiReconnect()
 			while (
 				!bsy &&
 				!scsiDev.resetFlag &&
-				(diffTime_ms(waitStart_ms, getTime_ms()) < 250))
+				(elapsedTime_ms(waitStart_ms) < 250))
 			{
 				bsy = SCSI_ReadFilt(SCSI_Filt_BSY);
 			}
@@ -967,3 +1000,4 @@ int scsiReconnect()
 	return reconnected;
 }
 
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/scsi.h

@@ -147,4 +147,10 @@ void scsiPoll(void);
 void scsiDisconnect(void);
 int scsiReconnect(void);
 
+
+// Utility macros, consistent with the Linux Kernel code.
+#define likely(x)       __builtin_expect(!!(x), 1)
+#define unlikely(x)     __builtin_expect(!!(x), 0)
+//#define likely(x)       (x)
+//#define unlikely(x)     (x)
 #endif

lib/SCSI2SD/software/SCSI2SD/src/scsiPhy.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -42,19 +44,19 @@ static uint8 scsiDmaTxTd[1] = { CY_DMA_INVALID_TD };
 // Source of dummy bytes for DMA reads
 static uint8 dummyBuffer = 0xFF;
 
-volatile static uint8 rxDMAComplete;
-volatile static uint8 txDMAComplete;
+volatile uint8_t scsiRxDMAComplete;
+volatile uint8_t scsiTxDMAComplete;
 
 CY_ISR_PROTO(scsiRxCompleteISR);
 CY_ISR(scsiRxCompleteISR)
 {
-	rxDMAComplete = 1;
+	scsiRxDMAComplete = 1;
 }
 
 CY_ISR_PROTO(scsiTxCompleteISR);
 CY_ISR(scsiTxCompleteISR)
 {
-	txDMAComplete = 1;
+	scsiTxDMAComplete = 1;
 }
 
 CY_ISR_PROTO(scsiResetISR);
@@ -80,14 +82,14 @@ scsiReadDBxPins()
 uint8_t
 scsiReadByte(void)
 {
-	while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {}
+	while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}
 	scsiPhyTx(0);
 
-	while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {}
+	while (scsiPhyRxFifoEmpty() && likely(!scsiDev.resetFlag)) {}
 	uint8_t val = scsiPhyRx();
 	scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
 
-	while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}
+	while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
 
 	return val;
 }
@@ -98,7 +100,7 @@ scsiReadPIO(uint8* data, uint32 count)
 	int prep = 0;
 	int i = 0;
 
-	while (i < count && !scsiDev.resetFlag)
+	while (i < count && likely(!scsiDev.resetFlag))
 	{
 		uint8_t status = scsiPhyStatus();
 
@@ -114,7 +116,7 @@ scsiReadPIO(uint8* data, uint32 count)
 		}
 	}
 	scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
-	while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}
+	while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
 }
 
 static void
@@ -136,7 +138,7 @@ doRxSingleDMA(uint8* data, uint32 count)
 		TD_INC_DST_ADR |
 			SCSI_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
 		);
-	
+
 	CyDmaTdSetAddress(
 		scsiDmaTxTd[0],
 		LO16((uint32)&dummyBuffer),
@@ -146,18 +148,18 @@ doRxSingleDMA(uint8* data, uint32 count)
 		LO16((uint32)scsiTarget_datapath__F1_REG),
 		LO16((uint32)data)
 		);
-	
+
 	CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]);
 	CyDmaChSetInitialTd(scsiDmaRxChan, scsiDmaRxTd[0]);
-	
+
 	// The DMA controller is a bit trigger-happy. It will retain
 	// a drq request that was triggered while the channel was
 	// disabled.
 	CyDmaClearPendingDrq(scsiDmaTxChan);
 	CyDmaClearPendingDrq(scsiDmaRxChan);
 
-	txDMAComplete = 0;
-	rxDMAComplete = 0;
+	scsiTxDMAComplete = 0;
+	scsiRxDMAComplete = 0;
 
 	CyDmaChEnable(scsiDmaRxChan, 1);
 	CyDmaChEnable(scsiDmaTxChan, 1);
@@ -178,9 +180,13 @@ scsiReadDMA(uint8* data, uint32 count)
 int
 scsiReadDMAPoll()
 {
-	if (txDMAComplete && rxDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE))
+	if (scsiTxDMAComplete && scsiRxDMAComplete)
 	{
-		if (dmaSentCount == dmaTotalCount)
+		// Wait until our scsi signals are consistent. This should only be
+		// a few cycles.
+		while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}
+
+		if (likely(dmaSentCount == dmaTotalCount))
 		{
 			dmaInProgress = 0;
 			scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();
@@ -191,7 +197,7 @@ scsiReadDMAPoll()
 			// Transfer was too large for a single DMA transfer. Continue
 			// to send remaining bytes.
 			uint32_t count = dmaTotalCount - dmaSentCount;
-			if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES;
+			if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES;
 			doRxSingleDMA(dmaBuffer + dmaSentCount, count);
 			dmaSentCount += count;
 			return 0;
@@ -213,26 +219,32 @@ scsiRead(uint8_t* data, uint32_t count)
 	else
 	{
 		scsiReadDMA(data, count);
-		while (!scsiReadDMAPoll() && !scsiDev.resetFlag) {};
+		
+		// Wait for the next DMA interrupt (or the 1ms systick)
+		// It's beneficial to halt the processor to
+		// give the DMA controller more memory bandwidth to work with.
+		__WFI();
+		
+		while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};
 	}
 }
 
 void
 scsiWriteByte(uint8 value)
 {
-	while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {}
+	while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {}
 	scsiPhyTx(value);
 
-	while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}
+	while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
 	scsiPhyRxFifoClear();
 }
 
 static void
-scsiWritePIO(uint8_t* data, uint32_t count)
+scsiWritePIO(const uint8_t* data, uint32_t count)
 {
 	int i = 0;
 
-	while (i < count && !scsiDev.resetFlag)
+	while (i < count && likely(!scsiDev.resetFlag))
 	{
 		if (!scsiPhyTxFifoFull())
 		{
@@ -241,12 +253,12 @@ scsiWritePIO(uint8_t* data, uint32_t count)
 		}
 	}
 
-	while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}
+	while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {}
 	scsiPhyRxFifoClear();
 }
 
 static void
-doTxSingleDMA(uint8* data, uint32 count)
+doTxSingleDMA(const uint8* data, uint32 count)
 {
 	// Prepare DMA transfer
 	dmaInProgress = 1;
@@ -269,14 +281,14 @@ doTxSingleDMA(uint8* data, uint32 count)
 	// disabled.
 	CyDmaClearPendingDrq(scsiDmaTxChan);
 
-	txDMAComplete = 0;
-	rxDMAComplete = 1;
+	scsiTxDMAComplete = 0;
+	scsiRxDMAComplete = 1;
 
 	CyDmaChEnable(scsiDmaTxChan, 1);
 }
 
 void
-scsiWriteDMA(uint8* data, uint32 count)
+scsiWriteDMA(const uint8* data, uint32 count)
 {
 	dmaSentCount = 0;
 	dmaTotalCount = count;
@@ -290,9 +302,13 @@ scsiWriteDMA(uint8* data, uint32 count)
 int
 scsiWriteDMAPoll()
 {
-	if (txDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE))
+	if (scsiTxDMAComplete)
 	{
-		if (dmaSentCount == dmaTotalCount)
+		// Wait until our scsi signals are consistent. This should only be
+		// a few cycles.
+		while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {}
+
+		if (likely(dmaSentCount == dmaTotalCount))
 		{
 			scsiPhyRxFifoClear();
 			dmaInProgress = 0;
@@ -303,7 +319,7 @@ scsiWriteDMAPoll()
 			// Transfer was too large for a single DMA transfer. Continue
 			// to send remaining bytes.
 			uint32_t count = dmaTotalCount - dmaSentCount;
-			if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES;
+			if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES;
 			doTxSingleDMA(dmaBuffer + dmaSentCount, count);
 			dmaSentCount += count;
 			return 0;
@@ -316,7 +332,7 @@ scsiWriteDMAPoll()
 }
 
 void
-scsiWrite(uint8_t* data, uint32_t count)
+scsiWrite(const uint8_t* data, uint32_t count)
 {
 	if (count < 8)
 	{
@@ -325,11 +341,17 @@ scsiWrite(uint8_t* data, uint32_t count)
 	else
 	{
 		scsiWriteDMA(data, count);
-		while (!scsiWriteDMAPoll() && !scsiDev.resetFlag) {};
+		
+		// Wait for the next DMA interrupt (or the 1ms systick)
+		// It's beneficial to halt the processor to
+		// give the DMA controller more memory bandwidth to work with.
+		__WFI();
+
+		while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};
 	}
 }
 
-static void busSettleDelay(void)
+static inline void busSettleDelay(void)
 {
 	// Data Release time (switching IO) = 400ns
 	// + Bus Settle time (switching phase) = 400ns.
@@ -356,7 +378,7 @@ void scsiPhyReset()
 		dmaTotalCount = 0;
 		CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN);
 		CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN);
-		while (!(txDMAComplete && rxDMAComplete)) {}
+		while (!(scsiTxDMAComplete && scsiRxDMAComplete)) {}
 
 		CyDmaChDisable(scsiDmaTxChan);
 		CyDmaChDisable(scsiDmaRxChan);
@@ -406,7 +428,7 @@ static void scsiPhyInitDMA()
 				HI16(CYDEV_SRAM_BASE),
 				HI16(CYDEV_PERIPH_BASE)
 				);
-
+		
 		CyDmaChDisable(scsiDmaRxChan);
 		CyDmaChDisable(scsiDmaTxChan);
 
@@ -425,3 +447,4 @@ void scsiPhyInit()
 
 	SCSI_RST_ISR_StartEx(scsiResetISR);
 }
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/scsiPhy.h

@@ -67,6 +67,10 @@ enum FilteredInputs
 // Contains the odd-parity flag for a given 8-bit value.
 extern const uint8_t Lookup_OddParity[256];
 
+extern volatile uint8_t scsiRxDMAComplete;
+extern volatile uint8_t scsiTxDMAComplete;
+#define scsiDMABusy() (!(scsiRxDMAComplete && scsiTxDMAComplete))
+
 void scsiPhyReset(void);
 void scsiPhyInit(void);
 
@@ -76,8 +80,8 @@ void scsiReadDMA(uint8_t* data, uint32_t count);
 int scsiReadDMAPoll();
 
 void scsiWriteByte(uint8_t value);
-void scsiWrite(uint8_t* data, uint32_t count);
-void scsiWriteDMA(uint8_t* data, uint32_t count);
+void scsiWrite(const uint8_t* data, uint32_t count);
+void scsiWriteDMA(const uint8_t* data, uint32_t count);
 int scsiWriteDMAPoll();
 
 uint8_t scsiReadDBxPins(void);

lib/SCSI2SD/software/SCSI2SD/src/sd.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "device.h"
 #include "scsi.h"
@@ -37,10 +39,6 @@ static int sdIOState = SD_IDLE;
 static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;
 static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;
 
-// DMA descriptors
-static uint8 sdDMARxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
-static uint8 sdDMATxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
-
 // Dummy location for DMA to send unchecked CRC bytes to
 static uint8 discardBuffer;
 
@@ -53,18 +51,18 @@ static uint8_t writeStartToken = 0xFC;
 // Source of dummy SPI bytes for DMA
 static uint8 dummyBuffer = 0xFF;
 
-volatile static uint8 rxDMAComplete;
-volatile static uint8 txDMAComplete;
+volatile uint8_t sdRxDMAComplete;
+volatile uint8_t sdTxDMAComplete;
 
 CY_ISR_PROTO(sdRxISR);
 CY_ISR(sdRxISR)
 {
-	rxDMAComplete = 1;
+	sdRxDMAComplete = 1;
 }
 CY_ISR_PROTO(sdTxISR);
 CY_ISR(sdTxISR)
 {
-	txDMAComplete = 1;
+	sdTxDMAComplete = 1;
 }
 
 static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc)
@@ -98,14 +96,23 @@ static uint16_t sdDoCommand(
 	int useCRC,
 	int use2byteResponse)
 {
-	uint8_t send[7];
+	int waitWhileBusy = (cmd != SD_GO_IDLE_STATE) && (cmd != SD_STOP_TRANSMISSION);
+
+	// "busy" probe. We'll examine the results later.
+	if (waitWhileBusy)
+	{
+		SDCard_WriteTxData(0xFF);
+	}
 
+	// send is static as the address must remain consistent for the static
+	// DMA descriptors to work.
+	static uint8_t send[7];
 	send[0] = cmd | 0x40;
 	send[1] = param >> 24;
 	send[2] = param >> 16;
 	send[3] = param >> 8;
 	send[4] = param;
-	if (useCRC)
+	if (unlikely(useCRC))
 	{
 		send[5] = (sdCrc7(send, 5, 0) << 1) | 1;
 	}
@@ -115,31 +122,52 @@ static uint16_t sdDoCommand(
 	}
 	send[6] = 0xFF; // Result code or stuff byte.
 
-	CyDmaTdSetConfiguration(sdDMATxTd[0], sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);
-	CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));
-	CyDmaTdSetConfiguration(sdDMARxTd[0], sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
-	CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
+	static uint8_t dmaRxTd = CY_DMA_INVALID_TD;
+	static uint8_t dmaTxTd = CY_DMA_INVALID_TD;
+	if (unlikely(dmaRxTd == CY_DMA_INVALID_TD))
+	{
+		dmaRxTd = CyDmaTdAllocate();
+		dmaTxTd = CyDmaTdAllocate();
+		CyDmaTdSetConfiguration(dmaTxTd, sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);
+		CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));
+		CyDmaTdSetConfiguration(dmaRxTd, sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
+		CyDmaTdSetAddress(dmaRxTd, LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
+	}
+
+	sdTxDMAComplete = 0;
+	sdRxDMAComplete = 0;
+
+	CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd);
+	CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd);
+
+	// Some Samsung cards enter a busy-state after single-sector reads.
+	// But we also need to wait for R1B to complete from the multi-sector
+	// reads.
+	if (waitWhileBusy)
+	{
+		while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}
+		int busy = SDCard_ReadRxData() != 0xFF;
+		if (unlikely(busy))
+		{
+			while (sdSpiByte(0xFF) != 0xFF) {}
+		}
+	}
+
 	// The DMA controller is a bit trigger-happy. It will retain
 	// a drq request that was triggered while the channel was
 	// disabled.
 	CyDmaClearPendingDrq(sdDMATxChan);
 	CyDmaClearPendingDrq(sdDMARxChan);
 
-	txDMAComplete = 0;
-	rxDMAComplete = 0;
-
-	CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);
-	CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);
-
 	// There is no flow control, so we must ensure we can read the bytes
 	// before we start transmitting
 	CyDmaChEnable(sdDMARxChan, 1);
 	CyDmaChEnable(sdDMATxChan, 1);
 
-	while (!(txDMAComplete && rxDMAComplete)) {}
+	while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); }
 
 	uint16_t response = discardBuffer;
-	if (cmd == SD_STOP_TRANSMISSION)
+	if (unlikely(cmd == SD_STOP_TRANSMISSION))
 	{
 		// Stuff byte is required for this command only.
 		// Part 1 Simplified standard 3.01
@@ -149,11 +177,11 @@ static uint16_t sdDoCommand(
 	}
 
 	uint32_t start = getTime_ms();
-	while ((response & 0x80) && (diffTime_ms(start, getTime_ms()) <= 200))
+	while ((response & 0x80) && likely(elapsedTime_ms(start) <= 200))
 	{
 		response = sdSpiByte(0xFF);
 	}
-	if (use2byteResponse)
+	if (unlikely(use2byteResponse))
 	{
 		response = (response << 8) | sdSpiByte(0xFF);
 	}
@@ -161,21 +189,13 @@ static uint16_t sdDoCommand(
 }
 
 
-static uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)
+static inline uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)
 {
-	// Some Samsung cards enter a busy-state after single-sector reads.
-	// But we also need to wait for R1B to complete from the multi-sector
-	// reads.
-	while (sdSpiByte(0xFF) == 0x00) {}
 	return sdDoCommand(cmd, param, 0, 0);
 }
 
-static uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)
+static inline uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)
 {
-	// Some Samsung cards enter a busy-state after single-sector reads.
-	// But we also need to wait for R1B to complete from the multi-sector
-	// reads.
-	while (sdSpiByte(0xFF) == 0x00) {}
 	return sdDoCommand(cmd, param, 1, 0);
 }
 
@@ -203,14 +223,14 @@ sdReadMultiSectorPrep()
 		sdLBA = sdLBA * SD_SECTOR_SIZE;
 	}
 	v = sdCommandAndResponse(SD_READ_MULTIPLE_BLOCK, sdLBA);
-	if (v)
+	if (unlikely(v))
 	{
 		scsiDiskReset();
 		sdClearStatus();
 
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE;
+		scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
 		scsiDev.phase = STATUS;
 	}
 	else
@@ -226,16 +246,16 @@ dmaReadSector(uint8_t* outputBuffer)
 	// Don't wait more than 200ms.  The standard recommends 100ms.
 	uint32_t start = getTime_ms();
 	uint8_t token = sdSpiByte(0xFF);
-	while (token != 0xFE && (diffTime_ms(start, getTime_ms()) <= 200))
+	while (token != 0xFE && likely(elapsedTime_ms(start) <= 200))
 	{
-		if (token && ((token & 0xE0) == 0))
+		if (unlikely(token && ((token & 0xE0) == 0)))
 		{
 			// Error token!
 			break;
 		}
 		token = sdSpiByte(0xFF);
 	}
-	if (token != 0xFE)
+	if (unlikely(token != 0xFE))
 	{
 		if (transfer.multiBlock)
 		{
@@ -245,31 +265,41 @@ dmaReadSector(uint8_t* outputBuffer)
 		{
 			scsiDev.status = CHECK_CONDITION;
 			scsiDev.target->sense.code = HARDWARE_ERROR;
-			scsiDev.target->sense.asc = 0x4400 | token;
+			scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;
 			scsiDev.phase = STATUS;
 		}
 		sdClearStatus();
 		return;
 	}
 
-	// Receive 512 bytes of data and then 2 bytes CRC.
-	CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, sdDMARxTd[1], TD_INC_DST_ADR);
-	CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer));
-	CyDmaTdSetConfiguration(sdDMARxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
-	CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
+	static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
+	static uint8_t dmaTxTd = CY_DMA_INVALID_TD;
+	if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD))
+	{
+		dmaRxTd[0] = CyDmaTdAllocate();
+		dmaRxTd[1] = CyDmaTdAllocate();
+		dmaTxTd = CyDmaTdAllocate();
+		
+		// Receive 512 bytes of data and then 2 bytes CRC.
+		CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE, dmaRxTd[1], TD_INC_DST_ADR);
+		CyDmaTdSetConfiguration(dmaRxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
+		CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
+	
+		CyDmaTdSetConfiguration(dmaTxTd, SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
+		CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
 
-	CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
-	CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
+	}
+	CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer));
 
 	sdIOState = SD_DMA;
-	txDMAComplete = 0;
-	rxDMAComplete = 0;
+	sdTxDMAComplete = 0;
+	sdRxDMAComplete = 0;
 
 	// Re-loading the initial TD's here is very important, or else
 	// we'll be re-using the last-used TD, which would be the last
 	// in the chain (ie. CRC TD)
-	CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);
-	CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);
+	CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]);
+	CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd);
 
 	// The DMA controller is a bit trigger-happy. It will retain
 	// a drq request that was triggered while the channel was
@@ -286,7 +316,7 @@ dmaReadSector(uint8_t* outputBuffer)
 int
 sdReadSectorDMAPoll()
 {
-	if (rxDMAComplete && txDMAComplete)
+	if (sdRxDMAComplete && sdTxDMAComplete)
 	{
 		// DMA transfer is complete
 		sdIOState = SD_IDLE;
@@ -306,14 +336,14 @@ void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer)
 		lba = lba * SD_SECTOR_SIZE;
 	}
 	v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, lba);
-	if (v)
+	if (unlikely(v))
 	{
 		scsiDiskReset();
 		sdClearStatus();
 
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION;
+		scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
 		scsiDev.phase = STATUS;
 	}
 	else
@@ -332,29 +362,26 @@ sdReadMultiSectorDMA(uint8_t* outputBuffer)
 
 void sdCompleteRead()
 {
-	if (sdIOState != SD_IDLE)
+	if (unlikely(sdIOState != SD_IDLE))
 	{
 		// Not much choice but to wait until we've completed the transfer.
 		// Cancelling the transfer can't be done as we have no way to reset
 		// the SD card.
 		while (!sdReadSectorDMAPoll()) { /* spin */ }
 	}
-	transfer.inProgress = 0;
-
-	// We cannot send even a single "padding" byte, as we normally would when
-	// sending a command.  If we've just finished reading the very last block
-	// on the card, then reading an additional dummy byte will just trigger
-	// an error condition as we're trying to read past-the-end of the storage
-	// device.
-	// ie. do not use sdCommandAndResponse here.
-	uint8 r1b = sdDoCommand(SD_STOP_TRANSMISSION, 0, 0, 0);
-
-	if (r1b)
+	
+	if (transfer.inProgress)
 	{
-		scsiDev.status = CHECK_CONDITION;
-		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR | r1b;
-		scsiDev.phase = STATUS;
+		transfer.inProgress = 0;
+		uint8 r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);
+
+		if (unlikely(r1b))
+		{
+			scsiDev.status = CHECK_CONDITION;
+			scsiDev.target->sense.code = HARDWARE_ERROR;
+			scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;
+			scsiDev.phase = STATUS;
+		}
 	}
 
 	// R1b has an optional trailing "busy" signal, but we defer waiting on this.
@@ -374,22 +401,34 @@ static void sdWaitWriteBusy()
 void
 sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 {
-	// Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte
-	// We need to do this without stopping the clock
-	CyDmaTdSetConfiguration(sdDMATxTd[0], 1, sdDMATxTd[1], TD_INC_SRC_ADR);
-	CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));
+	static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
+	static uint8_t dmaTxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD};
+	if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD))
+	{
+		dmaRxTd[0] = CyDmaTdAllocate();
+		dmaRxTd[1] = CyDmaTdAllocate();
+		dmaTxTd[0] = CyDmaTdAllocate();
+		dmaTxTd[1] = CyDmaTdAllocate();
+		dmaTxTd[2] = CyDmaTdAllocate();
+		
+		// Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte
+		// We need to do this without stopping the clock
+		CyDmaTdSetConfiguration(dmaTxTd[0], 1, dmaTxTd[1], TD_INC_SRC_ADR);
+		CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));
 
-	CyDmaTdSetConfiguration(sdDMATxTd[1], SD_SECTOR_SIZE, sdDMATxTd[2], TD_INC_SRC_ADR);
-	CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));
+		CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR);
+
+		CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
+		CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
+
+		CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 3, dmaRxTd[1], 0);
+		CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
+		CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);
+		CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));
+	}
+	CyDmaTdSetAddress(dmaTxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));
 
-	CyDmaTdSetConfiguration(sdDMATxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
-	CyDmaTdSetAddress(sdDMATxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
 
-	CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 3, sdDMARxTd[1], 0);
-	CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
-	CyDmaTdSetConfiguration(sdDMARxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);
-	CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));
-	
 	sdIOState = SD_DMA;
 	// The DMA controller is a bit trigger-happy. It will retain
 	// a drq request that was triggered while the channel was
@@ -397,14 +436,14 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 	CyDmaClearPendingDrq(sdDMATxChan);
 	CyDmaClearPendingDrq(sdDMARxChan);
 
-	txDMAComplete = 0;
-	rxDMAComplete = 0;
+	sdTxDMAComplete = 0;
+	sdRxDMAComplete = 0;
 
 	// Re-loading the initial TD's here is very important, or else
 	// we'll be re-using the last-used TD, which would be the last
 	// in the chain (ie. CRC TD)
-	CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);
-	CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);
+	CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]);
+	CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd[0]);
 
 	// There is no flow control, so we must ensure we can read the bytes
 	// before we start transmitting
@@ -415,7 +454,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 int
 sdWriteSectorDMAPoll(int sendStopToken)
 {
-	if (rxDMAComplete && txDMAComplete)
+	if (sdRxDMAComplete && sdTxDMAComplete)
 	{
 		if (sdIOState == SD_DMA)
 		{
@@ -431,7 +470,7 @@ sdWriteSectorDMAPoll(int sendStopToken)
 
 			// At this point we should either have an accepted token, or we'll
 			// timeout and proceed into the error case below.
-			if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.
+			if (unlikely(((dataToken & 0x1F) >> 1) != 0x2)) // Accepted.
 			{
 				sdIOState = SD_IDLE;
 
@@ -445,7 +484,7 @@ sdWriteSectorDMAPoll(int sendStopToken)
 
 				scsiDev.status = CHECK_CONDITION;
 				scsiDev.target->sense.code = HARDWARE_ERROR;
-				scsiDev.target->sense.asc = 0x6900 | dataToken;
+				scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
 				scsiDev.phase = STATUS;
 			}
 			else
@@ -492,7 +531,7 @@ sdWriteSectorDMAPoll(int sendStopToken)
 
 void sdCompleteWrite()
 {
-	if (sdIOState != SD_IDLE)
+	if (unlikely(sdIOState != SD_IDLE))
 	{
 		// Not much choice but to wait until we've completed the transfer.
 		// Cancelling the transfer can't be done as we have no way to reset
@@ -500,13 +539,10 @@ void sdCompleteWrite()
 		while (!sdWriteSectorDMAPoll(1)) { /* spin */ }
 	}
 
-	transfer.inProgress = 0;
-
-	if (scsiDev.phase == DATA_OUT)
+	if (transfer.inProgress && likely(scsiDev.phase == DATA_OUT))
 	{
-		sdSpiByte(0xFF);
 		uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 0, 1);
-		if (r2)
+		if (unlikely(r2))
 		{
 			sdClearStatus();
 			scsiDev.status = CHECK_CONDITION;
@@ -515,6 +551,7 @@ void sdCompleteWrite()
 			scsiDev.phase = STATUS;
 		}
 	}
+	transfer.inProgress = 0;
 }
 
 
@@ -569,7 +606,7 @@ static int sdOpCond()
 		sdClearStatus();
 
 	// Spec says to poll for 1 second.
-	} while ((status != 0) && (diffTime_ms(start, getTime_ms()) < 1000));
+	} while ((status != 0) && (elapsedTime_ms(start) < 1000));
 
 	return status == 0;
 }
@@ -598,7 +635,7 @@ static int sdReadOCR()
 
 	} while (!status &&
 		!complete &&
-		(diffTime_ms(start, getTime_ms()) < 1000));
+		(elapsedTime_ms(start) < 1000));
 
 	return (status == 0) && complete;
 }
@@ -702,12 +739,6 @@ static void sdInitDMA()
 		CyDmaChDisable(sdDMATxChan);
 		CyDmaChDisable(sdDMARxChan);
 
-		sdDMARxTd[0] = CyDmaTdAllocate();
-		sdDMARxTd[1] = CyDmaTdAllocate();
-		sdDMATxTd[0] = CyDmaTdAllocate();
-		sdDMATxTd[1] = CyDmaTdAllocate();
-		sdDMATxTd[2] = CyDmaTdAllocate();
-
 		SD_RX_DMA_COMPLETE_StartEx(sdRxISR);
 		SD_TX_DMA_COMPLETE_StartEx(sdTxISR);
 	}
@@ -791,6 +822,7 @@ int sdInit()
 	goto out;
 
 bad:
+	SD_Data_Clk_SetDivider(clkDiv25MHz); // Restore the clock for our next retry
 	sdDev.capacity = 0;
 
 out:
@@ -826,13 +858,13 @@ void sdWriteMultiSectorPrep()
 		sdLBA = sdLBA * SD_SECTOR_SIZE;
 	}
 	v = sdCommandAndResponse(SD_WRITE_MULTIPLE_BLOCK, sdLBA);
-	if (v)
+	if (unlikely(v))
 	{
 		scsiDiskReset();
 		sdClearStatus();
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = 0x8800 | v;
+		scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
 		scsiDev.phase = STATUS;
 	}
 	else
@@ -854,7 +886,7 @@ void sdPoll()
 		// overpower the SD pullup resistor.
 		SD_CS_Write(0);
 		SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ);
-		
+
 		CyDelayCycles(64);
 		uint8_t cs = SD_CS_Read();
 		SD_CS_SetDriveMode(SD_CS_DM_STRONG)	;
@@ -862,14 +894,14 @@ void sdPoll()
 		if (cs && !(blockDev.state & DISK_PRESENT))
 		{
 			static int firstInit = 1;
-		
+
 			// Debounce
 			CyDelay(250);
-			
+
 			if (sdInit())
 			{
 				blockDev.state |= DISK_PRESENT | DISK_INITIALISED;
-				
+
 				if (!firstInit)
 				{
 					int i;
@@ -894,3 +926,5 @@ void sdPoll()
 		}
 	}
 }
+
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/sd.h

@@ -61,9 +61,13 @@ typedef struct
 } SdDevice;
 
 extern SdDevice sdDev;
+extern volatile uint8_t sdRxDMAComplete;
+extern volatile uint8_t sdTxDMAComplete;
 
 int sdInit(void);
 
+#define sdDMABusy() (!(sdRxDMAComplete && sdTxDMAComplete))
+
 void sdWriteMultiSectorPrep(void);
 void sdWriteMultiSectorDMA(uint8_t* outputBuffer);
 int sdWriteSectorDMAPoll(int sendStopToken);

lib/SCSI2SD/software/SCSI2SD/src/time.c

@@ -14,6 +14,8 @@
 //
 //	You should have received a copy of the GNU General Public License
 //	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#pragma GCC push_options
+#pragma GCC optimize("-flto")
 
 #include "time.h"
 #include "limits.h"
@@ -54,3 +56,18 @@ uint32_t diffTime_ms(uint32_t start, uint32_t end)
 		return (UINT_MAX - start) + end;
 	}
 }
+
+uint32_t elapsedTime_ms(uint32_t since)
+{
+	uint32_t now = counter;
+	if (now >= since)
+	{
+		return now - since;
+	}
+	else
+	{
+		return (UINT_MAX - since) + now;
+	}
+}
+
+#pragma GCC pop_options

lib/SCSI2SD/software/SCSI2SD/src/time.h

@@ -22,5 +22,6 @@
 void timeInit(void);
 uint32_t getTime_ms(void); // Returns milliseconds since init
 uint32_t diffTime_ms(uint32_t start, uint32_t end);
+uint32_t elapsedTime_ms(uint32_t since);
 
 #endif

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h

@@ -381,32 +381,32 @@
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
 
 /* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
 #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
 #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
@@ -419,29 +419,29 @@
 #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
 #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
 #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
 #define SDCard_BSPIM_TxStsReg__0__POS 0
 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
 #define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
 #define SDCard_BSPIM_TxStsReg__2__POS 2
 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@@ -449,9 +449,9 @@
 #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
 #define SDCard_BSPIM_TxStsReg__4__POS 4
 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST
 
 /* SD_SCK */
 #define SD_SCK__0__MASK 0x04u
@@ -1909,24 +1909,24 @@
 /* SCSI_Out_Ctl */
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
 #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
 
 /* SCSI_Out_DBx */
 #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
@@ -2366,7 +2366,7 @@
 #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
 #define SD_RX_DMA__DRQ_NUMBER 2u
 #define SD_RX_DMA__NUMBEROF_TDS 0u
-#define SD_RX_DMA__PRIORITY 2u
+#define SD_RX_DMA__PRIORITY 0u
 #define SD_RX_DMA__TERMIN_EN 0u
 #define SD_RX_DMA__TERMIN_SEL 0u
 #define SD_RX_DMA__TERMOUT0_EN 1u
@@ -2388,7 +2388,7 @@
 #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
 #define SD_TX_DMA__DRQ_NUMBER 3u
 #define SD_TX_DMA__NUMBEROF_TDS 0u
-#define SD_TX_DMA__PRIORITY 2u
+#define SD_TX_DMA__PRIORITY 1u
 #define SD_TX_DMA__TERMIN_EN 0u
 #define SD_TX_DMA__TERMIN_SEL 0u
 #define SD_TX_DMA__TERMOUT0_EN 1u
@@ -2677,57 +2677,57 @@
 #define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW
 
 /* scsiTarget */
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB05_06_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB05_06_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB05_06_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB05_06_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB05_06_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB05_06_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB05_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB05_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB05_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB05_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB05_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB05_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB05_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB05_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB05_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB05_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB05_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB05_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB05_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB05_MSK
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK
 #define scsiTarget_StatusReg__0__MASK 0x01u
 #define scsiTarget_StatusReg__0__POS 0
 #define scsiTarget_StatusReg__1__MASK 0x02u
 #define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
 #define scsiTarget_StatusReg__2__MASK 0x04u
 #define scsiTarget_StatusReg__2__POS 2
 #define scsiTarget_StatusReg__3__MASK 0x08u
@@ -2735,13 +2735,9 @@
 #define scsiTarget_StatusReg__4__MASK 0x10u
 #define scsiTarget_StatusReg__4__POS 4
 #define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST
 
 /* Debug_Timer_Interrupt */
 #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -2852,8 +2848,8 @@
 #define SCSI_Filtered_sts_sts_reg__0__POS 0
 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
 #define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST
 #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
 #define SCSI_Filtered_sts_sts_reg__2__POS 2
 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@@ -2861,49 +2857,45 @@
 #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
 #define SCSI_Filtered_sts_sts_reg__4__POS 4
 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST
 
 /* SCSI_CTL_PHASE */
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
 #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
 
 /* SCSI_Parity_Error */
 #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
 #define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
 #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
 
 /* Miscellaneous */
 #define BCLK__BUS_CLK__HZ 50000000U

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc

@@ -381,32 +381,32 @@
 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
 
 /* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
 .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
 .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
 .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
@@ -419,29 +419,29 @@
 .set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
 .set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
 .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
 .set SDCard_BSPIM_TxStsReg__0__POS, 0
 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
 .set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
 .set SDCard_BSPIM_TxStsReg__2__POS, 2
 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@@ -449,9 +449,9 @@
 .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
 .set SDCard_BSPIM_TxStsReg__4__POS, 4
 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST
 
 /* SD_SCK */
 .set SD_SCK__0__MASK, 0x04
@@ -1909,24 +1909,24 @@
 /* SCSI_Out_Ctl */
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
 .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
 
 /* SCSI_Out_DBx */
 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
@@ -2366,7 +2366,7 @@
 .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
 .set SD_RX_DMA__DRQ_NUMBER, 2
 .set SD_RX_DMA__NUMBEROF_TDS, 0
-.set SD_RX_DMA__PRIORITY, 2
+.set SD_RX_DMA__PRIORITY, 0
 .set SD_RX_DMA__TERMIN_EN, 0
 .set SD_RX_DMA__TERMIN_SEL, 0
 .set SD_RX_DMA__TERMOUT0_EN, 1
@@ -2388,7 +2388,7 @@
 .set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
 .set SD_TX_DMA__DRQ_NUMBER, 3
 .set SD_TX_DMA__NUMBEROF_TDS, 0
-.set SD_TX_DMA__PRIORITY, 2
+.set SD_TX_DMA__PRIORITY, 1
 .set SD_TX_DMA__TERMIN_EN, 0
 .set SD_TX_DMA__TERMIN_SEL, 0
 .set SD_TX_DMA__TERMOUT0_EN, 1
@@ -2677,57 +2677,57 @@
 .set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW
 
 /* scsiTarget */
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB05_06_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB05_06_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB05_06_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB05_06_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB05_06_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB05_06_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB05_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB05_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB05_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB05_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB05_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB05_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB05_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB05_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB05_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB05_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB05_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB05_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB05_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB05_MSK
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB00_01_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB00_01_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB00_01_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB00_01_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB00_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB00_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB00_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB00_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB00_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB00_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB00_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB00_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB00_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB00_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB00_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB00_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB00_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB00_MSK
 .set scsiTarget_StatusReg__0__MASK, 0x01
 .set scsiTarget_StatusReg__0__POS, 0
 .set scsiTarget_StatusReg__1__MASK, 0x02
 .set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
 .set scsiTarget_StatusReg__2__MASK, 0x04
 .set scsiTarget_StatusReg__2__POS, 2
 .set scsiTarget_StatusReg__3__MASK, 0x08
@@ -2735,13 +2735,9 @@
 .set scsiTarget_StatusReg__4__MASK, 0x10
 .set scsiTarget_StatusReg__4__POS, 4
 .set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST
 
 /* Debug_Timer_Interrupt */
 .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -2852,8 +2848,8 @@
 .set SCSI_Filtered_sts_sts_reg__0__POS, 0
 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
 .set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST
 .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
 .set SCSI_Filtered_sts_sts_reg__2__POS, 2
 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@@ -2861,49 +2857,45 @@
 .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
 .set SCSI_Filtered_sts_sts_reg__4__POS, 4
 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST
 
 /* SCSI_CTL_PHASE */
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
 .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
 
 /* SCSI_Parity_Error */
 .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
 .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
 
 /* Miscellaneous */
 .set BCLK__BUS_CLK__HZ, 50000000

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc

@@ -381,32 +381,32 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
 /* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
 SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
 SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
@@ -419,29 +419,29 @@ SDCard_BSPIM_RxStsReg__MASK EQU 0x70
 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
 SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
 SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
 SDCard_BSPIM_TxStsReg__2__POS EQU 2
 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -449,9 +449,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
 
 /* SD_SCK */
 SD_SCK__0__MASK EQU 0x04
@@ -1909,24 +1909,24 @@ SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
 /* SCSI_Out_Ctl */
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
 
 /* SCSI_Out_DBx */
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@@ -2366,7 +2366,7 @@ SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
 SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
 SD_RX_DMA__DRQ_NUMBER EQU 2
 SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 2
+SD_RX_DMA__PRIORITY EQU 0
 SD_RX_DMA__TERMIN_EN EQU 0
 SD_RX_DMA__TERMIN_SEL EQU 0
 SD_RX_DMA__TERMOUT0_EN EQU 1
@@ -2388,7 +2388,7 @@ SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
 SD_TX_DMA__DRQ_NUMBER EQU 3
 SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 2
+SD_TX_DMA__PRIORITY EQU 1
 SD_TX_DMA__TERMIN_EN EQU 0
 SD_TX_DMA__TERMIN_SEL EQU 0
 SD_TX_DMA__TERMOUT0_EN EQU 1
@@ -2677,57 +2677,57 @@ SCSI_Noise__SEL__SHIFT EQU 0
 SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW
 
 /* scsiTarget */
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB05_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB05_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB05_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB05_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB05_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB05_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB05_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB05_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB05_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB05_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB05_MSK
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK
 scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2735,13 +2735,9 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
 
 /* Debug_Timer_Interrupt */
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2852,8 +2848,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2861,49 +2857,45 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST
 
 /* SCSI_CTL_PHASE */
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
 
 /* SCSI_Parity_Error */
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
 
 /* Miscellaneous */
 BCLK__BUS_CLK__HZ EQU 50000000

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc

@@ -381,32 +381,32 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
 ; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
 SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
 SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
 SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
@@ -419,29 +419,29 @@ SDCard_BSPIM_RxStsReg__MASK EQU 0x70
 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
 SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
 SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
 SDCard_BSPIM_TxStsReg__0__POS EQU 0
 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
 SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
 SDCard_BSPIM_TxStsReg__2__POS EQU 2
 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -449,9 +449,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
 SDCard_BSPIM_TxStsReg__4__POS EQU 4
 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
 
 ; SD_SCK
 SD_SCK__0__MASK EQU 0x04
@@ -1909,24 +1909,24 @@ SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
 ; SCSI_Out_Ctl
 SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
 SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
 
 ; SCSI_Out_DBx
 SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@@ -2366,7 +2366,7 @@ SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
 SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
 SD_RX_DMA__DRQ_NUMBER EQU 2
 SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 2
+SD_RX_DMA__PRIORITY EQU 0
 SD_RX_DMA__TERMIN_EN EQU 0
 SD_RX_DMA__TERMIN_SEL EQU 0
 SD_RX_DMA__TERMOUT0_EN EQU 1
@@ -2388,7 +2388,7 @@ SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
 SD_TX_DMA__DRQ_NUMBER EQU 3
 SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 2
+SD_TX_DMA__PRIORITY EQU 1
 SD_TX_DMA__TERMIN_EN EQU 0
 SD_TX_DMA__TERMIN_SEL EQU 0
 SD_TX_DMA__TERMOUT0_EN EQU 1
@@ -2677,57 +2677,57 @@ SCSI_Noise__SEL__SHIFT EQU 0
 SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW
 
 ; scsiTarget
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB05_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB05_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB05_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB05_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB05_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB05_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB05_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB05_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB05_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB05_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB05_MSK
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK
 scsiTarget_StatusReg__0__MASK EQU 0x01
 scsiTarget_StatusReg__0__POS EQU 0
 scsiTarget_StatusReg__1__MASK EQU 0x02
 scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
 scsiTarget_StatusReg__2__MASK EQU 0x04
 scsiTarget_StatusReg__2__POS EQU 2
 scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2735,13 +2735,9 @@ scsiTarget_StatusReg__3__POS EQU 3
 scsiTarget_StatusReg__4__MASK EQU 0x10
 scsiTarget_StatusReg__4__POS EQU 4
 scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
 
 ; Debug_Timer_Interrupt
 Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2852,8 +2848,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Filtered_sts_sts_reg__0__POS EQU 0
 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
 SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
 SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
 SCSI_Filtered_sts_sts_reg__2__POS EQU 2
 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2861,49 +2857,45 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
 SCSI_Filtered_sts_sts_reg__4__POS EQU 4
 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST
 
 ; SCSI_CTL_PHASE
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
 SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
 
 ; SCSI_Parity_Error
 SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
 SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
 
 ; Miscellaneous
 BCLK__BUS_CLK__HZ EQU 50000000

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c

@@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
 const uint8 cy_meta_loadable[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x10u, 0x04u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x20u, 0x04u,
     0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx

@@ -11,7 +11,7 @@
   </block>
   <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
   </block>
   <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
@@ -82,9 +82,9 @@
   <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Filtered_STATUS_REG" address="0x4000646C" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_MASK_REG" address="0x4000648C" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649C" bitWidth="8" desc="">
+    <register name="SCSI_Filtered_STATUS_REG" address="0x4000646D" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_MASK_REG" address="0x4000648D" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649D" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -112,9 +112,9 @@
     </register>
   </block>
   <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006466" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_MASK_REG" address="0x40006486" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006496" bitWidth="8" desc="">
+    <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -144,7 +144,7 @@
   <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
   </block>
   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj

@@ -3355,7 +3355,7 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
 </name>

lib/SCSI2SD/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd

@@ -30,7 +30,7 @@
     <peripheral>
       <name>SCSI_Out_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x4000647D</baseAddress>
+      <baseAddress>0x40006478</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -343,7 +343,7 @@
     <peripheral>
       <name>SCSI_Filtered</name>
       <description>No description available</description>
-      <baseAddress>0x4000646C</baseAddress>
+      <baseAddress>0x4000646D</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -498,7 +498,7 @@
     <peripheral>
       <name>SCSI_Parity_Error</name>
       <description>No description available</description>
-      <baseAddress>0x40006466</baseAddress>
+      <baseAddress>0x40006465</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>
@@ -653,7 +653,7 @@
     <peripheral>
       <name>SCSI_CTL_PHASE</name>
       <description>No description available</description>
-      <baseAddress>0x4000647C</baseAddress>
+      <baseAddress>0x40006472</baseAddress>
       <addressBlock>
         <offset>0</offset>
         <size>0x0</size>

lib/SCSI2SD/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj

@@ -2483,7 +2483,7 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Struct Return Method" v="System Default" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
@@ -2497,7 +2497,7 @@
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
 </name>

lib/SCSI2SD/software/include/scsi2sd.h

@@ -95,6 +95,12 @@ typedef enum
 	CONFIG_FLOPPY_14MB
 } CONFIG_TYPE;
 
+typedef enum
+{
+	CONFIG_QUIRKS_NONE,
+	CONFIG_QUIRKS_APPLE
+} CONFIG_QUIRKS;
+
 typedef struct __attribute__((packed))
 {
 	uint8_t deviceType;
@@ -112,7 +118,7 @@ typedef struct __attribute__((packed))
 
 	uint8_t deviceType; // CONFIG_TYPE
 	uint8_t flags; // CONFIG_FLAGS
-	uint8_t pad0;
+	uint8_t deviceTypeModifier; // Used in INQUIRY response.
 
 	uint32_t sdSectorStart;
 	uint32_t scsiSectors;
@@ -131,7 +137,9 @@ typedef struct __attribute__((packed))
 	char revision[4];
 	char serial[16];
 
-	uint8_t reserved[962]; // Pad out to 1024 bytes for main section.
+	uint16_t quirks; // CONFIG_QUIRKS
+
+	uint8_t reserved[960]; // Pad out to 1024 bytes for main section.
 
 	uint8_t vpd[3072]; // Total size is 4k.
 } TargetConfig;

lib/SCSI2SD/software/scsi2sd-util/ConfigUtil.cc

@@ -24,6 +24,7 @@
 
 using namespace SCSI2SD;
 
+ADD QUIRKS MODES
 namespace
 {
 	// Endian conversion routines.
@@ -93,7 +94,7 @@ ConfigUtil::Default(size_t targetIdx)
 
 	// Default to maximum fail-safe options.
 	config.flags = 0;// CONFIG_ENABLE_PARITY | CONFIG_ENABLE_UNIT_ATTENTION;
-	config.pad0 = 0;
+	config.deviceTypeModifier = 0;
 	config.sdSectorStart = 0;
 
 	// Default to 2GB. Many systems have trouble with > 2GB disks, and
@@ -145,3 +146,60 @@ ConfigUtil::toBytes(const TargetConfig& _config)
 	return std::vector<uint8_t>(begin, begin + sizeof(config));
 }
 
+wxXmlNode*
+ConfigUtil::toXML(const TargetConfig& config)
+{
+	wxXmlNode* target = new wxXmlNode(wxXML_ELEMENT_NODE, "SCSITarget");
+
+	{
+		std::stringstream s; s << scsiId & CONFIG_TARGET_ID_BITS;
+		target.AddAttribute("id", s.str());
+	}
+	{
+		std::stringstream s; s << config.deviceType;
+		new wxXmlNode(
+			new wxXmlNode(target, wxXML_ELEMENT_NODE, "deviceType"),
+			wxXML_TEXT_NODE, "", s.str());
+	}
+
+	{
+		std::stringstream s; s << "0x" << std::hex << config.deviceTypeModifier;
+		new wxXmlNode(
+			new wxXmlNode(target, wxXML_ELEMENT_NODE, "deviceTypeModifier"),
+			wxXML_TEXT_NODE, "", s.str());
+	}
+
+	wxXmlNode* flags(new wxXmlNode(target, wxXML_ELEMENT_NODE, "flags"));
+
+	new wxXmlNode(
+		new wxXmlNode(flags, wxXML_ELEMENT_NODE, "enabled"),
+		wxXML_TEXT_NODE,
+		"",
+		config.scsiId & CONFIG_TARGET_ENABLED ? "true" : "false");
+
+				"<unitAttention>" <<
+					(config.flags & CONFIG_ENABLE_UNIT_ATTENTION ? "true" : "false") <<
+				"</unitAttention>\n" <<
+				"<parity>" <<
+					(config.flags & CONFIG_ENABLE_PARITY ? "true" : "false") <<
+				"</parity>\n" <<
+
+			"<sdSectorStart>" << config.sdSectorStart << "</sdSectorStart>\n" <<
+			"<scsiSectors>" << config.scsiSectors << "</scsiSectors>\n" <<
+			"<bytesPerSector>" << config.bytesPerSector << "</bytesPerSector>\n" <<
+			"<sectorsPerTrack>" << config.sectorsPerTrack<< "</sectorsPerTrack>\n" <<
+			"<headsPerCylinder>" << config.headsPerCylinder << "</headsPerCylinder>\n" <<
+
+			"<vendor>" << std::string(config.vendor, 8) << "</vendor>" <<
+			"<prodId>" << std::string(config.prodId, 16) << "</prodId>" <<
+			"<revision>" << std::string(config.revision, 4) << "</revision>" <<
+			"<serial>" << std::string(config.serial, 16) << "</serial>" <<
+
+		"</SCSITarget>";
+}
+
+void
+ConfigUtil::deserialise(const std::string& in)
+{
+
+}

lib/SCSI2SD/software/scsi2sd-util/SCSI2SD_HID.cc

@@ -404,7 +404,7 @@ HID::sendHIDPacket(
 	size_t respLen;
 	resp = hidPacket_getPacket(&respLen);
 
-	for (int retry = 0; retry < responseLength * 2 && !resp; ++retry)
+	for (unsigned int retry = 0; retry < responseLength * 2 && !resp; ++retry)
 	{
 		readHID(hidBuf, sizeof(hidBuf)); // Will block
 		hidPacket_recv(hidBuf, HID_PACKET_SIZE);

lib/SCSI2SD/software/scsi2sd-util/scsi2sd-util.cc

@@ -849,10 +849,12 @@ private:
 		return;
 	}
 
-	void OnExit(wxCommandEvent& event)
+	// Note: Don't confuse this with the wxApp::OnExit virtual method
+	void OnExitEvt(wxCommandEvent& event)
 	{
 		Close(true);
 	}
+
 	void OnAbout(wxCommandEvent& event)
 	{
 		wxMessageBox(
@@ -882,7 +884,7 @@ wxBEGIN_EVENT_TABLE(AppFrame, wxFrame)
 	EVT_MENU(AppFrame::ID_ConfigDefaults, AppFrame::OnID_ConfigDefaults)
 	EVT_MENU(AppFrame::ID_Firmware, AppFrame::OnID_Firmware)
 	EVT_MENU(AppFrame::ID_LogWindow, AppFrame::OnID_LogWindow)
-	EVT_MENU(wxID_EXIT, AppFrame::OnExit)
+	EVT_MENU(wxID_EXIT, AppFrame::OnExitEvt)
 	EVT_MENU(wxID_ABOUT, AppFrame::OnAbout)
 
 	EVT_TIMER(AppFrame::ID_Timer, AppFrame::OnID_Timer)