f7: Enable data cache.

inc/stm32/f7.h

@@ -10,6 +10,7 @@
  */
 
 /* C pointer types */
+#define CPUFEAT volatile struct cpufeat * const
 #define CACHE volatile struct cache * const
 #define SYSCFG volatile struct syscfg * const
 #define DMA_STR volatile struct dma_str * const
@@ -20,6 +21,7 @@ static STK stk = (struct stk *)STK_BASE;
 static SCB scb = (struct scb *)SCB_BASE;
 static NVIC nvic = (struct nvic *)NVIC_BASE;
 static DBG dbg = (struct dbg *)DBG_BASE;
+static CPUFEAT cpufeat = (struct cpufeat *)CPUFEAT_BASE;
 static CACHE cache = (struct cache *)CACHE_BASE;
 static FLASH flash = (struct flash *)FLASH_BASE;
 static PWR pwr = (struct pwr *)PWR_BASE;

inc/stm32/f7_regs.h

@@ -18,6 +18,18 @@ struct dbg {
 
 #define DBG_BASE 0xe0042000
 
+struct cpufeat {
+    uint32_t clidr;      /* 00: Cache level ID */
+    uint32_t ctr;        /* 04: Cache type */
+    uint32_t ccsidr;     /* 08: Cache size ID */
+    uint32_t csselr;     /* 10: Cache size selection */
+};
+
+#define CCSIDR_SETS(x) (((x)>>13)&0x7fffu)
+#define CCSIDR_WAYS(x) (((x)>> 3)& 0x3ffu)
+
+#define CPUFEAT_BASE 0xe000ed78
+
 struct cache {
     uint32_t iciallu;    /* 00: ICache invalidate all to PoU */
     uint32_t _unused0;
@@ -32,6 +44,9 @@ struct cache {
     uint32_t bpiall;
 };
 
+#define DCISW_WAY(x)  ((x)<<30)
+#define DCISW_SET(x)  ((x)<< 5)
+
 #define CACHE_BASE 0xe000ef50    
 
 /* Flash memory interface */

src/stm32f7.c

@@ -66,6 +66,31 @@ static void icache_enable(void)
     cpu_sync(); 
 }
 
+static void dcache_invalidate_all(void)
+{
+    uint32_t ccsidr;
+    unsigned int sets, ways;
+
+    cpufeat->csselr = 0; /* L1 DCache */
+    cpu_sync();
+    ccsidr = cpufeat->ccsidr;
+    sets = CCSIDR_SETS(ccsidr);
+    do {
+        ways = CCSIDR_WAYS(ccsidr);
+        do {
+            cache->dcisw = DCISW_SET(sets) | DCISW_WAY(ways);
+        } while (ways--);
+    } while (sets--);
+    cpu_sync();
+}
+
+static void dcache_enable(void)
+{
+    dcache_invalidate_all();
+    scb->ccr |= SCB_CCR_DC;
+    cpu_sync();
+}
+
 void peripheral_clock_delay(void)
 {
     delay_ticks(2);
@@ -94,6 +119,7 @@ void stm32_init(void)
     cortex_init();
     clock_init();
     icache_enable();
+    dcache_enable();
     peripheral_init();
     cpu_sync();
 }