Clean up Quartus version-dependent files

*.qip-files are apparently version dependent in a bad way. Remove them.

.gitignore

@@ -10,3 +10,4 @@ greybox_tmp/
 *.cmp
 *.inc
 *.ppf
+*.qip

ip/hdmitx.qip

@@ -1,10 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTLVDS_TX"
-set_global_assignment -name IP_TOOL_VERSION "18.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hdmitx.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx_inst.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx_bb.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmitx.ppf"]

ip/pll.qip

@@ -1,8 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "18.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

max80.qsf

@@ -116,11 +116,6 @@ set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
-set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
-set_global_assignment -name SDC_FILE max80.sdc
-set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
-set_global_assignment -name QIP_FILE ip/pll.qip
-set_global_assignment -name QIP_FILE ip/hdmitx.qip
 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
@@ -131,149 +126,156 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_miso
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_mosi
 set_instance_assignment -name IO_STANDARD "2.5 V" -to clock_48
-set_location_assignment PIN_A2 -to "abc_int800_x"
-set_location_assignment PIN_A3 -to "abc_nmi_x"
-set_location_assignment PIN_A4 -to "sr_dq[11]"
-set_location_assignment PIN_A5 -to "sr_dq[8]"
-set_location_assignment PIN_A6 -to "sr_a[9]"
-set_location_assignment PIN_A7 -to "sr_a[7]"
-set_location_assignment PIN_A8 -to "abc_a[0]"
-set_location_assignment PIN_A9 -to "abc_a[2]"
-set_location_assignment PIN_A10 -to "sr_dq[7]"
-set_location_assignment PIN_A11 -to "sr_dq[5]"
-set_location_assignment PIN_A12 -to "sr_dq[0]"
-set_location_assignment PIN_A13 -to "sr_ba[0]"
-set_location_assignment PIN_A14 -to "sr_a[0]"
-set_location_assignment PIN_A15 -to "sr_a[3]"
-set_location_assignment PIN_B1 -to "abc_xm_x"
-set_location_assignment PIN_B3 -to "abc_int80_x"
-set_location_assignment PIN_B4 -to "abc_rdy_x"
-set_location_assignment PIN_B5 -to "sr_dq[10]"
-set_location_assignment PIN_B6 -to "sr_a[12]"
-set_location_assignment PIN_B7 -to "sr_a[8]"
-set_location_assignment PIN_B8 -to "abc_a[1]"
-set_location_assignment PIN_B10 -to "sr_dq[6]"
-set_location_assignment PIN_B11 -to "sr_dq[4]"
-set_location_assignment PIN_B12 -to "sr_ras_n"
-set_location_assignment PIN_B13 -to "sr_ba[1]"
-set_location_assignment PIN_B14 -to "sr_a[1]"
-set_location_assignment PIN_B16 -to "rtc_int_n"
-set_location_assignment PIN_C1 -to "flash_mosi"
-set_location_assignment PIN_C2 -to "abc_a_oe"
-set_location_assignment PIN_C6 -to "sr_dq[14]"
-set_location_assignment PIN_C8 -to "sr_a[11]"
-set_location_assignment PIN_C9 -to "sr_a[4]"
-set_location_assignment PIN_C11 -to "sr_dq[3]"
-set_location_assignment PIN_C14 -to "sr_a[10]"
-set_location_assignment PIN_C15 -to "i2c_sda"
-set_location_assignment PIN_C16 -to "i2c_scl"
-set_location_assignment PIN_D1 -to "abc_a[3]"
-set_location_assignment PIN_D2 -to "flash_cs_n"
-set_location_assignment PIN_D3 -to "sr_clk"
-set_location_assignment PIN_D5 -to "sr_dq[15]"
-set_location_assignment PIN_D6 -to "sr_dq[13]"
-set_location_assignment PIN_D8 -to "sr_dqm[1]"
-set_location_assignment PIN_D9 -to "sr_a[5]"
-set_location_assignment PIN_D11 -to "sr_dq[2]"
-set_location_assignment PIN_D12 -to "sr_cs_n"
-set_location_assignment PIN_D14 -to "sr_a[2]"
-set_location_assignment PIN_D15 -to "tty_cts"
-set_location_assignment PIN_D16 -to "tty_rts"
-set_location_assignment PIN_E1 -to "abc_a[6]"
-set_location_assignment PIN_E6 -to "sr_dq[12]"
-set_location_assignment PIN_E7 -to "sr_dq[9]"
-set_location_assignment PIN_E8 -to "sr_a[6]"
-set_location_assignment PIN_E9 -to "sr_cas_n"
-set_location_assignment PIN_E10 -to "sr_dqm[0]"
-set_location_assignment PIN_E11 -to "sr_dq[1]"
-set_location_assignment PIN_E15 -to "rtc_32khz"
-set_location_assignment PIN_E16 -to "tty_txd"
-set_location_assignment PIN_F1 -to "abc_a[7]"
-set_location_assignment PIN_F2 -to "abc_cs_n"
-set_location_assignment PIN_F3 -to "abc_a[5]"
-set_location_assignment PIN_F8 -to "sr_cke"
-set_location_assignment PIN_F9 -to "sr_we_n"
-set_location_assignment PIN_F13 -to "tty_rxd"
-set_location_assignment PIN_F14 -to "sd_dat[2]"
-set_location_assignment PIN_F15 -to "sd_dat[0]"
-set_location_assignment PIN_F16 -to "sd_dat[3]"
-set_location_assignment PIN_G1 -to "abc_a[8]"
-set_location_assignment PIN_G2 -to "abc_out_n[0]"
-set_location_assignment PIN_G5 -to "abc_a[4]"
-set_location_assignment PIN_G15 -to "sd_clk"
-set_location_assignment PIN_G16 -to "sd_cmd"
-set_location_assignment PIN_H1 -to "flash_clk"
-set_location_assignment PIN_H2 -to "flash_miso"
-set_location_assignment PIN_H3 -to "tck"
-set_location_assignment PIN_H4 -to "tdi"
-set_location_assignment PIN_J1 -to "abc_a[9]"
-set_location_assignment PIN_J2 -to "abc_out_n[1]"
-set_location_assignment PIN_J4 -to "tdo"
-set_location_assignment PIN_J5 -to "tms"
-set_location_assignment PIN_J15 -to "hdmi_clk"
-set_location_assignment PIN_K1 -to "abc_a[11]"
-set_location_assignment PIN_K2 -to "abc_out_n[4]"
-set_location_assignment PIN_K5 -to "abc_out_n[2]"
-set_location_assignment PIN_K15 -to "hdmi_d[0]"
-set_location_assignment PIN_L1 -to "abc_a[12]"
-set_location_assignment PIN_L2 -to "abc_inp_n[0]"
-set_location_assignment PIN_L3 -to "abc_out_n[3]"
-set_location_assignment PIN_L4 -to "abc_a[10]"
-set_location_assignment PIN_L7 -to "gpio[0]"
-set_location_assignment PIN_L8 -to "esp_io0"
-set_location_assignment PIN_L10 -to "abc_xoutpstb_n"
-set_location_assignment PIN_M1 -to "abc_a[13]"
-set_location_assignment PIN_M2 -to "abc_inp_n[1]"
-set_location_assignment PIN_M6 -to "abc_d[1]"
-set_location_assignment PIN_M7 -to "spi_miso"
-set_location_assignment PIN_M8 -to "spi_mosi"
-set_location_assignment PIN_M10 -to "sd_dat[1]"
-set_location_assignment PIN_M11 -to "hdmi_scl"
-set_location_assignment PIN_M15 -to "clock_48"
-set_location_assignment PIN_N1 -to "abc_a[15]"
-set_location_assignment PIN_N2 -to "abc_a[14]"
-set_location_assignment PIN_N3 -to "abc_xmemfl_n"
-set_location_assignment PIN_N5 -to "abc_d[2]"
-set_location_assignment PIN_N6 -to "esp_io1"
-set_location_assignment PIN_N8 -to "spi_cs_esp_n"
-set_location_assignment PIN_N9 -to "xabc_op[2]"
-set_location_assignment PIN_N11 -to "xabc_xm_n"
-set_location_assignment PIN_N12 -to "xabc_xio_n"
-set_location_assignment PIN_N15 -to "hdmi_d[1]"
-set_location_assignment PIN_P1 -to "abc_xmemw800_n"
-set_location_assignment PIN_P2 -to "abc_rst_n"
-set_location_assignment PIN_P3 -to "abc_d[0]"
-set_location_assignment PIN_P6 -to "spi_clk"
-set_location_assignment PIN_P8 -to "esp_int"
-set_location_assignment PIN_P9 -to "gpio[1]"
-set_location_assignment PIN_P14 -to "tty_dtr"
+set_location_assignment PIN_A2 -to abc_int800_x
+set_location_assignment PIN_A3 -to abc_nmi_x
+set_location_assignment PIN_A4 -to sr_dq[11]
+set_location_assignment PIN_A5 -to sr_dq[8]
+set_location_assignment PIN_A6 -to sr_a[9]
+set_location_assignment PIN_A7 -to sr_a[7]
+set_location_assignment PIN_A8 -to abc_a[0]
+set_location_assignment PIN_A9 -to abc_a[2]
+set_location_assignment PIN_A10 -to sr_dq[7]
+set_location_assignment PIN_A11 -to sr_dq[5]
+set_location_assignment PIN_A12 -to sr_dq[0]
+set_location_assignment PIN_A13 -to sr_ba[0]
+set_location_assignment PIN_A14 -to sr_a[0]
+set_location_assignment PIN_A15 -to sr_a[3]
+set_location_assignment PIN_B1 -to abc_xm_x
+set_location_assignment PIN_B3 -to abc_int80_x
+set_location_assignment PIN_B4 -to abc_rdy_x
+set_location_assignment PIN_B5 -to sr_dq[10]
+set_location_assignment PIN_B6 -to sr_a[12]
+set_location_assignment PIN_B7 -to sr_a[8]
+set_location_assignment PIN_B8 -to abc_a[1]
+set_location_assignment PIN_B10 -to sr_dq[6]
+set_location_assignment PIN_B11 -to sr_dq[4]
+set_location_assignment PIN_B12 -to sr_ras_n
+set_location_assignment PIN_B13 -to sr_ba[1]
+set_location_assignment PIN_B14 -to sr_a[1]
+set_location_assignment PIN_B16 -to rtc_int_n
+set_location_assignment PIN_C1 -to flash_mosi
+set_location_assignment PIN_C2 -to abc_a_oe
+set_location_assignment PIN_C6 -to sr_dq[14]
+set_location_assignment PIN_C8 -to sr_a[11]
+set_location_assignment PIN_C9 -to sr_a[4]
+set_location_assignment PIN_C11 -to sr_dq[3]
+set_location_assignment PIN_C14 -to sr_a[10]
+set_location_assignment PIN_C15 -to i2c_sda
+set_location_assignment PIN_C16 -to i2c_scl
+set_location_assignment PIN_D1 -to abc_a[3]
+set_location_assignment PIN_D2 -to flash_cs_n
+set_location_assignment PIN_D3 -to sr_clk
+set_location_assignment PIN_D5 -to sr_dq[15]
+set_location_assignment PIN_D6 -to sr_dq[13]
+set_location_assignment PIN_D8 -to sr_dqm[1]
+set_location_assignment PIN_D9 -to sr_a[5]
+set_location_assignment PIN_D11 -to sr_dq[2]
+set_location_assignment PIN_D12 -to sr_cs_n
+set_location_assignment PIN_D14 -to sr_a[2]
+set_location_assignment PIN_D15 -to tty_cts
+set_location_assignment PIN_D16 -to tty_rts
+set_location_assignment PIN_E1 -to abc_a[6]
+set_location_assignment PIN_E6 -to sr_dq[12]
+set_location_assignment PIN_E7 -to sr_dq[9]
+set_location_assignment PIN_E8 -to sr_a[6]
+set_location_assignment PIN_E9 -to sr_cas_n
+set_location_assignment PIN_E10 -to sr_dqm[0]
+set_location_assignment PIN_E11 -to sr_dq[1]
+set_location_assignment PIN_E15 -to rtc_32khz
+set_location_assignment PIN_E16 -to tty_txd
+set_location_assignment PIN_F1 -to abc_a[7]
+set_location_assignment PIN_F2 -to abc_cs_n
+set_location_assignment PIN_F3 -to abc_a[5]
+set_location_assignment PIN_F8 -to sr_cke
+set_location_assignment PIN_F9 -to sr_we_n
+set_location_assignment PIN_F13 -to tty_rxd
+set_location_assignment PIN_F14 -to sd_dat[2]
+set_location_assignment PIN_F15 -to sd_dat[0]
+set_location_assignment PIN_F16 -to sd_dat[3]
+set_location_assignment PIN_G1 -to abc_a[8]
+set_location_assignment PIN_G2 -to abc_out_n[0]
+set_location_assignment PIN_G5 -to abc_a[4]
+set_location_assignment PIN_G15 -to sd_clk
+set_location_assignment PIN_G16 -to sd_cmd
+set_location_assignment PIN_H1 -to flash_clk
+set_location_assignment PIN_H2 -to flash_miso
+set_location_assignment PIN_H3 -to tck
+set_location_assignment PIN_H4 -to tdi
+set_location_assignment PIN_J1 -to abc_a[9]
+set_location_assignment PIN_J2 -to abc_out_n[1]
+set_location_assignment PIN_J4 -to tdo
+set_location_assignment PIN_J5 -to tms
+set_location_assignment PIN_J15 -to hdmi_clk
+set_location_assignment PIN_K1 -to abc_a[11]
+set_location_assignment PIN_K2 -to abc_out_n[4]
+set_location_assignment PIN_K5 -to abc_out_n[2]
+set_location_assignment PIN_K15 -to hdmi_d[0]
+set_location_assignment PIN_L1 -to abc_a[12]
+set_location_assignment PIN_L2 -to abc_inp_n[0]
+set_location_assignment PIN_L3 -to abc_out_n[3]
+set_location_assignment PIN_L4 -to abc_a[10]
+set_location_assignment PIN_L7 -to gpio[0]
+set_location_assignment PIN_L8 -to esp_io0
+set_location_assignment PIN_L10 -to abc_xoutpstb_n
+set_location_assignment PIN_M1 -to abc_a[13]
+set_location_assignment PIN_M2 -to abc_inp_n[1]
+set_location_assignment PIN_M6 -to abc_d[1]
+set_location_assignment PIN_M7 -to spi_miso
+set_location_assignment PIN_M8 -to spi_mosi
+set_location_assignment PIN_M10 -to sd_dat[1]
+set_location_assignment PIN_M11 -to hdmi_scl
+set_location_assignment PIN_M15 -to clock_48
+set_location_assignment PIN_N1 -to abc_a[15]
+set_location_assignment PIN_N2 -to abc_a[14]
+set_location_assignment PIN_N3 -to abc_xmemfl_n
+set_location_assignment PIN_N5 -to abc_d[2]
+set_location_assignment PIN_N6 -to esp_io1
+set_location_assignment PIN_N8 -to spi_cs_esp_n
+set_location_assignment PIN_N9 -to xabc_op[2]
+set_location_assignment PIN_N11 -to xabc_xm_n
+set_location_assignment PIN_N12 -to xabc_xio_n
+set_location_assignment PIN_N15 -to hdmi_d[1]
+set_location_assignment PIN_P1 -to abc_xmemw800_n
+set_location_assignment PIN_P2 -to abc_rst_n
+set_location_assignment PIN_P3 -to abc_d[0]
+set_location_assignment PIN_P6 -to spi_clk
+set_location_assignment PIN_P8 -to esp_int
+set_location_assignment PIN_P9 -to gpio[1]
+set_location_assignment PIN_P14 -to tty_dtr
 set_location_assignment PIN_P16 -to "hdmi_d[2](n)"
-set_location_assignment PIN_R1 -to "abc_xmemw80_n"
-set_location_assignment PIN_R3 -to "abc_d[4]"
-set_location_assignment PIN_R4 -to "abc_d[6]"
-set_location_assignment PIN_R5 -to "abc_d_ce_n"
-set_location_assignment PIN_R6 -to "abc_resin_x"
-set_location_assignment PIN_R7 -to "gpio[5]"
-set_location_assignment PIN_R8 -to "xabc_op[0]"
-set_location_assignment PIN_R10 -to "gpio[3]"
-set_location_assignment PIN_R11 -to "xabc_nmi_n"
-set_location_assignment PIN_R12 -to "xabc_gpio[1]"
-set_location_assignment PIN_R13 -to "hdmi_sda"
-set_location_assignment PIN_R14 -to "led[2]"
-set_location_assignment PIN_R16 -to "hdmi_d[2]"
-set_location_assignment PIN_T2 -to "abc_d[3]"
-set_location_assignment PIN_T3 -to "abc_d[5]"
-set_location_assignment PIN_T4 -to "abc_d[7]"
-set_location_assignment PIN_T5 -to "abc_d_oe"
-set_location_assignment PIN_T6 -to "gpio[2]"
-set_location_assignment PIN_T7 -to "gpio[4]"
-set_location_assignment PIN_T8 -to "abc_clk"
-set_location_assignment PIN_T9 -to "xabc_op[1]"
-set_location_assignment PIN_T10 -to "abc_master"
-set_location_assignment PIN_T11 -to "xabc_gpio[0]"
-set_location_assignment PIN_T12 -to "abc_xinpstb_n"
-set_location_assignment PIN_T13 -to "led[1]"
-set_location_assignment PIN_T14 -to "led[3]"
-set_location_assignment PIN_T15 -to "hdmi_hpd"
+set_location_assignment PIN_R1 -to abc_xmemw80_n
+set_location_assignment PIN_R3 -to abc_d[4]
+set_location_assignment PIN_R4 -to abc_d[6]
+set_location_assignment PIN_R5 -to abc_d_ce_n
+set_location_assignment PIN_R6 -to abc_resin_x
+set_location_assignment PIN_R7 -to gpio[5]
+set_location_assignment PIN_R8 -to xabc_op[0]
+set_location_assignment PIN_R10 -to gpio[3]
+set_location_assignment PIN_R11 -to xabc_nmi_n
+set_location_assignment PIN_R12 -to xabc_gpio[1]
+set_location_assignment PIN_R13 -to hdmi_sda
+set_location_assignment PIN_R14 -to led[2]
+set_location_assignment PIN_R16 -to hdmi_d[2]
+set_location_assignment PIN_T2 -to abc_d[3]
+set_location_assignment PIN_T3 -to abc_d[5]
+set_location_assignment PIN_T4 -to abc_d[7]
+set_location_assignment PIN_T5 -to abc_d_oe
+set_location_assignment PIN_T6 -to gpio[2]
+set_location_assignment PIN_T7 -to gpio[4]
+set_location_assignment PIN_T8 -to abc_clk
+set_location_assignment PIN_T9 -to xabc_op[1]
+set_location_assignment PIN_T10 -to abc_master
+set_location_assignment PIN_T11 -to xabc_gpio[0]
+set_location_assignment PIN_T12 -to abc_xinpstb_n
+set_location_assignment PIN_T13 -to led[1]
+set_location_assignment PIN_T14 -to led[3]
+set_location_assignment PIN_T15 -to hdmi_hpd
+
 
+set_global_assignment -name VERILOG_FILE syncho.v
+set_global_assignment -name VERILOG_FILE ip/hdmitx.v
+set_global_assignment -name VERILOG_FILE ip/pll.v
+set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
+set_global_assignment -name SDC_FILE max80.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

output_files/max80.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for max80
-Thu Jul 29 01:11:28 2021
+Thu Jul 29 01:17:54 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -39,7 +39,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Jul 29 01:11:28 2021 ;
+; Assembler Status      ; Successful - Thu Jul 29 01:17:54 2021 ;
 ; Revision Name         ; max80                                 ;
 ; Top-level Entity Name ; max80                                 ;
 ; Family                ; Cyclone IV E                          ;
@@ -89,7 +89,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:11:27 2021
+    Info: Processing started: Thu Jul 29 01:17:52 2021
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
@@ -97,9 +97,9 @@ Info (115030): Assembler is generating device programming files
 Info (210117): Created JAM or JBC file for the specified chain: 
 Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 903 megabytes
-    Info: Processing ended: Thu Jul 29 01:11:28 2021
-    Info: Elapsed time: 00:00:01
+    Info: Peak virtual memory: 904 megabytes
+    Info: Processing ended: Thu Jul 29 01:17:54 2021
+    Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 
 

output_files/max80.done

@@ -1 +1 @@
-Thu Jul 29 01:11:35 2021
+Thu Jul 29 01:18:00 2021

output_files/max80.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for max80
-Thu Jul 29 01:11:34 2021
+Thu Jul 29 01:18:00 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Jul 29 01:11:34 2021 ;
+; EDA Netlist Writer Status ; Successful - Thu Jul 29 01:18:00 2021 ;
 ; Revision Name             ; max80                                 ;
 ; Top-level Entity Name     ; max80                                 ;
 ; Family                    ; Cyclone IV E                          ;
@@ -81,14 +81,14 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:11:34 2021
+    Info: Processing started: Thu Jul 29 01:17:59 2021
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 1127 megabytes
-    Info: Processing ended: Thu Jul 29 01:11:34 2021
-    Info: Elapsed time: 00:00:00
+    Info: Peak virtual memory: 1125 megabytes
+    Info: Processing ended: Thu Jul 29 01:18:00 2021
+    Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:00
 
 

output_files/max80.fit.rpt

@@ -1,5 +1,5 @@
 Fitter report for max80
-Thu Jul 29 01:11:26 2021
+Thu Jul 29 01:17:51 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -73,7 +73,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                   ;
 +------------------------------------+---------------------------------------------+
-; Fitter Status                      ; Successful - Thu Jul 29 01:11:26 2021       ;
+; Fitter Status                      ; Successful - Thu Jul 29 01:17:51 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -2052,8 +2052,8 @@ Warning (169064): Following 45 pins have no output enable or a GND or VCC output
     Info (169065): Pin hdmi_hpd has a permanently disabled output enable File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 101
 Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 39 warnings
-    Info: Peak virtual memory: 1333 megabytes
-    Info: Processing ended: Thu Jul 29 01:11:26 2021
+    Info: Peak virtual memory: 1345 megabytes
+    Info: Processing ended: Thu Jul 29 01:17:52 2021
     Info: Elapsed time: 00:00:09
     Info: Total CPU time (on all processors): 00:00:09
 

output_files/max80.fit.summary

@@ -1,4 +1,4 @@
-Fitter Status : Successful - Thu Jul 29 01:11:26 2021
+Fitter Status : Successful - Thu Jul 29 01:17:51 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for max80
-Thu Jul 29 01:11:34 2021
+Thu Jul 29 01:18:00 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Thu Jul 29 01:11:34 2021       ;
+; Flow Status                        ; Successful - Thu Jul 29 01:18:00 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 07/29/2021 01:11:04 ;
+; Start date & time ; 07/29/2021 01:17:30 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; max80               ;
 +-------------------+---------------------+
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                      ; 180546899331588.162754626460986        ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID                      ; 180546899331588.162754665061494        ; --            ; --          ; --                                ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
@@ -96,16 +96,6 @@ https://fpgasoftware.intel.com/eula.
 ; IOBANK_VCCIO                               ; 3.3V                                   ; --            ; --          ; 8                                 ;
 ; MAX_CORE_JUNCTION_TEMP                     ; 85                                     ; --            ; --          ; --                                ;
 ; MIN_CORE_JUNCTION_TEMP                     ; 0                                      ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/pll.bsf                             ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/pll_inst.v                          ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/pll_bb.v                            ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/pll.ppf                             ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/hdmitx.bsf                          ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/hdmitx_inst.v                       ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/hdmitx_bb.v                         ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/hdmitx.inc                          ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/hdmitx.cmp                          ; --            ; --          ; --                                ;
-; MISC_FILE                                  ; ip/hdmitx.ppf                          ; --            ; --          ; --                                ;
 ; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers                  ; Normal        ; --          ; --                                ;
 ; OUTPUT_IO_TIMING_FAR_END_VMEAS             ; Half Signal Swing                      ; --            ; --          ; --                                ;
 ; OUTPUT_IO_TIMING_FAR_END_VMEAS             ; Half Signal Swing                      ; --            ; --          ; --                                ;
@@ -135,13 +125,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:12     ; 1.0                     ; 1037 MB             ; 00:00:27                           ;
-; Fitter               ; 00:00:09     ; 1.0                     ; 1333 MB             ; 00:00:09                           ;
-; Assembler            ; 00:00:01     ; 1.0                     ; 903 MB              ; 00:00:02                           ;
-; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1268 MB             ; 00:00:02                           ;
-; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 896 MB              ; 00:00:02                           ;
-; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 1127 MB             ; 00:00:00                           ;
-; Total                ; 00:00:26     ; --                      ; --                  ; 00:00:42                           ;
+; Analysis & Synthesis ; 00:00:12     ; 1.0                     ; 1038 MB             ; 00:00:28                           ;
+; Fitter               ; 00:00:08     ; 1.0                     ; 1345 MB             ; 00:00:09                           ;
+; Assembler            ; 00:00:02     ; 1.0                     ; 904 MB              ; 00:00:02                           ;
+; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1264 MB             ; 00:00:02                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 891 MB              ; 00:00:02                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 1125 MB             ; 00:00:00                           ;
+; Total                ; 00:00:27     ; --                      ; --                  ; 00:00:43                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 

output_files/max80.map.rpt

@@ -1,5 +1,5 @@
 Analysis & Synthesis report for max80
-Thu Jul 29 01:11:17 2021
+Thu Jul 29 01:17:42 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -13,35 +13,34 @@ Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
   5. Analysis & Synthesis Source Files Read
   6. Analysis & Synthesis Resource Usage Summary
   7. Analysis & Synthesis Resource Utilization by Entity
-  8. Analysis & Synthesis IP Cores Summary
-  9. Registers Removed During Synthesis
- 10. Removed Registers Triggering Further Register Optimizations
- 11. General Register Statistics
- 12. Inverted Register Statistics
- 13. Multiplexer Restructuring Statistics (Restructuring Performed)
- 14. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated
- 15. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2
- 16. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4
- 17. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5
- 18. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated
- 19. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out
- 20. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio
- 21. Parameter Settings for User Entity Instance: Top-level Entity: |max80
- 22. Parameter Settings for User Entity Instance: pll:pll|altpll:altpll_component
- 23. Parameter Settings for User Entity Instance: transpose:hdmitranspose
- 24. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:dreg
- 25. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:qreg
- 26. Parameter Settings for User Entity Instance: hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component
- 27. altpll Parameter Settings by Entity Instance
- 28. Port Connectivity Checks: "hdmitx:hdmitx"
- 29. Port Connectivity Checks: "transpose:hdmitranspose"
- 30. Port Connectivity Checks: "tmdsenc:hdmitmds[2].enc"
- 31. Port Connectivity Checks: "tmdsenc:hdmitmds[1].enc"
- 32. Port Connectivity Checks: "tmdsenc:hdmitmds[0].enc"
- 33. Port Connectivity Checks: "pll:pll"
- 34. Post-Synthesis Netlist Statistics for Top Partition
- 35. Elapsed Time Per Partition
- 36. Analysis & Synthesis Messages
+  8. Registers Removed During Synthesis
+  9. Removed Registers Triggering Further Register Optimizations
+ 10. General Register Statistics
+ 11. Inverted Register Statistics
+ 12. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 13. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated
+ 14. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2
+ 15. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4
+ 16. Source assignments for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5
+ 17. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated
+ 18. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out:ddio_out
+ 19. Source assignments for hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_ddio_out1:outclock_ddio
+ 20. Parameter Settings for User Entity Instance: Top-level Entity: |max80
+ 21. Parameter Settings for User Entity Instance: pll:pll|altpll:altpll_component
+ 22. Parameter Settings for User Entity Instance: transpose:hdmitranspose
+ 23. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:dreg
+ 24. Parameter Settings for User Entity Instance: transpose:hdmitranspose|condreg:qreg
+ 25. Parameter Settings for User Entity Instance: hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component
+ 26. altpll Parameter Settings by Entity Instance
+ 27. Port Connectivity Checks: "hdmitx:hdmitx"
+ 28. Port Connectivity Checks: "transpose:hdmitranspose"
+ 29. Port Connectivity Checks: "tmdsenc:hdmitmds[2].enc"
+ 30. Port Connectivity Checks: "tmdsenc:hdmitmds[1].enc"
+ 31. Port Connectivity Checks: "tmdsenc:hdmitmds[0].enc"
+ 32. Port Connectivity Checks: "pll:pll"
+ 33. Post-Synthesis Netlist Statistics for Top Partition
+ 34. Elapsed Time Per Partition
+ 35. Analysis & Synthesis Messages
 
 
 
@@ -68,7 +67,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Thu Jul 29 01:11:17 2021       ;
+; Analysis & Synthesis Status        ; Successful - Thu Jul 29 01:17:42 2021       ;
 ; Quartus Prime Version              ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -195,10 +194,10 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
 ; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                    ; Library ;
 +----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
+; ip/hdmitx.v                      ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/hdmitx.v                                     ;         ;
+; ip/pll.v                         ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/pll.v                                        ;         ;
 ; transpose.sv                     ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/transpose.sv                                    ;         ;
 ; max80.sv                         ; yes             ; User SystemVerilog HDL File  ; /home/hpa/abc80/max80/blinktest/max80.sv                                        ;         ;
-; ip/pll.v                         ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/pll.v                                        ;         ;
-; ip/hdmitx.v                      ; yes             ; User Wizard-Generated File   ; /home/hpa/abc80/max80/blinktest/ip/hdmitx.v                                     ;         ;
 ; altpll.tdf                       ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/altpll.tdf                     ;         ;
 ; aglobal181.inc                   ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/aglobal181.inc                 ;         ;
 ; stratix_pll.inc                  ; yes             ; Megafunction                 ; /opt/altera/18.1/quartus/libraries/megafunctions/stratix_pll.inc                ;         ;
@@ -286,16 +285,6 @@ https://fpgasoftware.intel.com/eula.
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
-+--------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary                                                                  ;
-+--------+--------------+---------+--------------+--------------+----------------------+-----------------+
-; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File ;
-+--------+--------------+---------+--------------+--------------+----------------------+-----------------+
-; Altera ; ALTLVDS_TX   ; 18.1    ; N/A          ; N/A          ; |max80|hdmitx:hdmitx ; ip/hdmitx.v     ;
-; Altera ; ALTPLL       ; 18.1    ; N/A          ; N/A          ; |max80|pll:pll       ; ip/pll.v        ;
-+--------+--------------+---------+--------------+--------------+----------------------+-----------------+
-
-
 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 ; Registers Removed During Synthesis                                                                                                                                                                                                                              ;
 +--------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
@@ -1103,20 +1092,21 @@ Note: In order to hide this table in the UI and the text report file, please set
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:11:04 2021
+    Info: Processing started: Thu Jul 29 01:17:30 2021
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Warning (12019): Can't analyze file -- file syncho.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file ip/hdmitx.v
+    Info (12023): Found entity 1: hdmitx File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file ip/pll.v
+    Info (12023): Found entity 1: pll File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 40
 Info (12021): Found 3 design units, including 3 entities, in source file transpose.sv
     Info (12023): Found entity 1: condreg File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 4
     Info (12023): Found entity 2: transpose File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 35
     Info (12023): Found entity 3: reverse File: /home/hpa/abc80/max80/blinktest/transpose.sv Line: 79
 Info (12021): Found 1 design units, including 1 entities, in source file max80.sv
     Info (12023): Found entity 1: max80 File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 11
-Info (12021): Found 1 design units, including 1 entities, in source file ip/pll.v
-    Info (12023): Found entity 1: pll File: /home/hpa/abc80/max80/blinktest/ip/pll.v Line: 40
-Info (12021): Found 1 design units, including 1 entities, in source file ip/hdmitx.v
-    Info (12023): Found entity 1: hdmitx File: /home/hpa/abc80/max80/blinktest/ip/hdmitx.v Line: 40
 Warning (10236): Verilog HDL Implicit Net warning at max80.sv(172): created implicit net for "hdmi_sck" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 172
 Warning (10236): Verilog HDL Implicit Net warning at max80.sv(268): created implicit net for "spi_cs_flash_n" File: /home/hpa/abc80/max80/blinktest/max80.sv Line: 268
 Info (12127): Elaborating entity "max80" for the top level hierarchy
@@ -1516,10 +1506,10 @@ Info (21057): Implemented 475 device resources after synthesis - the final resou
     Info (21060): Implemented 45 bidirectional pins
     Info (21061): Implemented 339 logic cells
     Info (21065): Implemented 2 PLLs
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 207 warnings
-    Info: Peak virtual memory: 1086 megabytes
-    Info: Processing ended: Thu Jul 29 01:11:17 2021
-    Info: Elapsed time: 00:00:13
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 208 warnings
+    Info: Peak virtual memory: 1087 megabytes
+    Info: Processing ended: Thu Jul 29 01:17:42 2021
+    Info: Elapsed time: 00:00:12
     Info: Total CPU time (on all processors): 00:00:28
 
 

output_files/max80.map.summary

@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Thu Jul 29 01:11:17 2021
+Analysis & Synthesis Status : Successful - Thu Jul 29 01:17:42 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.pow.rpt

@@ -1,5 +1,5 @@
 Power Analyzer report for max80
-Thu Jul 29 01:11:31 2021
+Thu Jul 29 01:17:56 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------------+
 ; Power Analyzer Summary                                                                    ;
 +----------------------------------------+--------------------------------------------------+
-; Power Analyzer Status                  ; Successful - Thu Jul 29 01:11:31 2021            ;
+; Power Analyzer Status                  ; Successful - Thu Jul 29 01:17:56 2021            ;
 ; Quartus Prime Version                  ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition      ;
 ; Revision Name                          ; max80                                            ;
 ; Top-level Entity Name                  ; max80                                            ;
@@ -383,7 +383,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Power Analyzer
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:11:29 2021
+    Info: Processing started: Thu Jul 29 01:17:54 2021
 Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (21077): Low junction temperature is 0 degrees C
@@ -424,8 +424,8 @@ Info (334004): Delay annotation completed successfully
 Info (215049): Average toggle rate for this design is 11.033 millions of transitions / sec
 Info (215031): Total thermal power estimate for the design is 213.74 mW
 Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 1268 megabytes
-    Info: Processing ended: Thu Jul 29 01:11:31 2021
+    Info: Peak virtual memory: 1264 megabytes
+    Info: Processing ended: Thu Jul 29 01:17:56 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 

output_files/max80.pow.summary

@@ -1,4 +1,4 @@
-Power Analyzer Status : Successful - Thu Jul 29 01:11:31 2021
+Power Analyzer Status : Successful - Thu Jul 29 01:17:56 2021
 Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.sta.rpt

@@ -1,5 +1,5 @@
 Timing Analyzer report for max80
-Thu Jul 29 01:11:33 2021
+Thu Jul 29 01:17:59 2021
 Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
 
 
@@ -123,7 +123,7 @@ https://fpgasoftware.intel.com/eula.
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   3.0%      ;
+;     Processor 2            ;   2.9%      ;
 +----------------------------+-------------+
 
 
@@ -132,7 +132,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------+--------+--------------------------+
 ; SDC File Path ; Status ; Read at                  ;
 +---------------+--------+--------------------------+
-; max80.sdc     ; OK     ; Thu Jul 29 01:11:32 2021 ;
+; max80.sdc     ; OK     ; Thu Jul 29 01:17:57 2021 ;
 +---------------+--------+--------------------------+
 
 
@@ -2279,6 +2279,10 @@ No paths to report.
 ; 0.293 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
 ; 0.293 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.413      ;
 ; 0.293 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.412      ;
+; 0.294 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.294 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
 ; 0.294 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
 ; 0.294 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
 ; 0.294 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
@@ -2288,10 +2292,10 @@ No paths to report.
 ; 0.294 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
 ; 0.294 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
 ; 0.294 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.413      ;
-; 0.294 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
-; 0.294 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
-; 0.294 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
-; 0.294 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.414      ;
+; 0.295 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
 ; 0.295 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
 ; 0.295 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
 ; 0.295 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
@@ -2300,78 +2304,74 @@ No paths to report.
 ; 0.295 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
 ; 0.295 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
 ; 0.295 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.414      ;
-; 0.295 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
-; 0.295 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
-; 0.295 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
-; 0.295 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.415      ;
+; 0.296 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
 ; 0.296 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
 ; 0.296 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
 ; 0.296 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
 ; 0.296 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
 ; 0.296 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
 ; 0.296 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.415      ;
-; 0.296 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
-; 0.296 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
-; 0.296 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
-; 0.296 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.416      ;
 ; 0.300 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.419      ;
 ; 0.365 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.484      ;
 ; 0.441 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.561      ;
 ; 0.442 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
 ; 0.442 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
 ; 0.442 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.562      ;
+; 0.443 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
+; 0.443 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
 ; 0.443 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
 ; 0.443 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
 ; 0.443 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
 ; 0.443 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
 ; 0.443 ; led_ctr[10]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
 ; 0.443 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.562      ;
-; 0.443 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
-; 0.443 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.563      ;
-; 0.444 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
-; 0.444 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
-; 0.444 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
 ; 0.444 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
 ; 0.444 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
 ; 0.444 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
+; 0.444 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.564      ;
+; 0.444 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
+; 0.444 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.563      ;
 ; 0.452 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
 ; 0.452 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.572      ;
+; 0.453 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.453 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.453 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.453 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.453 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.453 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.453 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
 ; 0.453 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
 ; 0.453 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
 ; 0.453 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.572      ;
-; 0.453 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
-; 0.453 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
-; 0.453 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
-; 0.453 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.573      ;
+; 0.454 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
+; 0.454 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
 ; 0.454 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
 ; 0.454 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
 ; 0.454 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
 ; 0.454 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
 ; 0.454 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
 ; 0.454 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.573      ;
-; 0.454 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
-; 0.454 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.574      ;
 ; 0.455 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
 ; 0.455 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
 ; 0.455 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.575      ;
+; 0.456 ; rst_ctr[0]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.456 ; rst_ctr[4]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.456 ; rst_ctr[2]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.456 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.456 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.456 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.575      ;
 ; 0.456 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
 ; 0.456 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.575      ;
-; 0.456 ; rst_ctr[0]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
-; 0.456 ; rst_ctr[4]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
-; 0.456 ; rst_ctr[2]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.576      ;
+; 0.457 ; rst_ctr[8]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
+; 0.457 ; rst_ctr[6]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
 ; 0.457 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
 ; 0.457 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
 ; 0.457 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
 ; 0.457 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
 ; 0.457 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.035      ; 0.576      ;
-; 0.457 ; rst_ctr[8]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
-; 0.457 ; rst_ctr[6]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.577      ;
 ; 0.462 ; rst_ctr[11]              ; rst_n                    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.582      ;
 ; 0.474 ; rst_ctr[10]              ; rst_n                    ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.594      ;
 +-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
@@ -3203,7 +3203,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-    Info: Processing started: Thu Jul 29 01:11:31 2021
+    Info: Processing started: Thu Jul 29 01:17:57 2021
 Info: Command: quartus_sta max80 -c max80
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -3325,8 +3325,8 @@ Info (332146): Worst-case minimum pulse width slack is 2.563
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings
-    Info: Peak virtual memory: 896 megabytes
-    Info: Processing ended: Thu Jul 29 01:11:33 2021
+    Info: Peak virtual memory: 891 megabytes
+    Info: Processing ended: Thu Jul 29 01:17:59 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02