 H. Peter Anvin
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9ac4e30722
time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC
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2 years ago |
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H. Peter Anvin
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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2 years ago |
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H. Peter Anvin
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e1c53dfb56
vjtag: allow both SRAM and DRAM to be accessed over VJTAG
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2 years ago |
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H. Peter Anvin
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8ba4a1a3de
vjtag: fix "one bit behind" problem for write properly; use sys_clk
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2 years ago |
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H. Peter Anvin
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47300bdbed
vjtag: require a synchronization prefix to write to memory
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2 years ago |
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H. Peter Anvin
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37de408c19
Allow the CPU to force an FPGA reload; vjtag improvement
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2 years ago |
