 H. Peter Anvin
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9ac4e30722
time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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aac953ed19
Implement FPGA <-> ESP32 communication path
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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60be2e1201
v2: v2 has a 16 MHz oscillator instead of 48 MHz
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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81633591fa
v2: abc_host and abc_a_oe are redundant and unified in v2
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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6db45e74e6
WIP: build both v1 and v2
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%!s(int64=3) %!d(string=hai) anos |
