abcbus.sv 22 KB

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  1. module abcbus (
  2. input rst_n,
  3. input sys_clk,
  4. input sdram_clk, // Assumed to be a multiple of sys_clk
  5. input stb_1mhz, // 1-2 MHz sys_clk strobe
  6. input stb_50us, // 10-20 kHz sdram_clk strobe
  7. // CPU interface
  8. input abc_valid, // Control/status registers
  9. input map_valid, // Memory map
  10. input [31:0] cpu_addr,
  11. input [31:0] cpu_wdata,
  12. input [3:0] cpu_wstrb,
  13. output reg [31:0] cpu_rdata, // For the ABC-bus control
  14. output [31:0] cpu_rdata_map, // For the map RAM
  15. output reg irq,
  16. // ABC bus
  17. inout abc_clk,
  18. output abc_clk_s,
  19. inout [15:0] abc_a,
  20. inout [7:0] abc_d,
  21. output reg abc_d_oe,
  22. inout abc_rst_n,
  23. inout abc_cs_n,
  24. inout [4:0] abc_out_n,
  25. inout [1:0] abc_inp_n,
  26. inout abc_xmemfl_n,
  27. inout abc_xmemw800_n, // Memory write strobe (ABC800)
  28. inout abc_xmemw80_n, // Memory write strobe (ABC80)
  29. inout abc_xinpstb_n, // I/O read strobe (ABC800)
  30. inout abc_xoutpstb_n, // I/O write strobe (ABC80)
  31. // The following are inverted versus the bus IF
  32. // the corresponding MOSFETs are installed
  33. inout abc_rdy_x, // RDY = WAIT#
  34. inout abc_resin_x, // System reset request
  35. inout abc_int80_x, // System INT request (ABC80)
  36. inout abc_int800_x, // System INT request (ABC800)
  37. inout abc_nmi_x, // System NMI request (ABC800)
  38. inout abc_xm_x, // System memory override (ABC800)
  39. // Host/device control
  40. output abc_host, // 1 = host, 0 = device
  41. // ABC-bus extension header
  42. // (Note: cannot use an array here because HC and HH are
  43. // input only.)
  44. inout exth_ha,
  45. inout exth_hb,
  46. input exth_hc,
  47. inout exth_hd,
  48. inout exth_he,
  49. inout exth_hf,
  50. inout exth_hg,
  51. input exth_hh,
  52. // SDRAM interface
  53. output [24:0] sdram_addr,
  54. input [7:0] sdram_rd,
  55. output reg sdram_valid,
  56. input sdram_ready,
  57. output [7:0] sdram_wd,
  58. output reg sdram_wstrb
  59. );
  60. // SDRAM base address, used for reading back the map registers
  61. parameter [31:0] sdram_base_addr;
  62. // Set if MOSFETs Q1-Q6 are installed rather than the corresponding
  63. // resistors. BOTH CANNOT BE INSTALLED AT THE SAME TIME.
  64. parameter [6:1] mosfet_installed = 6'b111_111;
  65. // Are the auxiliary extension header bits reversed (this may be
  66. // programmable in the future depending on orientation of the header)?
  67. parameter [0:0] exth_reversed = 1'b0;
  68. // Synchronizer for ABC-bus input signals; also changes
  69. // the sense to positive logic where applicable
  70. wire [15:0] abc_a_s;
  71. wire [7:0] abc_di;
  72. wire abc_rst_s;
  73. wire abc_cs_s;
  74. wire [4:0] abc_out_s;
  75. wire [1:0] abc_inp_s;
  76. wire abc_xmemfl_s;
  77. wire abc_xmemw800_s;
  78. wire abc_xmemw80_s;
  79. wire abc_xinpstb_s;
  80. wire abc_xoutpstb_s;
  81. synchronizer #( .width(39) ) abc_synchro
  82. (
  83. .rst_n ( rst_n ),
  84. .clk ( sys_clk ),
  85. .d ( { abc_clk, abc_a, abc_d, ~abc_rst_n, ~abc_cs_n,
  86. ~abc_out_n, ~abc_inp_n, ~abc_xmemfl_n, ~abc_xmemw800_n,
  87. ~abc_xmemw80_n, ~abc_xinpstb_n, ~abc_xoutpstb_n } ),
  88. .q ( { abc_clk_s, abc_a_s, abc_di, abc_rst_s, abc_cs_s,
  89. abc_out_s, abc_inp_s, abc_xmemfl_s, abc_xmemw800_s,
  90. abc_xmemw80_s, abc_xinpstb_s, abc_xoutpstb_s } )
  91. );
  92. // Only support device mode for now (v2 cards could support host mode)
  93. assign abc_host = 1'b0;
  94. reg abc_clk_active;
  95. reg abc80 = 1'b1;
  96. wire abc800 = ~abc80;
  97. wire xinpstb_s = (abc800 & abc_xinpstb_s & ~abc_xoutpstb_s)
  98. | (|abc_inp_s);
  99. wire xoutpstb_s = (abc800 & abc_xoutpstb_s & ~abc_xinpstb_s)
  100. | (|abc_out_s);
  101. // Memory and I/O read/write strobes for ABC-bus
  102. reg abc_xmemrd;
  103. reg abc_xmemwr;
  104. reg abc_xinpstb;
  105. reg abc_xoutpstb;
  106. reg [1:0] abc_inp;
  107. reg [4:0] abc_out;
  108. reg abc_rst;
  109. reg abc_cs;
  110. reg [3:1] abc_stb; // Delayed strobes
  111. always @(negedge rst_n or posedge sdram_clk)
  112. if (~rst_n)
  113. begin
  114. abc_xmemrd <= 1'b0;
  115. abc_xmemwr <= 1'b0;
  116. abc_inp <= 2'b0;
  117. abc_out <= 5'b0;
  118. abc_xinpstb <= 1'b0;
  119. abc_xoutpstb <= 1'b0;
  120. abc_rst <= 1'b0;
  121. abc_cs <= 1'b0;
  122. abc_stb <= 'b0;
  123. end
  124. else
  125. begin
  126. abc_xmemrd <= abc_clk_active & abc_xmemfl_s;
  127. abc_xmemwr <= abc_clk_active &
  128. (abc800 ? abc_xmemw800_s : abc_xmemw80_s);
  129. abc_inp <= abc_inp_s & {2{abc_clk_active}};
  130. abc_out <= abc_out_s & {5{abc_clk_active}};
  131. abc_xinpstb <= xinpstb_s & abc_clk_active;
  132. abc_xoutpstb <= xoutpstb_s & abc_clk_active;
  133. abc_rst <= abc_rst_s & abc_clk_active;
  134. abc_cs <= abc_cs_s & abc_clk_active;
  135. abc_stb <= { abc_stb,
  136. abc_xinpstb|abc_xoutpstb|abc_xmemrd|abc_xmemwr };
  137. end
  138. reg [7:0] abc_do;
  139. assign abc_d = abc_d_oe ? abc_do : 8'hzz;
  140. reg [8:0] ioselx;
  141. wire iosel_en = ioselx[8];
  142. wire [5:0] iosel = ioselx[5:0];
  143. // ABC-bus I/O select
  144. always @(negedge rst_n or posedge sdram_clk)
  145. if (~rst_n)
  146. ioselx <= 9'b0;
  147. else if (abc_rst)
  148. ioselx <= 9'b0;
  149. else if (abc_cs)
  150. ioselx <= { 1'b1, abc_di };
  151. // Open drain signals with optional MOSFETs
  152. reg abc_wait = 1'b1; // Power up asserted; see below
  153. reg abc_int = 1'b0;
  154. reg abc_nmi = 1'b0;
  155. reg abc_resin = 1'b0;
  156. reg abc_xm = 1'b0;
  157. function reg opt_mosfet(input signal, input mosfet);
  158. if (mosfet)
  159. opt_mosfet = signal;
  160. else
  161. opt_mosfet = signal ? 1'b0 : 1'bz;
  162. endfunction // opt_mosfet
  163. assign abc_int80_x = opt_mosfet(abc_int & abc80, mosfet_installed[1]);
  164. assign abc_rdy_x = opt_mosfet(abc_wait, mosfet_installed[2]);
  165. assign abc_nmi_x = opt_mosfet(abc_nmi, mosfet_installed[3]);
  166. assign abc_resin_x = opt_mosfet(abc_resin, mosfet_installed[4]);
  167. assign abc_int800_x = opt_mosfet(abc_int & abc800, mosfet_installed[5]);
  168. assign abc_xm_x = opt_mosfet(abc_xm, mosfet_installed[6]);
  169. // Detect ABC-bus clock: need a minimum frequency of 84/64 MHz
  170. // to be considered live. Sample XINPSTB# and XOUTPSTB# on clock
  171. // transitions to try to auto-detect ABC80 or ABC800.
  172. //
  173. // On ABC800, only one of XINPSTB# or XOUTPSTB# will be active;
  174. // on ABC80 they will either be 00 or ZZ; in the latter case pulled
  175. // low by external resistors.
  176. reg [2:0] abc_clk_ctr;
  177. reg [1:0] abc_clk_q;
  178. reg abc80_force;
  179. reg abc800_force;
  180. always @(negedge rst_n or posedge sys_clk)
  181. if (~rst_n)
  182. begin
  183. abc_clk_q <= 2'b0;
  184. abc_clk_ctr <= 3'b0;
  185. abc_clk_active <= 1'b0;
  186. end
  187. else
  188. begin
  189. abc_clk_q <= { abc_clk_q[0], abc_clk_s };
  190. case ( { abc_clk_q == 2'b01, stb_1mhz } )
  191. 2'b10: begin
  192. if (abc_clk_ctr == 3'b111)
  193. begin
  194. abc_clk_active <= 1'b1;
  195. if (abc80_force)
  196. abc80 <= 1'b1;
  197. else if (abc800_force)
  198. abc80 <= 1'b0;
  199. else
  200. abc80 <= abc_xinpstb_s & abc_xoutpstb_s;
  201. end
  202. else
  203. abc_clk_ctr <= abc_clk_ctr + 1'b1;
  204. end
  205. 2'b01: begin
  206. if (abc_clk_ctr == 3'b000)
  207. abc_clk_active <= 1'b0;
  208. else
  209. abc_clk_ctr <= abc_clk_ctr - 1'b1;
  210. end
  211. default: begin
  212. // nothing
  213. end
  214. endcase // case ( {(abc_clk_q == 2'10), sys_clk_stb[6]} )
  215. end // else: !if(~rst_n)
  216. // ABC-bus extension header (exth_c and exth_h are input only)
  217. // The naming of pins is kind of nonsensical:
  218. //
  219. // +3V3 - 1 2 - +3V3
  220. // HA - 3 4 - HE
  221. // HB - 5 6 - HG
  222. // HC - 7 8 - HH
  223. // HD - 9 10 - HF
  224. // GND - 11 12 - GND
  225. //
  226. // This layout allows the header to be connected on either side
  227. // of the board. This logic assigns the following names to the pins;
  228. // if the ext_reversed is set to 1 then the left and right sides
  229. // are flipped.
  230. //
  231. // +3V3 - 1 2 - +3V3
  232. // exth[0] - 3 4 - exth[1]
  233. // exth[2] - 5 6 - exth[3]
  234. // exth[6] - 7 8 - exth[7]
  235. // exth[4] - 9 10 - exth[5]
  236. // GND - 11 12 - GND
  237. wire [7:0] exth_d; // Input data
  238. wire [5:0] exth_q; // Output data
  239. wire [5:0] exth_oe; // Output enable
  240. assign exth_d[0] = exth_reversed ? exth_he : exth_ha;
  241. assign exth_d[1] = exth_reversed ? exth_ha : exth_he;
  242. assign exth_d[2] = exth_reversed ? exth_hg : exth_hb;
  243. assign exth_d[3] = exth_reversed ? exth_hb : exth_hg;
  244. assign exth_d[4] = exth_reversed ? exth_hf : exth_hd;
  245. assign exth_d[5] = exth_reversed ? exth_hd : exth_hf;
  246. assign exth_d[6] = exth_reversed ? exth_hh : exth_hc;
  247. assign exth_d[7] = exth_reversed ? exth_hc : exth_hh;
  248. wire [2:0] erx = { 2'b00, exth_reversed };
  249. assign exth_ha = exth_oe[3'd0 ^ erx] ? exth_q[3'd0 ^ erx] : 1'bz;
  250. assign exth_he = exth_oe[3'd1 ^ erx] ? exth_q[3'd1 ^ erx] : 1'bz;
  251. assign exth_hb = exth_oe[3'd2 ^ erx] ? exth_q[3'd2 ^ erx] : 1'bz;
  252. assign exth_hg = exth_oe[3'd3 ^ erx] ? exth_q[3'd3 ^ erx] : 1'bz;
  253. assign exth_hd = exth_oe[3'd4 ^ erx] ? exth_q[3'd4 ^ erx] : 1'bz;
  254. assign exth_hf = exth_oe[3'd5 ^ erx] ? exth_q[3'd5 ^ erx] : 1'bz;
  255. assign exth_q = 6'b0;
  256. assign exth_oe = 6'b0;
  257. // ABC SDRAM interface
  258. //
  259. // Memory map for ABC-bus memory references.
  260. // 1024 byte granularity in two maps for memory (registers 0-127).
  261. //
  262. // For simplicity, the data bits from the CPU are reorganized
  263. // so the SDRAM address is the same as the CPU uses.
  264. //
  265. // bit [14:0] = SDRAM address [24:10] ( bits 24:10 from RV32 )
  266. // bit [15] = write enable ( bit 0 from RV32 )
  267. // bit [16] = read enable ( bit 1 from RV32 )
  268. // bit [17] = assert XM# ( bit 2 from RV32 )
  269. //
  270. // Accesses from RV32 supports 32-bit accesses only!
  271. //
  272. logic [2:0] abc_a_map;
  273. logic [15:0] abc_a_addr;
  274. wire [17:0] rdata_abcmemmap; // RV32 access port
  275. wire [17:0] abc_memmap_rd; // ABC-bus access port
  276. abcmapram
  277. (
  278. .aclr ( ~rst_n ),
  279. .clock ( sdram_clk ),
  280. .address_a ( { abc_a_map, abc_a_addr } ),
  281. .data_a ( 18'bx ),
  282. .wren_a ( 1'b0 ),
  283. .q_a ( abc_memmap_rd ),
  284. .address_b ( cpu_addr[10:2] ),
  285. .data_b ( { cpu_wdata[2:0], cpu_wdata[24:10] } ),
  286. .wren_b ( map_valid & cpu_wstrb[0] ),
  287. .q_b ( rdata_abcmemmap )
  288. );
  289. assign cpu_rdata_map = sdram_base_addr | // Fixed bits
  290. { 7'b0, rdata_abcmemmap[14:0], // Address
  291. 7'b0, rdata_abcmemmap[17:15] }; // Flags
  292. wire abc_xmen = abc_memmap_rd[17];
  293. wire abc_rden = abc_memmap_rd[16];
  294. wire abc_wren = abc_memmap_rd[15];
  295. wire [24:0] abc_memaddr = { abc_memmap_rd[14:0], abc_a_s[9:0] };
  296. reg abc_memrd_en;
  297. reg abc_memwr_en;
  298. reg abc_do_memrd;
  299. reg abc_do_memwr;
  300. reg abc_mem_ready;
  301. always @(posedge sdram_clk or negedge rst_n)
  302. if (~rst_n)
  303. begin
  304. abc_memrd_en <= 1'b0;
  305. abc_memwr_en <= 1'b0;
  306. abc_do_memrd <= 1'b0;
  307. abc_do_memwr <= 1'b0;
  308. sdram_valid <= 1'b0;
  309. sdram_wstrb <= 1'b0;
  310. abc_xm <= 1'b0;
  311. abc_mem_ready <= 1'b0;
  312. end
  313. else
  314. begin
  315. // Careful with the registering here: need to make sure
  316. // abcmapram is caught up with the address. If sam is in use
  317. // then the address can change after XMEMRD# is asserted.
  318. abc_memwr_en <= abc_xmemwr;
  319. abc_memrd_en <= abc_xmemrd;
  320. abc_mem_ready <= abc_memwr_en | abc_memrd_en;
  321. abc_do_memrd <= abc_rden & abc_memrd_en & abc_mem_ready;
  322. abc_do_memwr <= abc_wren & abc_memwr_en & abc_mem_ready;
  323. sdram_valid <= abc_do_memrd | abc_do_memwr;
  324. sdram_wstrb <= abc_do_memwr;
  325. abc_xm <= abc_xmen;
  326. end // else: !if(~rst_n)
  327. assign sdram_addr = abc_memaddr;
  328. assign sdram_wd = abc_di;
  329. //
  330. // 4680 data registers; RST# is considered OUT 7 even through
  331. // it is an IN from the ABC point of view.
  332. //
  333. // OUT register, written from ABC: <addr 2:0> <data 7:0>
  334. // IN register, written from CPU: <enable 1:0> <status 7:0> <inp 7:0>
  335. // Busy register:
  336. //
  337. // [7:0] - busy OUT status (write-1-clear)
  338. // [9:8] - busy IN status (write-1-clear)
  339. // [15:12] - bus status change (write-1-clear)
  340. // same bit positions as the bus status register
  341. //
  342. // [23:16] - busy OUT mask
  343. // [25:24] - busy IN mask
  344. // [31:28] - bus status change IRQ enable
  345. //
  346. // Assert WAIT# (deassert RDY) if the masked busy status is nonzero
  347. // and an busy-unmasked I/O comes in.
  348. //
  349. // An IRQ is generated if the masked busy status is nonzero.
  350. //
  351. reg [9:0] busy_status;
  352. reg [9:0] busy_mask;
  353. reg [9:0] busy_io_q;
  354. reg [1:0] inp_en;
  355. reg [3:0] bus_change_status;
  356. reg [3:0] bus_change_mask;
  357. wire [9:0] is_io = { abc_inp[1:0], abc_rst, 1'b0,
  358. abc_out[4:1], abc_cs, abc_out[0] };
  359. wire [9:0] busy_io = is_io & busy_mask;
  360. wire is_busy = |(busy_status & busy_mask);
  361. wire [9:0] busy_valid = 10'b11_1011_1111;
  362. wire [9:0] set_busy = busy_io_q & ~busy_io;
  363. always @(posedge sys_clk or negedge rst_n)
  364. if (~rst_n)
  365. busy_io_q <= 10'b0;
  366. else
  367. busy_io_q <= busy_io;
  368. // WAIT# logic
  369. reg abc_wait_force = 1'b1; // Power up asserted; ignores rst_n
  370. always @(posedge sys_clk)
  371. abc_wait <= abc_wait_force | (rst_n & |set_busy & is_busy);
  372. //
  373. // 4680 bus data registers
  374. //
  375. reg [2:0] reg_out_addr;
  376. reg [7:0] reg_out_data;
  377. reg [7:0] reg_inp_data[0:1];
  378. // OUT logic
  379. always @(posedge sdram_clk)
  380. begin
  381. if (|busy_io[7:0])
  382. begin
  383. reg_out_data <= abc_di;
  384. case (busy_io[7:0])
  385. 8'b0000_0001: reg_out_addr <= 3'd0;
  386. 8'b0000_0010: reg_out_addr <= 3'd1;
  387. 8'b0000_0100: reg_out_addr <= 3'd2;
  388. 8'b0000_1000: reg_out_addr <= 3'd3;
  389. 8'b0001_0000: reg_out_addr <= 3'd4;
  390. 8'b0010_0000: reg_out_addr <= 3'd5;
  391. 8'b0100_0000: reg_out_addr <= 3'd6;
  392. 8'b1000_0000: reg_out_addr <= 3'd7;
  393. default: reg_out_addr <= 3'dx;
  394. endcase // case (busy_io)
  395. end // if (|busy_io[7:0])
  396. end // always @ (posedge sdram_clk)
  397. //
  398. // Default memory map
  399. //
  400. reg [2:0] abc_mem_map = 3'b000;
  401. //
  402. // ABC800 non-4680 I/O ports
  403. //
  404. reg abc800mac_en = 1'b0;
  405. reg [7:1] abc800mac_iobase = 7'b0;
  406. reg [15:0] abc800mac_xmmask = 16'b0;
  407. wire abc800mac_avalid =
  408. abc800mac_en && abc_a_s[7:1] == abc800mac_iobase;
  409. wire cpu_xmmask = rst_n && abc_valid && cpu_addr[6:2] == 5'b01001;
  410. // XMMASK logic (abc800mac_en is handled with other CPU registers)
  411. always @(posedge sdram_clk)
  412. begin
  413. if (abc_xoutpstb & abc800mac_avalid & !abc_a_s[0])
  414. abc800mac_xmmask[7:0] <= abc_di;
  415. else if (cpu_xmmask & cpu_wstrb[0])
  416. abc800mac_xmmask[7:0] <= cpu_wdata[7:0];
  417. if (abc_xoutpstb & abc800mac_avalid & abc_a_s[1])
  418. abc800mac_xmmask[15:8] <= abc_di;
  419. else if (cpu_xmmask & cpu_wstrb[1])
  420. abc800mac_xmmask[15:8] <= cpu_wdata[15:8];
  421. end // always @ (posedge sdram_clk)
  422. //
  423. // Smartaid Magnum
  424. //
  425. reg sam_en = 1'b0;
  426. reg [2:0] sam_mem_map = 3'b000;
  427. wire sam_resin_n;
  428. wire [15:0] sam_a_out;
  429. wire sam_map;
  430. wire [7:0] sam_do;
  431. wire sam_dout_oe;
  432. samagnum sam (
  433. .fast_clk ( sdram_clk ),
  434. .stb_50us ( stb_50us ),
  435. .clk ( abc_clk_s ),
  436. .xmemwr_n ( ~abc_xmemwr ),
  437. .xmemfl_n ( ~abc_xmemrd ),
  438. .xmemfl_out_n ( ),
  439. .resin_n ( sam_resin_n ),
  440. .a ( abc_a_s ),
  441. .a_out ( sam_a_out ),
  442. .a_map ( sam_map ),
  443. .dout ( sam_dout ),
  444. .dout_oe ( sam_dout_oe )
  445. );
  446. //
  447. // ABC data out (= ABC host read) logic
  448. //
  449. always @(negedge rst_n or posedge sdram_clk)
  450. if (~rst_n)
  451. begin
  452. abc_d_oe <= 1'b0;
  453. abc_do <= 8'bx;
  454. end
  455. else
  456. begin
  457. abc_d_oe <= 1'b0;
  458. abc_do <= sdram_rd;
  459. if (sam_en & sam_dout_oe)
  460. begin
  461. abc_d_oe <= 1'b1;
  462. abc_do <= sam_dout;
  463. end
  464. else if (abc_do_memrd)
  465. begin
  466. // Drive the output bus even if sdram_rd doesn't yet have
  467. // valid data yet (i.e. sdram_ready = 0).
  468. // The propagation delay for OE#/DIR for 74HC245 is about
  469. // twice what it is for data.
  470. abc_d_oe <= 1'b1;
  471. abc_do <= sdram_rd;
  472. end
  473. else if (abc_inp[0] & inp_en[0])
  474. begin
  475. abc_d_oe <= 1'b1;
  476. abc_do <= reg_inp_data[0];
  477. end
  478. else if (abc_inp[1] & inp_en[1])
  479. begin
  480. abc_d_oe <= 1'b1;
  481. abc_do <= reg_inp_data[1];
  482. end
  483. else if (abc_xinpstb & abc800mac_avalid)
  484. begin
  485. abc_d_oe <= 1'b1;
  486. case (abc_a_s[0])
  487. 1'b0: abc_do <= abc800mac_xmmask[7:0];
  488. 1'b1: abc_do <= abc800mac_xmmask[15:8];
  489. endcase // case (abc_a_s[0])
  490. end
  491. end // else: !if(~rst_n)
  492. //
  493. // Memory map control logic
  494. //
  495. always_comb
  496. begin
  497. abc_a_map = abc_mem_map;
  498. abc_a_map[0] ^= abc800mac_en & abc800mac_xmmask[abc_a_s[15:12]];
  499. abc_a_addr = abc_a_s;
  500. if ( sam_en & sam_map )
  501. begin
  502. abc_a_map = sam_mem_map;
  503. abc_a_addr = sam_a_out;
  504. end
  505. end
  506. // Memory read latency counter
  507. reg [7:0] memrd_latency_ctr = 'b0;
  508. reg [7:0] memrd_latency_max = 'b0;
  509. reg memrd_latency_err = 1'b0;
  510. wire [7:0] memrd_latency_ctr_next = memrd_latency_ctr + 1'b1;
  511. always @(posedge sdram_clk)
  512. begin
  513. if (abc_do_memrd & ~sdram_ready)
  514. begin
  515. memrd_latency_ctr <= memrd_latency_ctr_next;
  516. if (memrd_latency_max == memrd_latency_ctr)
  517. memrd_latency_max <= memrd_latency_ctr_next;
  518. // If abc_xmemrd goes away, then we missed our time
  519. // window... this is bad.
  520. if (~abc_xmemrd)
  521. memrd_latency_err <= 1'b1;
  522. end // else: !if(~abc_do_memrd)
  523. else if (~abc_do_memrd)
  524. begin
  525. memrd_latency_ctr <= 'b0;
  526. end
  527. end // always @ (posedge sdram_clk)
  528. // Bus status
  529. reg [3:0] abc_status[0:1];
  530. always @(posedge sys_clk)
  531. begin
  532. abc_status[0] <= { 1'b0, abc800, abc_rst_s, abc_clk_active };
  533. abc_status[1] <= abc_status[0];
  534. end
  535. wire [3:0] bus_change = (abc_status[0] ^ abc_status[1]) & bus_change_mask;
  536. wire [3:0] bus_change_valid = 4'b0111;
  537. //
  538. // Busy/IRQ status and CPU register writes
  539. //
  540. always @(posedge sys_clk or negedge rst_n)
  541. if (~rst_n)
  542. begin
  543. busy_status <= 10'b0;
  544. busy_mask <= 10'h082; // Enable hold on RST# and CS#
  545. inp_en <= 2'b00;
  546. bus_change_status <= 4'b0;
  547. bus_change_mask <= 4'b0;
  548. abc800mac_en <= 1'b0;
  549. abc80_force <= 1'b0;
  550. abc800_force <= 1'b0;
  551. abc_mem_map <= 3'b0;
  552. sam_mem_map <= 3'b0;
  553. sam_en <= 1'b0;
  554. // abc_resin, nmi, int and force_wait are deliberately not affected
  555. // by an internal CPU reset. They are, however, inherently asserted
  556. // when the FPGA is configured, and initialized to fixed values
  557. // at configuration time (RESIN# asserted, the others deasserted.)
  558. end
  559. else
  560. begin
  561. busy_status <= busy_status | set_busy;
  562. bus_change_status <= bus_change_status | bus_change;
  563. if (abc_valid)
  564. begin
  565. casez (cpu_addr[6:2] )
  566. 5'b00000: begin
  567. if (cpu_wstrb[1])
  568. begin
  569. abc80_force <= cpu_wdata[8];
  570. abc800_force <= cpu_wdata[9];
  571. end
  572. end
  573. 5'b00010: begin
  574. if (cpu_wstrb[0])
  575. busy_status[7:0] <= set_busy[7:0] | (busy_status[7:0] & ~cpu_wdata[7:0]);
  576. if (cpu_wstrb[1])
  577. begin
  578. busy_status[9:8] <= set_busy[9:8] | (busy_status[9:8] & ~cpu_wdata[9:8]);
  579. bus_change_status <= bus_change | (bus_change_status & ~cpu_wdata[15:12]);
  580. end
  581. if (cpu_wstrb[2])
  582. busy_mask[7:0] <= cpu_wdata[23:16] & busy_valid[7:0];
  583. if (cpu_wstrb[3])
  584. begin
  585. busy_mask[9:8] <= cpu_wdata[25:24] & busy_valid[9:8];
  586. bus_change_mask <= cpu_wdata[31:28] & bus_change_valid;
  587. end
  588. end
  589. 5'b00011: begin
  590. if (cpu_wstrb[0])
  591. begin
  592. abc_resin <= cpu_wdata[3];
  593. abc_nmi <= cpu_wdata[2];
  594. abc_int <= cpu_wdata[1];
  595. abc_wait_force <= cpu_wdata[0];
  596. end
  597. end
  598. 5'b00101: begin
  599. if (cpu_wstrb[0])
  600. reg_inp_data[0] <= cpu_wdata[7:0];
  601. if (cpu_wstrb[1])
  602. reg_inp_data[1] <= cpu_wdata[15:8];
  603. if (cpu_wstrb[2])
  604. inp_en <= cpu_wdata[17:16];
  605. end
  606. 5'b01000: begin
  607. if (cpu_wstrb[0])
  608. abc800mac_iobase <= cpu_wdata[7:1];
  609. if (cpu_wstrb[3])
  610. abc800mac_en <= cpu_wdata[31];
  611. end
  612. // 5'b01001: abc800mac_xmdata - handled elsewhere
  613. 5'b01010: begin
  614. if (cpu_wstrb[0])
  615. abc_mem_map <= cpu_wdata[2:0];
  616. if (cpu_wstrb[1])
  617. begin
  618. sam_mem_map <= cpu_wdata[10:8];
  619. sam_en <= cpu_wdata[15];
  620. end
  621. end
  622. default: begin
  623. /* do nothing */
  624. end
  625. endcase // casez (cpu_addr[6:2])
  626. end // if (abc_valid & cpu_wstrb[0])
  627. end
  628. // Level triggered IRQ
  629. always @(posedge sys_clk)
  630. irq <= is_busy | |(bus_change_status & bus_change_mask);
  631. // Read MUX
  632. always_comb
  633. begin
  634. cpu_rdata = 32'b0;
  635. casez (cpu_addr[6:2])
  636. 5'b00000: cpu_rdata = { 22'b0, abc800_force, abc80_force,
  637. 4'b0, abc_status[0] };
  638. 5'b00001: cpu_rdata = { 23'b0, ~iosel_en, ioselx[7:0] };
  639. 5'b00010: cpu_rdata = { bus_change_mask, 2'b0, busy_mask,
  640. bus_change_status, 2'b0, busy_status };
  641. 5'b00011: cpu_rdata = { 28'b0, abc_resin, abc_nmi, abc_int, abc_wait };
  642. 5'b00100: cpu_rdata = { 21'b0, reg_out_addr, reg_out_data };
  643. 5'b00101: cpu_rdata = { 14'b0, inp_en, reg_inp_data[1], reg_inp_data[0] };
  644. 5'b00111: cpu_rdata = { 23'b0, memrd_latency_err, memrd_latency_max };
  645. 5'b01000: cpu_rdata = { abc800mac_en, 23'b0, abc800mac_iobase, 1'b0 };
  646. 5'b01001: cpu_rdata = { 16'b0, abc800mac_xmmask };
  647. 5'b01010: cpu_rdata = { 16'b0, sam_en, 4'b0, sam_mem_map, 5'b0, abc_mem_map };
  648. default: cpu_rdata = 32'b0;
  649. endcase // casez (cpu_addr[6:2])
  650. end
  651. endmodule // abcbus