Commit History

Autor SHA1 Mensaxe Data
  H. Peter Anvin 0a742774ae Getting full synthesis with CPU and fast memory; not tested yet %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 29caaeebbe pll: change system clock to 84 MHz %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 98999420a7 max80: better testing of the sdram controller %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 728e8de139 sdram: allow arbitrary alignments on port 1 %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 2c6d4d66d2 sdram: fix some timing calculations, pre-ack, cleanups %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 7efe6c8d1c sdram: fix op_cycle counter overflow %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 9363f018e1 sdram: rewrite state machine with an operations loop counter %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin b2d184d021 Fix polarity of output SDRAM clock; move into sdram module %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 30d5acc569 Change core clock to 168 MHz and video clock to 48 MHz %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin afc9429471 Add simple SDRAM controller %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 43d9806872 Remove unused assignments; use a DDIO buffer for sr_clk %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 0cc1a65b5e Change N/C pins to output driving GND %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 85544a3c97 Add pin for flash_mosi; update some I/O options %!s(int64=3) %!d(string=hai) anos
  H. Peter Anvin 5ddc02d7cf Update pinout to match latest schematic %!s(int64=3) %!d(string=hai) anos