 H. Peter Anvin
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0a742774ae
Getting full synthesis with CPU and fast memory; not tested yet
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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29caaeebbe
pll: change system clock to 84 MHz
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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98999420a7
max80: better testing of the sdram controller
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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728e8de139
sdram: allow arbitrary alignments on port 1
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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2c6d4d66d2
sdram: fix some timing calculations, pre-ack, cleanups
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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7efe6c8d1c
sdram: fix op_cycle counter overflow
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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9363f018e1
sdram: rewrite state machine with an operations loop counter
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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b2d184d021
Fix polarity of output SDRAM clock; move into sdram module
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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30d5acc569
Change core clock to 168 MHz and video clock to 48 MHz
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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afc9429471
Add simple SDRAM controller
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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43d9806872
Remove unused assignments; use a DDIO buffer for sr_clk
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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0cc1a65b5e
Change N/C pins to output driving GND
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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85544a3c97
Add pin for flash_mosi; update some I/O options
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%!s(int64=3) %!d(string=hai) anos |
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H. Peter Anvin
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5ddc02d7cf
Update pinout to match latest schematic
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%!s(int64=3) %!d(string=hai) anos |
