Historia zmian

Autor SHA1 Wiadomość Data
  H. Peter Anvin 30d5acc569 Change core clock to 168 MHz and video clock to 48 MHz 4 lat temu
  H. Peter Anvin afc9429471 Add simple SDRAM controller 4 lat temu
  H. Peter Anvin 43d9806872 Remove unused assignments; use a DDIO buffer for sr_clk 4 lat temu
  H. Peter Anvin 0cc1a65b5e Change N/C pins to output driving GND 4 lat temu
  H. Peter Anvin 85544a3c97 Add pin for flash_mosi; update some I/O options 4 lat temu
  H. Peter Anvin 5ddc02d7cf Update pinout to match latest schematic 4 lat temu