 H. Peter Anvin
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9ac4e30722
time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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bec7285913
esplink: fix handshake between ESP and FPGA
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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3847060a6e
Merge esplink work with mainline
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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50f7f572a3
WIP: ringbuffer system between ESP32 and FPGA
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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99c9b0ccc3
Better timezone handling; upload helper scripts
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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c4320f1f4f
esplink: better error checking, test ESP -> FPGA write direction
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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065742e213
esplink: fix startup time race condition on ESP32 side
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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d8e0e2d6ac
esplink: handle arbitrary byte ranges; allow ESP to query status
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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832c07c31f
Have ESP issue a handshake interrupt; some common link code
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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1725fbb91d
ESP32 code for FPGA link; test code and fixes
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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aac953ed19
Implement FPGA <-> ESP32 communication path
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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f1e04bf5c7
esp32 firmware image with support for OTA updates of both FPGA and ESP32
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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0cdd243825
serial.sv: mer generell serieport med Rx och Tx
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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e0305b26e3
system.c: disable the 5 s testing startup delay
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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4d4291d637
usb: fix descriptor regeneration; add name strings to individual ports
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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835310c76e
update: .fw file is a single compressed container; simplify I/O code
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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84afb464e6
update: encode version in the firmware files; better .rpf generation
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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6375646603
update: get closer to a working JTAG update infrastructure
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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e1c53dfb56
vjtag: allow both SRAM and DRAM to be accessed over VJTAG
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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8ba4a1a3de
vjtag: fix "one bit behind" problem for write properly; use sys_clk
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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47300bdbed
vjtag: require a synchronization prefix to write to memory
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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37de408c19
Allow the CPU to force an FPGA reload; vjtag improvement
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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2ec75f1807
fpga: virtual JTAG interface
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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9c1891e562
spiflash.[ch]: a (hopefully) platform-independent SPI flash writer
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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a90ef02f46
fpga: generate .xsvf files
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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e05dbe6f40
v2boot: simple boot loader connecting ESP32-SPI to flash-SPI
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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4b07e7703d
Fix USB serial number generation
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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aea92d6f7a
fw: download SPI ROM ID and send to USB very early in execution
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%!s(int64=2) %!d(string=hai) anos |
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H. Peter Anvin
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6014b9c6d7
max80: fix timing bug that affected code execution from SDRAM
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%!s(int64=2) %!d(string=hai) anos |
