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bsdl
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50f7f572a3
WIP: ringbuffer system between ESP32 and FPGA
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%!s(int64=2) %!d(string=hai) anos |
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ip
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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%!s(int64=2) %!d(string=hai) anos |
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output
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b138f38385
WIP: generalize I2C interface
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%!s(int64=2) %!d(string=hai) anos |
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scripts
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835310c76e
update: .fw file is a single compressed container; simplify I/O code
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%!s(int64=2) %!d(string=hai) anos |
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simulation
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f24cac3c43
fpga: lint code to make ModelSim RTL simulation work again
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%!s(int64=3) %!d(string=hai) anos |
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usb
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2016fa2500
usbparam.vh: corect Verilog `define syntax
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%!s(int64=2) %!d(string=hai) anos |
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.gitignore
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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%!s(int64=2) %!d(string=hai) anos |
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Makefile
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75e32256b8
fw: add ability to write a board ID string in ESP flash
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%!s(int64=2) %!d(string=hai) anos |
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abcbus.sv
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9ac4e30722
time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC
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%!s(int64=2) %!d(string=hai) anos |
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assignment_defaults.qdf
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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%!s(int64=3) %!d(string=hai) anos |
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bootldr.sv
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e05dbe6f40
v2boot: simple boot loader connecting ESP32-SPI to flash-SPI
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%!s(int64=2) %!d(string=hai) anos |
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bypass.pins
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f1e04bf5c7
esp32 firmware image with support for OTA updates of both FPGA and ESP32
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%!s(int64=2) %!d(string=hai) anos |
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bypass.qsf
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f1e04bf5c7
esp32 firmware image with support for OTA updates of both FPGA and ESP32
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%!s(int64=2) %!d(string=hai) anos |
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bypass.sdc
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f1e04bf5c7
esp32 firmware image with support for OTA updates of both FPGA and ESP32
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%!s(int64=2) %!d(string=hai) anos |
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bypass.sv
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f1e04bf5c7
esp32 firmware image with support for OTA updates of both FPGA and ESP32
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%!s(int64=2) %!d(string=hai) anos |
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bypass_description.txt
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f1e04bf5c7
esp32 firmware image with support for OTA updates of both FPGA and ESP32
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%!s(int64=2) %!d(string=hai) anos |
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clkbuf.sv
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808ba7c43c
usb: use a direct interface between the CPU and the USB FIFOs
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%!s(int64=3) %!d(string=hai) anos |
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deglitch.sv
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a69847d434
fpga: add deglitcher core
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%!s(int64=2) %!d(string=hai) anos |
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esp.sv
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54aa67c9dd
esplink: change to 7 interrupt/status bits per direction
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%!s(int64=2) %!d(string=hai) anos |
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fast_mem.sv
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9ac4e30722
time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC
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%!s(int64=2) %!d(string=hai) anos |
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fpgarst.sv
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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%!s(int64=2) %!d(string=hai) anos |
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functions.sv
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54aa67c9dd
esplink: change to 7 interrupt/status bits per direction
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%!s(int64=2) %!d(string=hai) anos |
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i2c.sv
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b138f38385
WIP: generalize I2C interface
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%!s(int64=2) %!d(string=hai) anos |
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iodevs.vh
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835310c76e
update: .fw file is a single compressed container; simplify I/O code
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%!s(int64=2) %!d(string=hai) anos |
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jic.cof.xml
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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%!s(int64=2) %!d(string=hai) anos |
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max80.qpf
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b138f38385
WIP: generalize I2C interface
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%!s(int64=2) %!d(string=hai) anos |
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max80.qsf
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5328aa117d
fpga: parameterize USB max packet size
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%!s(int64=2) %!d(string=hai) anos |
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max80.sdc
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8b67b5db30
spirom: fix SPI ROM I/O and data downloading
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%!s(int64=2) %!d(string=hai) anos |
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max80.sv
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1917765d2f
picorv32: add support for multiple user CPU contexts
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%!s(int64=2) %!d(string=hai) anos |
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picorv32.v
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1917765d2f
picorv32: add support for multiple user CPU contexts
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%!s(int64=2) %!d(string=hai) anos |
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pof.cof.xml
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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%!s(int64=2) %!d(string=hai) anos |
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reconfig.svf
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4803e910d3
fpga: .svf file to force a FPGA reconfiguration
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%!s(int64=2) %!d(string=hai) anos |
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rng.sv
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de1566292f
clocks: centralize strobes; rng: shut down when not in use
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%!s(int64=3) %!d(string=hai) anos |
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sdcard.sv
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ec99762a84
Use waitirq rather than suspending a memory transaction for SD card
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%!s(int64=3) %!d(string=hai) anos |
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sdram.sv
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0271d1979a
sdram: return start to the right subunit; add ABC-bus latency counter
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%!s(int64=2) %!d(string=hai) anos |
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serial.sv
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f1e04bf5c7
esp32 firmware image with support for OTA updates of both FPGA and ESP32
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%!s(int64=2) %!d(string=hai) anos |
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spi_master.sv
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062a3d9eb1
Reorganize tree so a single Makefile can do the right thing
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%!s(int64=3) %!d(string=hai) anos |
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spirom.sv
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ee45852b85
Full infrastructure for updating flash via JTAG SVF
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%!s(int64=2) %!d(string=hai) anos |
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synchro.sv
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4e65673781
spirom: add support for sending arbitrary SPI commands
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%!s(int64=3) %!d(string=hai) anos |
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sysclock.sv
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9ac4e30722
time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC
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%!s(int64=2) %!d(string=hai) anos |
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tmdsenc.sv
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74d9da52b0
hdmi/tmds: fix symbol data ordering
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%!s(int64=3) %!d(string=hai) anos |
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transpose.sv
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510e702728
video: initial simple video generator; add support for HDMI TERC4
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%!s(int64=3) %!d(string=hai) anos |
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ub.tcl
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2ec75f1807
fpga: virtual JTAG interface
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%!s(int64=2) %!d(string=hai) anos |
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v1.pins
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aac953ed19
Implement FPGA <-> ESP32 communication path
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%!s(int64=2) %!d(string=hai) anos |
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v1.qsf
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e05dbe6f40
v2boot: simple boot loader connecting ESP32-SPI to flash-SPI
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%!s(int64=2) %!d(string=hai) anos |
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v1.sv
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9ac4e30722
time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC
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%!s(int64=2) %!d(string=hai) anos |
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v1_description.txt
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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%!s(int64=3) %!d(string=hai) anos |
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v2.pins
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aac953ed19
Implement FPGA <-> ESP32 communication path
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%!s(int64=2) %!d(string=hai) anos |
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v2.qsf
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1725fbb91d
ESP32 code for FPGA link; test code and fixes
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%!s(int64=2) %!d(string=hai) anos |
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v2.sv
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e05dbe6f40
v2boot: simple boot loader connecting ESP32-SPI to flash-SPI
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%!s(int64=2) %!d(string=hai) anos |
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v2.vh
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aac953ed19
Implement FPGA <-> ESP32 communication path
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%!s(int64=2) %!d(string=hai) anos |
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v2_common.qsf
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e05dbe6f40
v2boot: simple boot loader connecting ESP32-SPI to flash-SPI
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%!s(int64=2) %!d(string=hai) anos |
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v2_description.txt
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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%!s(int64=3) %!d(string=hai) anos |
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v2boot.sv
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e05dbe6f40
v2boot: simple boot loader connecting ESP32-SPI to flash-SPI
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%!s(int64=2) %!d(string=hai) anos |
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video.sv
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980eaf0400
Restructure clock tree; better sdram timing; random number generator
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%!s(int64=3) %!d(string=hai) anos |
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vjtag_max80.sv
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9ac4e30722
time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC
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%!s(int64=2) %!d(string=hai) anos |
H. Peter Anvin
b138f38385
WIP: generalize I2C interface