 H. Peter Anvin
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0a742774ae
Getting full synthesis with CPU and fast memory; not tested yet
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3 年之前 |
|
H. Peter Anvin
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b2d184d021
Fix polarity of output SDRAM clock; move into sdram module
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3 年之前 |
|
H. Peter Anvin
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30d5acc569
Change core clock to 168 MHz and video clock to 48 MHz
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3 年之前 |
|
H. Peter Anvin
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afc9429471
Add simple SDRAM controller
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3 年之前 |
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H. Peter Anvin
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0cc1a65b5e
Change N/C pins to output driving GND
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3 年之前 |
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H. Peter Anvin
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85544a3c97
Add pin for flash_mosi; update some I/O options
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3 年之前 |
|
H. Peter Anvin
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5ddc02d7cf
Update pinout to match latest schematic
|
3 年之前 |
|
H. Peter Anvin
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e831938e38
max80 blink test
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3 年之前 |
