H. Peter Anvin 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
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bsdl 50f7f572a3 WIP: ringbuffer system between ESP32 and FPGA il y a 2 ans
ip ee45852b85 Full infrastructure for updating flash via JTAG SVF il y a 2 ans
output 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
scripts 835310c76e update: .fw file is a single compressed container; simplify I/O code il y a 2 ans
simulation f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again il y a 3 ans
usb 4d4291d637 usb: fix descriptor regeneration; add name strings to individual ports il y a 2 ans
.gitignore ee45852b85 Full infrastructure for updating flash via JTAG SVF il y a 2 ans
Makefile 8a98d85fa5 Integrate esp32 build using arduino-cli; www contents in zip file (WIP) il y a 2 ans
abcbus.sv 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
assignment_defaults.qdf 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA il y a 3 ans
bootldr.sv e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI il y a 2 ans
bypass.pins f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32 il y a 2 ans
bypass.qsf f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32 il y a 2 ans
bypass.sdc f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32 il y a 2 ans
bypass.sv f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32 il y a 2 ans
bypass_description.txt f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32 il y a 2 ans
clkbuf.sv 808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs il y a 3 ans
deglitch.sv a69847d434 fpga: add deglitcher core il y a 2 ans
esp.sv 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
fast_mem.sv 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
fpgarst.sv ee45852b85 Full infrastructure for updating flash via JTAG SVF il y a 2 ans
functions.sv f2060589ab Default baud rate = 115200, baud rate programmable il y a 3 ans
i2c.sv 4970fb6ef6 rtc: issue dummy clock cycles if SDA appears stuck il y a 3 ans
iodevs.vh 835310c76e update: .fw file is a single compressed container; simplify I/O code il y a 2 ans
jic.cof.xml ee45852b85 Full infrastructure for updating flash via JTAG SVF il y a 2 ans
max80.qpf 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
max80.qsf 50f7f572a3 WIP: ringbuffer system between ESP32 and FPGA il y a 2 ans
max80.sdc 8b67b5db30 spirom: fix SPI ROM I/O and data downloading il y a 2 ans
max80.sv 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
picorv32.v 2ec75f1807 fpga: virtual JTAG interface il y a 2 ans
pof.cof.xml ee45852b85 Full infrastructure for updating flash via JTAG SVF il y a 2 ans
reconfig.svf 4803e910d3 fpga: .svf file to force a FPGA reconfiguration il y a 2 ans
rng.sv de1566292f clocks: centralize strobes; rng: shut down when not in use il y a 3 ans
sdcard.sv ec99762a84 Use waitirq rather than suspending a memory transaction for SD card il y a 3 ans
sdram.sv 0271d1979a sdram: return start to the right subunit; add ABC-bus latency counter il y a 2 ans
serial.sv f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32 il y a 2 ans
spi_master.sv 062a3d9eb1 Reorganize tree so a single Makefile can do the right thing il y a 3 ans
spirom.sv ee45852b85 Full infrastructure for updating flash via JTAG SVF il y a 2 ans
synchro.sv 4e65673781 spirom: add support for sending arbitrary SPI commands il y a 3 ans
sysclock.sv 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
tmdsenc.sv 74d9da52b0 hdmi/tmds: fix symbol data ordering il y a 3 ans
transpose.sv 510e702728 video: initial simple video generator; add support for HDMI TERC4 il y a 3 ans
ub.tcl 2ec75f1807 fpga: virtual JTAG interface il y a 2 ans
v1.pins aac953ed19 Implement FPGA <-> ESP32 communication path il y a 2 ans
v1.qsf e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI il y a 2 ans
v1.sv 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans
v1_description.txt 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA il y a 3 ans
v2.pins aac953ed19 Implement FPGA <-> ESP32 communication path il y a 2 ans
v2.qsf 1725fbb91d ESP32 code for FPGA link; test code and fixes il y a 2 ans
v2.sv e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI il y a 2 ans
v2.vh aac953ed19 Implement FPGA <-> ESP32 communication path il y a 2 ans
v2_common.qsf e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI il y a 2 ans
v2_description.txt 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA il y a 3 ans
v2boot.sv e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI il y a 2 ans
video.sv 980eaf0400 Restructure clock tree; better sdram timing; random number generator il y a 3 ans
vjtag_max80.sv 9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC il y a 2 ans