 H. Peter Anvin
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933b8432fd
rv32: don't initialize the ABC memmap until we have configuration
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1 year ago |
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H. Peter Anvin
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33f209e48c
abcio: make ABC I/O devices configurable
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1 year ago |
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H. Peter Anvin
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30f99669a2
sysvar: transfer configuration from esp32 to rv32
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1 year ago |
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H. Peter Anvin
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bf9aa45886
riscv32: add the ctz instruction for better interrupt latency
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1 year ago |
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H. Peter Anvin
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969d145878
fw: propagate board_info from ESP32 to FPGA
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2 years ago |
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H. Peter Anvin
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1b9f666c8e
Create a common directory for sources between esp32 and rv32
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2 years ago |
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H. Peter Anvin
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1b4255df8e
esplink: add ring buffer read/write functions to rv32 side
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2 years ago |
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H. Peter Anvin
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bf2d593e50
rv32: combine heap and disk cache
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2 years ago |
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H. Peter Anvin
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d0c6ce11ed
rv32: rename fw.h -> common.h for consistency
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2 years ago |
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H. Peter Anvin
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832c07c31f
Have ESP issue a handshake interrupt; some common link code
|
2 years ago |
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H. Peter Anvin
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1725fbb91d
ESP32 code for FPGA link; test code and fixes
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2 years ago |
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H. Peter Anvin
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aac953ed19
Implement FPGA <-> ESP32 communication path
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2 years ago |
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H. Peter Anvin
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e0305b26e3
system.c: disable the 5 s testing startup delay
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2 years ago |
|
H. Peter Anvin
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6375646603
update: get closer to a working JTAG update infrastructure
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2 years ago |
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H. Peter Anvin
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aea92d6f7a
fw: download SPI ROM ID and send to USB very early in execution
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2 years ago |
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H. Peter Anvin
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6014b9c6d7
max80: fix timing bug that affected code execution from SDRAM
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2 years ago |
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H. Peter Anvin
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8b67b5db30
spirom: fix SPI ROM I/O and data downloading
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2 years ago |
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H. Peter Anvin
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9471dad838
Move date stamp generation to fpga build; record SDRAM checksum
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2 years ago |
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H. Peter Anvin
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0bb459f8dc
Fix SDRAM checksum generation
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2 years ago |
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H. Peter Anvin
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adf6c39024
serial: simplify physical tty and make BREAK reset work
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2 years ago |
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H. Peter Anvin
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7462426469
usb: use showahead on the Rx FIFO, but not the Tx FIFO
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2 years ago |
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H. Peter Anvin
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a0f8eb5820
Fix false positive ABC-bus memory overrun timer
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2 years ago |
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H. Peter Anvin
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1db3d07425
PUN80 emulation, per-channel IRQ handlers, TTY IRQ polarity control
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2 years ago |
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H. Peter Anvin
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808ba7c43c
usb: use a direct interface between the CPU and the USB FIFOs
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3 years ago |
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H. Peter Anvin
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63c8bc2ec8
sdram: fix signal timing that broke dram bss zeroing.
|
3 years ago |
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H. Peter Anvin
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778a7b2ded
spirom: restructure handshake signals
|
3 years ago |
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H. Peter Anvin
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6db45e74e6
WIP: build both v1 and v2
|
3 years ago |
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H. Peter Anvin
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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3 years ago |
|
H. Peter Anvin
|
372899ea3b
Move most code to SDRAM; fix problems with code in SDRAM; cleanups
|
3 years ago |
|
H. Peter Anvin
|
a99616cbc5
WIP: restructure USB using interfaces to be able to create more endpoints
|
3 years ago |
