|
abc
|
3dd521c55c
abc: new directory with ABC programs; first: read/set RTC
|
il y a 3 ans |
|
fpga
|
4b594cfa8b
usbdescgen: handle serial number, produce Verilog code with index
|
il y a 3 ans |
|
rv32
|
a99616cbc5
WIP: restructure USB using interfaces to be able to create more endpoints
|
il y a 3 ans |
|
tools
|
4b594cfa8b
usbdescgen: handle serial number, produce Verilog code with index
|
il y a 3 ans |
|
.gitattributes
|
e1878a396f
Detect the presence of an ABC-bus by looking for a clock signal
|
il y a 3 ans |
|
.gitignore
|
bf1976441c
Add *.qip files
|
il y a 3 ans |
|
.gitmodules
|
3673cdd132
Remove fatfs as a submodule. It is small and needs edits.
|
il y a 3 ans |
|
Makefile
|
ac8a492ba2
sdram: fix 8-bit ports; rename fw/ to rv32/ to avoid confusion
|
il y a 3 ans |
|
iodevs.conf
|
de1566292f
clocks: centralize strobes; rng: shut down when not in use
|
il y a 3 ans |
|
riscv-opts.mk
|
09d392bd4c
fw: use -malign-data=natural
|
il y a 3 ans |
H. Peter Anvin
4b594cfa8b
usbdescgen: handle serial number, produce Verilog code with index