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abc
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3dd521c55c
abc: new directory with ABC programs; first: read/set RTC
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%!s(int64=3) %!d(string=hai) anos |
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fpga
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4b594cfa8b
usbdescgen: handle serial number, produce Verilog code with index
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%!s(int64=3) %!d(string=hai) anos |
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rv32
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a99616cbc5
WIP: restructure USB using interfaces to be able to create more endpoints
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%!s(int64=3) %!d(string=hai) anos |
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tools
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4b594cfa8b
usbdescgen: handle serial number, produce Verilog code with index
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%!s(int64=3) %!d(string=hai) anos |
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.gitattributes
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e1878a396f
Detect the presence of an ABC-bus by looking for a clock signal
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%!s(int64=3) %!d(string=hai) anos |
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.gitignore
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bf1976441c
Add *.qip files
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%!s(int64=3) %!d(string=hai) anos |
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.gitmodules
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3673cdd132
Remove fatfs as a submodule. It is small and needs edits.
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%!s(int64=3) %!d(string=hai) anos |
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Makefile
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ac8a492ba2
sdram: fix 8-bit ports; rename fw/ to rv32/ to avoid confusion
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%!s(int64=3) %!d(string=hai) anos |
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iodevs.conf
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de1566292f
clocks: centralize strobes; rng: shut down when not in use
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%!s(int64=3) %!d(string=hai) anos |
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riscv-opts.mk
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09d392bd4c
fw: use -malign-data=natural
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%!s(int64=3) %!d(string=hai) anos |
H. Peter Anvin
4b594cfa8b
usbdescgen: handle serial number, produce Verilog code with index