H. Peter Anvin 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
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ip a99616cbc5 WIP: restructure USB using interfaces to be able to create more endpoints 3 سال پیش
output 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
scripts 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA 3 سال پیش
simulation f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again 3 سال پیش
usb 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
.gitignore 476ce0e1b9 fpga: add a few more .gitignore patterns 3 سال پیش
Makefile 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
abcbus.sv 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
assignment_defaults.qdf 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA 3 سال پیش
fast_mem.sv dd69eafb99 Many timing fixes; better IRQ handling for abcbus 3 سال پیش
functions.sv f2060589ab Default baud rate = 115200, baud rate programmable 3 سال پیش
i2c.sv 4970fb6ef6 rtc: issue dummy clock cycles if SDA appears stuck 3 سال پیش
iodevs.vh de1566292f clocks: centralize strobes; rng: shut down when not in use 3 سال پیش
max80-v1.cof 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA 3 سال پیش
max80-v2.cof 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA 3 سال پیش
max80.qpf 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
max80.qsf 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
max80.sdc 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
max80.sv 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
picorv32.v 372899ea3b Move most code to SDRAM; fix problems with code in SDRAM; cleanups 3 سال پیش
rng.sv de1566292f clocks: centralize strobes; rng: shut down when not in use 3 سال پیش
sdcard.sv ec99762a84 Use waitirq rather than suspending a memory transaction for SD card 3 سال پیش
sdram.sv 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
spi_master.sv 062a3d9eb1 Reorganize tree so a single Makefile can do the right thing 3 سال پیش
spirom.sv 4e65673781 spirom: add support for sending arbitrary SPI commands 3 سال پیش
synchro.sv 4e65673781 spirom: add support for sending arbitrary SPI commands 3 سال پیش
sysclock.sv 3dfb6626a1 More clock tree changes; fix rng oscillator sources 3 سال پیش
tmdsenc.sv 74d9da52b0 hdmi/tmds: fix symbol data ordering 3 سال پیش
transpose.sv 510e702728 video: initial simple video generator; add support for HDMI TERC4 3 سال پیش
tty.sv 6ae39aaf12 Make romcopy device programmable and able to zero memory 3 سال پیش
v1.pins 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
v1.qsf 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
v1.sv 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
v1_description.txt 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA 3 سال پیش
v2.pins 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
v2.qsf 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
v2.sv 6db45e74e6 WIP: build both v1 and v2 3 سال پیش
v2_description.txt 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA 3 سال پیش
video.sv 980eaf0400 Restructure clock tree; better sdram timing; random number generator 3 سال پیش