ABC80/max80_fw @ sysvars

H. Peter Anvin aae59a22f3 sysvar: fix a few broken pointers; don't reset status; add debug		1 anno fa
..
bsdl	50f7f572a3 WIP: ringbuffer system between ESP32 and FPGA	2 anni fa
ip	2ec1af473b picorv32: further IRQ latency improvements; regenerate with Quartus 22.1	1 anno fa
output	aae59a22f3 sysvar: fix a few broken pointers; don't reset status; add debug	1 anno fa
scripts	835310c76e update: .fw file is a single compressed container; simplify I/O code	2 anni fa
simulation	f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again	3 anni fa
usb	bddbff2298 usb: don't remove "empty" or "last" while a packet is in progress	2 anni fa
.gitignore	ee45852b85 Full infrastructure for updating flash via JTAG SVF	2 anni fa
Makefile	75e32256b8 fw: add ability to write a board ID string in ESP flash	2 anni fa
abcbus.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	2 anni fa
assignment_defaults.qdf	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 anni fa
bootldr.sv	e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI	2 anni fa
bypass.pins	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	2 anni fa
bypass.qsf	2ec1af473b picorv32: further IRQ latency improvements; regenerate with Quartus 22.1	1 anno fa
bypass.sdc	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	2 anni fa
bypass.sv	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	2 anni fa
bypass_description.txt	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	2 anni fa
clkbuf.sv	808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs	3 anni fa
dcpktfifo.sv	bddbff2298 usb: don't remove "empty" or "last" while a packet is in progress	2 anni fa
deglitch.sv	a69847d434 fpga: add deglitcher core	2 anni fa
esp.sv	54aa67c9dd esplink: change to 7 interrupt/status bits per direction	2 anni fa
fast_mem.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	2 anni fa
fpgarst.sv	ee45852b85 Full infrastructure for updating flash via JTAG SVF	2 anni fa
functions.sv	54aa67c9dd esplink: change to 7 interrupt/status bits per direction	2 anni fa
i2c.sv	4970fb6ef6 rtc: issue dummy clock cycles if SDA appears stuck	3 anni fa
iodevs.vh	16464af081 Refresh build	1 anno fa
jic.cof.xml	ee45852b85 Full infrastructure for updating flash via JTAG SVF	2 anni fa
max80.qpf	aae59a22f3 sysvar: fix a few broken pointers; don't reset status; add debug	1 anno fa
max80.qsf	ff236177cc fpga/max80.qsf: remove duplicate entry for esp.sv	2 anni fa
max80.sdc	8b67b5db30 spirom: fix SPI ROM I/O and data downloading	2 anni fa
max80.sv	2ec1af473b picorv32: further IRQ latency improvements; regenerate with Quartus 22.1	1 anno fa
picorv32.v	3672b35b21 picorv32: export user_context and addr[1:0] to outside bus	1 anno fa
pof.cof.xml	ee45852b85 Full infrastructure for updating flash via JTAG SVF	2 anni fa
reconfig.svf	4803e910d3 fpga: .svf file to force a FPGA reconfiguration	2 anni fa
rng.sv	de1566292f clocks: centralize strobes; rng: shut down when not in use	3 anni fa
sdcard.sv	ec99762a84 Use waitirq rather than suspending a memory transaction for SD card	3 anni fa
sdram.sv	3672b35b21 picorv32: export user_context and addr[1:0] to outside bus	1 anno fa
serial.sv	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	2 anni fa
spi_master.sv	062a3d9eb1 Reorganize tree so a single Makefile can do the right thing	3 anni fa
spirom.sv	ee45852b85 Full infrastructure for updating flash via JTAG SVF	2 anni fa
synchro.sv	4e65673781 spirom: add support for sending arbitrary SPI commands	3 anni fa
sysclock.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	2 anni fa
tmdsenc.sv	74d9da52b0 hdmi/tmds: fix symbol data ordering	3 anni fa
transpose.sv	510e702728 video: initial simple video generator; add support for HDMI TERC4	3 anni fa
ub.tcl	2ec75f1807 fpga: virtual JTAG interface	2 anni fa
v1.pins	aac953ed19 Implement FPGA <-> ESP32 communication path	2 anni fa
v1.qsf	16464af081 Refresh build	1 anno fa
v1.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	2 anni fa
v1_description.txt	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 anni fa
v1_main.qsf	bddbff2298 usb: don't remove "empty" or "last" while a packet is in progress	2 anni fa
v2.pins	aac953ed19 Implement FPGA <-> ESP32 communication path	2 anni fa
v2.qsf	16464af081 Refresh build	1 anno fa
v2.sv	e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI	2 anni fa
v2.vh	aac953ed19 Implement FPGA <-> ESP32 communication path	2 anni fa
v2_description.txt	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	3 anni fa
v2_main.qsf	bddbff2298 usb: don't remove "empty" or "last" while a packet is in progress	2 anni fa
v2boot.sv	e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI	2 anni fa
video.sv	980eaf0400 Restructure clock tree; better sdram timing; random number generator	3 anni fa
vjtag_max80.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	2 anni fa