ABC80/max80_fw @ d64ebed34440ba31e121a449b31e56b6a7bcde9e

H. Peter Anvin d64ebed344 rng: add the abc_clk to the inputs		3 年之前
..
ip	bf1976441c Add *.qip files	3 年之前
output_files	d64ebed344 rng: add the abc_clk to the inputs	3 年之前
scripts	27454bdbd3 qsfdeps.pl: ignore Signaltap files	4 年之前
simulation	f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again	4 年之前
usb	cc37f87c67 sdram: rewrite as parameterized ports; usb: add USB core for testing	3 年之前
.gitignore	e32df0c25b Remove max80.map from tree	4 年之前
Makefile	ac8a492ba2 sdram: fix 8-bit ports; rename fw/ to rv32/ to avoid confusion	3 年之前
abcbus.sv	cc37f87c67 sdram: rewrite as parameterized ports; usb: add USB core for testing	3 年之前
fast_mem.sv	dd69eafb99 Many timing fixes; better IRQ handling for abcbus	4 年之前
functions.sv	f2060589ab Default baud rate = 115200, baud rate programmable	4 年之前
i2c.sv	4970fb6ef6 rtc: issue dummy clock cycles if SDA appears stuck	4 年之前
iodevs.vh	1dfcf38fed sdcard: attempt to handle insertion and removal	4 年之前
max80.pins	980eaf0400 Restructure clock tree; better sdram timing; random number generator	3 年之前
max80.qpf	062a3d9eb1 Reorganize tree so a single Makefile can do the right thing	4 年之前
max80.qsf	ac8a492ba2 sdram: fix 8-bit ports; rename fw/ to rv32/ to avoid confusion	3 年之前
max80.sdc	980eaf0400 Restructure clock tree; better sdram timing; random number generator	3 年之前
max80.sv	d64ebed344 rng: add the abc_clk to the inputs	3 年之前
max80jic.cof	ac8a492ba2 sdram: fix 8-bit ports; rename fw/ to rv32/ to avoid confusion	3 年之前
picorv32.v	ec99762a84 Use waitirq rather than suspending a memory transaction for SD card	4 年之前
rng.sv	da417c5ed7 rng: better LSFR handling	3 年之前
sdcard.sv	ec99762a84 Use waitirq rather than suspending a memory transaction for SD card	4 年之前
sdram.sv	ac8a492ba2 sdram: fix 8-bit ports; rename fw/ to rv32/ to avoid confusion	3 年之前
spi_master.sv	062a3d9eb1 Reorganize tree so a single Makefile can do the right thing	4 年之前
spirom.sv	cc37f87c67 sdram: rewrite as parameterized ports; usb: add USB core for testing	3 年之前
synchro.sv	f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again	4 年之前
sysclock.sv	0271d2cd06 abcrtc: ABC-bus interface to RTC (currently readonly)	4 年之前
tmdsenc.sv	74d9da52b0 hdmi/tmds: fix symbol data ordering	4 年之前
transpose.sv	510e702728 video: initial simple video generator; add support for HDMI TERC4	4 年之前
tty.sv	6ae39aaf12 Make romcopy device programmable and able to zero memory	4 年之前
video.sv	980eaf0400 Restructure clock tree; better sdram timing; random number generator	3 年之前