ABC80/max80_fw

H. Peter Anvin 09273c35a8 Wire up Smartaid Magnum in the FPGA		пре 1 година
..
bsdl	50f7f572a3 WIP: ringbuffer system between ESP32 and FPGA	пре 2 година
ip	80ad2f4a50 fpga: dirty bit tracking for SDRAM	пре 1 година
output	09273c35a8 Wire up Smartaid Magnum in the FPGA	пре 1 година
scripts	fcbaca5e17 iodevs.conf: move iodevs.conf into common/	пре 1 година
simulation	f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again	пре 3 година
usb	fcbaca5e17 iodevs.conf: move iodevs.conf into common/	пре 1 година
.gitignore	dd3e36cf74 fpga: remove intermediate files; update .fw files	пре 1 година
Makefile	fcbaca5e17 iodevs.conf: move iodevs.conf into common/	пре 1 година
abcbus.sv	09273c35a8 Wire up Smartaid Magnum in the FPGA	пре 1 година
assignment_defaults.qdf	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	пре 3 година
bootldr.sv	e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI	пре 2 година
bypass.pins	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	пре 2 година
bypass.qsf	0cf5cc5926 Update binaries	пре 1 година
bypass.sdc	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	пре 2 година
bypass.sv	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	пре 2 година
bypass_description.txt	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	пре 2 година
bypass_main.qsf	3b452dc33e fpga: factor bypass.qsf like the other .qsf files	пре 1 година
clkbuf.sv	808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs	пре 3 година
dcpktfifo.sv	bddbff2298 usb: don't remove "empty" or "last" while a packet is in progress	пре 2 година
deglitch.sv	a69847d434 fpga: add deglitcher core	пре 2 година
dirty.sv	80ad2f4a50 fpga: dirty bit tracking for SDRAM	пре 1 година
esp.sv	54aa67c9dd esplink: change to 7 interrupt/status bits per direction	пре 2 година
fast_mem.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	пре 2 година
fpgarst.sv	ee45852b85 Full infrastructure for updating flash via JTAG SVF	пре 2 година
functions.sv	54aa67c9dd esplink: change to 7 interrupt/status bits per direction	пре 2 година
i2c.sv	4970fb6ef6 rtc: issue dummy clock cycles if SDA appears stuck	пре 3 година
iodevs.vh	f9a7f7cbdb Update generated files	пре 1 година
jic.cof.xml	ee45852b85 Full infrastructure for updating flash via JTAG SVF	пре 2 година
max80.qpf	09273c35a8 Wire up Smartaid Magnum in the FPGA	пре 1 година
max80.qsf	80ad2f4a50 fpga: dirty bit tracking for SDRAM	пре 1 година
max80.sdc	8b67b5db30 spirom: fix SPI ROM I/O and data downloading	пре 2 година
max80.sv	09273c35a8 Wire up Smartaid Magnum in the FPGA	пре 1 година
picorv32.v	78fb11f073 fpga, rv32: Add custom atomic instructions lw.l/sw.u	пре 1 година
pof.cof.xml	ee45852b85 Full infrastructure for updating flash via JTAG SVF	пре 2 година
reconfig.svf	4803e910d3 fpga: .svf file to force a FPGA reconfiguration	пре 2 година
rng.sv	de1566292f clocks: centralize strobes; rng: shut down when not in use	пре 3 година
sam.sv	0f24359f94 sam.sv: correct A0 -> bank[0], A1 -> bank[1]	пре 1 година
sdcard.sv	ec99762a84 Use waitirq rather than suspending a memory transaction for SD card	пре 3 година
sdram.sv	80ad2f4a50 fpga: dirty bit tracking for SDRAM	пре 1 година
serial.sv	f1e04bf5c7 esp32 firmware image with support for OTA updates of both FPGA and ESP32	пре 2 година
spi_master.sv	062a3d9eb1 Reorganize tree so a single Makefile can do the right thing	пре 3 година
spirom.sv	ee45852b85 Full infrastructure for updating flash via JTAG SVF	пре 2 година
synchro.sv	4e65673781 spirom: add support for sending arbitrary SPI commands	пре 3 година
sysclock.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	пре 2 година
tmdsenc.sv	74d9da52b0 hdmi/tmds: fix symbol data ordering	пре 3 година
transpose.sv	510e702728 video: initial simple video generator; add support for HDMI TERC4	пре 3 година
ub.tcl	2ec75f1807 fpga: virtual JTAG interface	пре 2 година
v1.pins	aac953ed19 Implement FPGA <-> ESP32 communication path	пре 2 година
v1.qsf	f40bb6e0be Rebuild binaries with the proper version of the tools	пре 1 година
v1.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	пре 2 година
v1_description.txt	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	пре 3 година
v1_main.qsf	bddbff2298 usb: don't remove "empty" or "last" while a packet is in progress	пре 2 година
v2.pins	aac953ed19 Implement FPGA <-> ESP32 communication path	пре 2 година
v2.qsf	f40bb6e0be Rebuild binaries with the proper version of the tools	пре 1 година
v2.sv	e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI	пре 2 година
v2.vh	aac953ed19 Implement FPGA <-> ESP32 communication path	пре 2 година
v2_description.txt	75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA	пре 3 година
v2_main.qsf	bddbff2298 usb: don't remove "empty" or "last" while a packet is in progress	пре 2 година
v2boot.sv	e05dbe6f40 v2boot: simple boot loader connecting ESP32-SPI to flash-SPI	пре 2 година
video.sv	980eaf0400 Restructure clock tree; better sdram timing; random number generator	пре 3 година
vjtag_max80.sv	9ac4e30722 time: synchronize all clocks: RTC, SNTP, ESP, FPGA/ABC	пре 2 година