H. Peter Anvin bd347f1c79 serial: set baud rate to 921600 пре 3 година
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ip 8eec9b9e0a Timing improvements; allow SRAM to be read over JTAG пре 3 година
output 4b07e7703d Fix USB serial number generation пре 3 година
scripts 67a2a42fce fpga/Makefile: fix additional dependency generation issues пре 3 година
simulation f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again пре 3 година
usb 4b07e7703d Fix USB serial number generation пре 3 година
.gitignore 9471dad838 Move date stamp generation to fpga build; record SDRAM checksum пре 3 година
Makefile 8b67b5db30 spirom: fix SPI ROM I/O and data downloading пре 3 година
abcbus.sv a0f8eb5820 Fix false positive ABC-bus memory overrun timer пре 3 година
assignment_defaults.qdf 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA пре 3 година
clkbuf.sv 808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs пре 3 година
fast_mem.sv dd69eafb99 Many timing fixes; better IRQ handling for abcbus пре 3 година
functions.sv f2060589ab Default baud rate = 115200, baud rate programmable пре 3 година
i2c.sv 4970fb6ef6 rtc: issue dummy clock cycles if SDA appears stuck пре 3 година
iodevs.vh 7dd7eb2ed7 usb: change "console" to "tty", with CON_ used for only the console пре 3 година
max80-v1.cof 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA пре 3 година
max80-v2.cof 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA пре 3 година
max80.qpf 4b07e7703d Fix USB serial number generation пре 3 година
max80.qsf 8b67b5db30 spirom: fix SPI ROM I/O and data downloading пре 3 година
max80.sdc 8b67b5db30 spirom: fix SPI ROM I/O and data downloading пре 3 година
max80.sv 6014b9c6d7 max80: fix timing bug that affected code execution from SDRAM пре 3 година
picorv32.v 372899ea3b Move most code to SDRAM; fix problems with code in SDRAM; cleanups пре 3 година
rng.sv de1566292f clocks: centralize strobes; rng: shut down when not in use пре 3 година
sdcard.sv ec99762a84 Use waitirq rather than suspending a memory transaction for SD card пре 3 година
sdram.sv 0271d1979a sdram: return start to the right subunit; add ABC-bus latency counter пре 3 година
serial.sv bd347f1c79 serial: set baud rate to 921600 пре 3 година
spi_master.sv 062a3d9eb1 Reorganize tree so a single Makefile can do the right thing пре 3 година
spirom.sv 8b67b5db30 spirom: fix SPI ROM I/O and data downloading пре 3 година
synchro.sv 4e65673781 spirom: add support for sending arbitrary SPI commands пре 3 година
sysclock.sv 3dfb6626a1 More clock tree changes; fix rng oscillator sources пре 3 година
tmdsenc.sv 74d9da52b0 hdmi/tmds: fix symbol data ordering пре 3 година
transpose.sv 510e702728 video: initial simple video generator; add support for HDMI TERC4 пре 3 година
v1.pins 6db45e74e6 WIP: build both v1 and v2 пре 3 година
v1.qsf 29a9876c39 USB: I/O standards adjustment пре 3 година
v1.sv 60be2e1201 v2: v2 has a 16 MHz oscillator instead of 48 MHz пре 3 година
v1_description.txt 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA пре 3 година
v2.pins 20994e38da LED: change sequence of LED on v2 пре 3 година
v2.qsf 8b67b5db30 spirom: fix SPI ROM I/O and data downloading пре 3 година
v2.sv bda6055351 v2: SD card CD# signal needs rework пре 3 година
v2_description.txt 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA пре 3 година
video.sv 980eaf0400 Restructure clock tree; better sdram timing; random number generator пре 3 година