 H. Peter Anvin
|
3b452dc33e
fpga: factor bypass.qsf like the other .qsf files
|
il y a 1 an |
|
H. Peter Anvin
|
ff236177cc
fpga/max80.qsf: remove duplicate entry for esp.sv
|
il y a 2 ans |
|
H. Peter Anvin
|
053ccb0739
USB: fix data loss due to bad rewind on CRC error
|
il y a 2 ans |
|
H. Peter Anvin
|
5328aa117d
fpga: parameterize USB max packet size
|
il y a 2 ans |
|
H. Peter Anvin
|
50f7f572a3
WIP: ringbuffer system between ESP32 and FPGA
|
il y a 2 ans |
|
H. Peter Anvin
|
aac953ed19
Implement FPGA <-> ESP32 communication path
|
il y a 2 ans |
|
H. Peter Anvin
|
ee45852b85
Full infrastructure for updating flash via JTAG SVF
|
il y a 2 ans |
|
H. Peter Anvin
|
6375646603
update: get closer to a working JTAG update infrastructure
|
il y a 2 ans |
|
H. Peter Anvin
|
37de408c19
Allow the CPU to force an FPGA reload; vjtag improvement
|
il y a 2 ans |
|
H. Peter Anvin
|
2ec75f1807
fpga: virtual JTAG interface
|
il y a 2 ans |
|
H. Peter Anvin
|
8b67b5db30
spirom: fix SPI ROM I/O and data downloading
|
il y a 2 ans |
|
H. Peter Anvin
|
29a9876c39
USB: I/O standards adjustment
|
il y a 2 ans |
|
H. Peter Anvin
|
9471dad838
Move date stamp generation to fpga build; record SDRAM checksum
|
il y a 2 ans |
|
H. Peter Anvin
|
adf6c39024
serial: simplify physical tty and make BREAK reset work
|
il y a 2 ans |
|
H. Peter Anvin
|
7462426469
usb: use showahead on the Rx FIFO, but not the Tx FIFO
|
il y a 2 ans |
|
H. Peter Anvin
|
808ba7c43c
usb: use a direct interface between the CPU and the USB FIFOs
|
il y a 3 ans |
|
H. Peter Anvin
|
92d18543b8
tty: don't require DTR#; v2: output some clocks on gpio[135]
|
il y a 3 ans |
|
H. Peter Anvin
|
60be2e1201
v2: v2 has a 16 MHz oscillator instead of 48 MHz
|
il y a 3 ans |
|
H. Peter Anvin
|
08d8d7d2c8
More cleanups of multi-version... still broken?!
|
il y a 3 ans |
|
H. Peter Anvin
|
344ccf56d4
Fixes for dual version generator
|
il y a 3 ans |
|
H. Peter Anvin
|
6db45e74e6
WIP: build both v1 and v2
|
il y a 3 ans |
|
H. Peter Anvin
|
75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
|
il y a 3 ans |
|
H. Peter Anvin
|
c21293d687
usb: use generated USB descriptors
|
il y a 3 ans |
|
H. Peter Anvin
|
a99616cbc5
WIP: restructure USB using interfaces to be able to create more endpoints
|
il y a 3 ans |
|
H. Peter Anvin
|
3dfb6626a1
More clock tree changes; fix rng oscillator sources
|
il y a 3 ans |
|
H. Peter Anvin
|
ac8a492ba2
sdram: fix 8-bit ports; rename fw/ to rv32/ to avoid confusion
|
il y a 3 ans |
|
H. Peter Anvin
|
980eaf0400
Restructure clock tree; better sdram timing; random number generator
|
il y a 3 ans |
|
H. Peter Anvin
|
cc37f87c67
sdram: rewrite as parameterized ports; usb: add USB core for testing
|
il y a 3 ans |
|
H. Peter Anvin
|
0edc64a9c8
abcio, abcdisk: revamp callback interface, fix abcdisk state machine
|
il y a 3 ans |
|
H. Peter Anvin
|
4a0966e759
abcbus: put the I/O status register (INP 1) in a separate SRAM
|
il y a 3 ans |
