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ip
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06f36dc8f0
Merge remote-tracking branch 'origin/main' into slow
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il y a 3 ans |
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output
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06f36dc8f0
Merge remote-tracking branch 'origin/main' into slow
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il y a 3 ans |
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scripts
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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il y a 3 ans |
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simulation
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f24cac3c43
fpga: lint code to make ModelSim RTL simulation work again
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il y a 3 ans |
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usb
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808ba7c43c
usb: use a direct interface between the CPU and the USB FIFOs
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il y a 3 ans |
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.gitignore
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344ccf56d4
Fixes for dual version generator
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il y a 3 ans |
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Makefile
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6db45e74e6
WIP: build both v1 and v2
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il y a 3 ans |
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abcbus.sv
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81633591fa
v2: abc_host and abc_a_oe are redundant and unified in v2
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il y a 3 ans |
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assignment_defaults.qdf
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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il y a 3 ans |
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clkbuf.sv
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808ba7c43c
usb: use a direct interface between the CPU and the USB FIFOs
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il y a 3 ans |
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fast_mem.sv
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dd69eafb99
Many timing fixes; better IRQ handling for abcbus
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il y a 3 ans |
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functions.sv
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f2060589ab
Default baud rate = 115200, baud rate programmable
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il y a 3 ans |
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i2c.sv
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4970fb6ef6
rtc: issue dummy clock cycles if SDA appears stuck
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il y a 3 ans |
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iodevs.vh
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7c7d4cd52c
usb: set the device serial number
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il y a 3 ans |
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max80-v1.cof
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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il y a 3 ans |
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max80-v2.cof
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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il y a 3 ans |
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max80.qpf
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808ba7c43c
usb: use a direct interface between the CPU and the USB FIFOs
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il y a 3 ans |
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max80.qsf
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808ba7c43c
usb: use a direct interface between the CPU and the USB FIFOs
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il y a 3 ans |
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max80.sdc
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60be2e1201
v2: v2 has a 16 MHz oscillator instead of 48 MHz
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il y a 3 ans |
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max80.sv
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06f36dc8f0
Merge remote-tracking branch 'origin/main' into slow
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il y a 3 ans |
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picorv32.v
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372899ea3b
Move most code to SDRAM; fix problems with code in SDRAM; cleanups
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il y a 3 ans |
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rng.sv
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de1566292f
clocks: centralize strobes; rng: shut down when not in use
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il y a 3 ans |
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sdcard.sv
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ec99762a84
Use waitirq rather than suspending a memory transaction for SD card
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il y a 3 ans |
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sdram.sv
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63c8bc2ec8
sdram: fix signal timing that broke dram bss zeroing.
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il y a 3 ans |
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spi_master.sv
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062a3d9eb1
Reorganize tree so a single Makefile can do the right thing
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il y a 3 ans |
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spirom.sv
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808ba7c43c
usb: use a direct interface between the CPU and the USB FIFOs
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il y a 3 ans |
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synchro.sv
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4e65673781
spirom: add support for sending arbitrary SPI commands
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il y a 3 ans |
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sysclock.sv
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3dfb6626a1
More clock tree changes; fix rng oscillator sources
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il y a 3 ans |
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tmdsenc.sv
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74d9da52b0
hdmi/tmds: fix symbol data ordering
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il y a 3 ans |
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transpose.sv
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510e702728
video: initial simple video generator; add support for HDMI TERC4
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il y a 3 ans |
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tty.sv
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6ae39aaf12
Make romcopy device programmable and able to zero memory
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il y a 3 ans |
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v1.pins
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6db45e74e6
WIP: build both v1 and v2
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il y a 3 ans |
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v1.qsf
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08d8d7d2c8
More cleanups of multi-version... still broken?!
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il y a 3 ans |
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v1.sv
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60be2e1201
v2: v2 has a 16 MHz oscillator instead of 48 MHz
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il y a 3 ans |
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v1_description.txt
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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il y a 3 ans |
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v2.pins
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60be2e1201
v2: v2 has a 16 MHz oscillator instead of 48 MHz
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il y a 3 ans |
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v2.qsf
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08d8d7d2c8
More cleanups of multi-version... still broken?!
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il y a 3 ans |
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v2.sv
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92d18543b8
tty: don't require DTR#; v2: output some clocks on gpio[135]
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il y a 3 ans |
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v2_description.txt
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75a6dbc7fa
fpga: infrastructure for building v1 and v2 FPGA
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il y a 3 ans |
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video.sv
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980eaf0400
Restructure clock tree; better sdram timing; random number generator
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il y a 3 ans |
H. Peter Anvin
06f36dc8f0
Merge remote-tracking branch 'origin/main' into slow