H. Peter Anvin 06f36dc8f0 Merge remote-tracking branch 'origin/main' into slow %!s(int64=3) %!d(string=hai) anos
..
ip 06f36dc8f0 Merge remote-tracking branch 'origin/main' into slow %!s(int64=3) %!d(string=hai) anos
output 06f36dc8f0 Merge remote-tracking branch 'origin/main' into slow %!s(int64=3) %!d(string=hai) anos
scripts 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA %!s(int64=3) %!d(string=hai) anos
simulation f24cac3c43 fpga: lint code to make ModelSim RTL simulation work again %!s(int64=3) %!d(string=hai) anos
usb 808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs %!s(int64=3) %!d(string=hai) anos
.gitignore 344ccf56d4 Fixes for dual version generator %!s(int64=3) %!d(string=hai) anos
Makefile 6db45e74e6 WIP: build both v1 and v2 %!s(int64=3) %!d(string=hai) anos
abcbus.sv 81633591fa v2: abc_host and abc_a_oe are redundant and unified in v2 %!s(int64=3) %!d(string=hai) anos
assignment_defaults.qdf 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA %!s(int64=3) %!d(string=hai) anos
clkbuf.sv 808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs %!s(int64=3) %!d(string=hai) anos
fast_mem.sv dd69eafb99 Many timing fixes; better IRQ handling for abcbus %!s(int64=3) %!d(string=hai) anos
functions.sv f2060589ab Default baud rate = 115200, baud rate programmable %!s(int64=3) %!d(string=hai) anos
i2c.sv 4970fb6ef6 rtc: issue dummy clock cycles if SDA appears stuck %!s(int64=3) %!d(string=hai) anos
iodevs.vh 7c7d4cd52c usb: set the device serial number %!s(int64=3) %!d(string=hai) anos
max80-v1.cof 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA %!s(int64=3) %!d(string=hai) anos
max80-v2.cof 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA %!s(int64=3) %!d(string=hai) anos
max80.qpf 808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs %!s(int64=3) %!d(string=hai) anos
max80.qsf 808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs %!s(int64=3) %!d(string=hai) anos
max80.sdc 60be2e1201 v2: v2 has a 16 MHz oscillator instead of 48 MHz %!s(int64=3) %!d(string=hai) anos
max80.sv 06f36dc8f0 Merge remote-tracking branch 'origin/main' into slow %!s(int64=3) %!d(string=hai) anos
picorv32.v 372899ea3b Move most code to SDRAM; fix problems with code in SDRAM; cleanups %!s(int64=3) %!d(string=hai) anos
rng.sv de1566292f clocks: centralize strobes; rng: shut down when not in use %!s(int64=3) %!d(string=hai) anos
sdcard.sv ec99762a84 Use waitirq rather than suspending a memory transaction for SD card %!s(int64=3) %!d(string=hai) anos
sdram.sv 63c8bc2ec8 sdram: fix signal timing that broke dram bss zeroing. %!s(int64=3) %!d(string=hai) anos
spi_master.sv 062a3d9eb1 Reorganize tree so a single Makefile can do the right thing %!s(int64=3) %!d(string=hai) anos
spirom.sv 808ba7c43c usb: use a direct interface between the CPU and the USB FIFOs %!s(int64=3) %!d(string=hai) anos
synchro.sv 4e65673781 spirom: add support for sending arbitrary SPI commands %!s(int64=3) %!d(string=hai) anos
sysclock.sv 3dfb6626a1 More clock tree changes; fix rng oscillator sources %!s(int64=3) %!d(string=hai) anos
tmdsenc.sv 74d9da52b0 hdmi/tmds: fix symbol data ordering %!s(int64=3) %!d(string=hai) anos
transpose.sv 510e702728 video: initial simple video generator; add support for HDMI TERC4 %!s(int64=3) %!d(string=hai) anos
tty.sv 6ae39aaf12 Make romcopy device programmable and able to zero memory %!s(int64=3) %!d(string=hai) anos
v1.pins 6db45e74e6 WIP: build both v1 and v2 %!s(int64=3) %!d(string=hai) anos
v1.qsf 08d8d7d2c8 More cleanups of multi-version... still broken?! %!s(int64=3) %!d(string=hai) anos
v1.sv 60be2e1201 v2: v2 has a 16 MHz oscillator instead of 48 MHz %!s(int64=3) %!d(string=hai) anos
v1_description.txt 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA %!s(int64=3) %!d(string=hai) anos
v2.pins 60be2e1201 v2: v2 has a 16 MHz oscillator instead of 48 MHz %!s(int64=3) %!d(string=hai) anos
v2.qsf 08d8d7d2c8 More cleanups of multi-version... still broken?! %!s(int64=3) %!d(string=hai) anos
v2.sv 92d18543b8 tty: don't require DTR#; v2: output some clocks on gpio[135] %!s(int64=3) %!d(string=hai) anos
v2_description.txt 75a6dbc7fa fpga: infrastructure for building v1 and v2 FPGA %!s(int64=3) %!d(string=hai) anos
video.sv 980eaf0400 Restructure clock tree; better sdram timing; random number generator %!s(int64=3) %!d(string=hai) anos